JPH06197291A - Biphase data decoding circuit - Google Patents

Abstract

PURPOSE:To attain decoding of vari-phase data with simple configuration, to obtain decoded data not affected by jitter and to attain detection of a synchronization pattern by obtaining a decode clock without use of a PLL circuit. CONSTITUTION:A decoding circuit is made up of an A/D converter 1 A/D- converting a MUSE signal, a comparator 2 binarizing an output from the A/D converter 1 at a center level, a frequency divider 4 applying 172 frequency division to a sampling clock from the A/D converter l, a D flip-flop 3 latching a binarized output from the comparator 2 with an output of the frequency divider 4, a frequency divider 8 applying 1/6 frequency division to a frequency division output of the frequency divider 4 by sampling the MUSE signal per bit, and an exclusive logic circuit 9 receiving an output of the flip-flop 3 and a frequency division output from the circuit 8. Thus, no PLL circuit is required when the MUSE signal is decoded and the operation such as alignment and adjustment is not required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bi-phase data decoding circuit which can be used in a MUSE type high-definition video disc player, and more particularly to a format of a control address signal recorded on a muse type high-definition video disc. The present invention relates to a bi-phase data decoding circuit that decodes bi-phase data having the following.

[0002]

2. Description of the Related Art The format of a control address signal recorded on a muse HDTV video disk is as shown in FIG. One line period consists of 480 samples, and 1 to 11 samples are 1 in the horizontal synchronization period (shown as the HD period in FIG. 4A).
7 samples from 2 to 18 samples are low level, 19
It is assigned to a control address signal as data from the sample, and there is an n-bit sync pattern at the beginning of the data, and the first bit is defined as "1". 6 samples (16.2 MHz clock) are set to 1 bit, and as shown in FIG.
For 1〃, 3 samples are recorded at low level and 3 consecutive samples are recorded as high level. As shown in Fig. 4 (c), for 3〃, 3 samples are recorded at high level and 3 consecutive samples are recorded as low level. To be done.

Bi-phase data encoded in this way is recorded on a high-definition video disk, and when reading and decoding such bi-phase data, conventionally, an edge of the bi-phase data is detected and the edge is PLL circuit. It is being supplied to the clock to be regenerated.

[0004]

However, when the above method is used, not only is the circuit scale increased, but
In addition to the problem that the number of adjustment points increases, there was the problem that phase matching between the demodulated clock and biphase data was difficult.

An object of the present invention is to provide a bi-phase data decoding circuit which can demodulate bi-phase data by an all digital circuit without using a PLL circuit and other analog circuits.

[0006]

A biphase data decoding circuit according to the present invention divides a sample clock of a muse signal by a frequency division ratio based on the number of samples of the muse signal corresponding to 1 bit of the biphase data and biphases it. A first exclusive means for inputting a frequency dividing means for generating a data decoding clock, a binarizing means for binarizing the muse signal at its center level, and an output from the binarizing means and an output from the frequency dividing means. And a logical sum operation means, and the output of the first exclusive OR operation means is the decoded data.

The bi-phase decoding circuit of the present invention comprises a latch pulse generating means for outputting a latch pulse at each of the first half and the latter half of the output of the frequency dividing means, and an output latch pulse from the latch pulse generating means. A first latching means for latching the output from the first exclusive OR operation means, and a first latch instead of the output of the first exclusive OR operation means
It is characterized in that the output of the latch means is the decoded data.

The bi-phase decoding circuit of the present invention has a second latch means for latching the output of the first latch means with an output latch pulse from the latch pulse generating means, and an output from the first and second latch means. Second exclusive-OR operation means, and coincidence detection means for detecting that the data based on the output of the second latch means coincides with the sync pattern,
The logical product of the error flag non-detection means for detecting that a predetermined number of signals based on the output from the second exclusive OR operation means does not continuously occur, the output of the coincidence detection means and the detection output of the error flag non-detection means And a logical product computing means for computing, and the output of the logical product computing means is a sync pattern detection output.

[0009]

In the bi-phase decoding circuit of the present invention, the bi-phase data decoding clock is divided by the frequency dividing means for dividing the sample clock of the muse signal by a frequency division ratio based on the number of samples of the muse signal corresponding to 1 bit of the bi-phase data. Is reproduced, the muse signal is binarized by the binarizing means at its center level, and the output binarized by the binarizing means and the output from the frequency dividing means are exclusive in the first exclusive OR operation means. An OR operation is performed and the muse signal is decoded. This decoding does not require a PLL circuit or the like, and phase matching and adjustment are almost unnecessary.

Further, a latch pulse is output from the latch pulse generating means at substantially the center of each of the first half and the second half of the output of the frequency dividing means, and the latch pulse is output from the first exclusive OR operation means by the first latch means by this latch pulse. Is latched, and the latched output is output as decoded data instead of the output of the first exclusive OR calculation means. Therefore, even if the binarized output fluctuates with time due to jitter, the decoding can be performed without being affected by the jitter.

The output of the first latch means is latched by the second latch means by the output latch pulse from the latch pulse generating means, and the output of the first and second latch means is input from the second exclusive OR operation means. An error signal is output, and the coincidence detection means detects that the data based on the output of the second latch means coincides with the sync pattern. Further, the error flag non-detection means detects that a predetermined number of error signals are not continuously generated, and the sync pattern is detected by the logical product operation of the output of the coincidence detection means and the detection output of the error flag non-detection means by the logical product operation means. Output is output.

[0012]

EXAMPLES The present invention will be described below with reference to examples. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

The muse signal a read from the HDTV disc is digitized by the A / D converter 1 into 8 to 10 bits. The digitized muse signal a is binarized at the center level by the comparator 2. In this embodiment, the A / D conversion clock supplied to the A / D converter 1 is 32.4 MHz, which is twice the sample clock of the muse signal. Clock d that is synchronized with the / D conversion clock and has the same frequency as the sample clock of the muse signal
And output b from comparator 2 at clock d
Are latched in the D flip-flop 3, and the latch output is used as the input data e.

The frequency division output of the frequency divider 4 is used as a clock d, and D
The inverted output e ′ of the flip-flop 3 is counted by the 4-bit binary counter 5 only during the high potential period, and the counter 5 is cleared when the inverted output e ′ of the D flip-flop 3 becomes low potential. Therefore, the output f of the fourth bit of the counter 5 becomes high potential when the input data e becomes low potential continuously for 9 samples (at 16.2 MHz clock) or more. The NAND gate 6 performs an AND operation on the output f of the fourth bit of the counter 5 and the input data e.

The clock d is supplied to the frequency dividing circuit 8 which is cleared by the output g of the NAND gate 6 and frequency-divided by 6. This frequency-divided output is decoded clock h for biphase data.
And On the other hand, the input data e is supplied to the 4-bit shift register 7 and delayed by 4 pulses of the clock d to compensate for the phase shift due to the insertion of the counter 5, and the shift register 7
Output i and the decode clock h are supplied to the exclusive OR circuit 9, and the output of the exclusive OR circuit 9 is used as the decoded data j to obtain the decoded data.

Here, the frequency dividing circuit 8 outputs a latch pulse k which rises at a substantially central position of each half cycle period of the decoded clock h. FIG. 2 is a timing chart showing the output of the frequency dividing circuit 8, and FIG. 2 (a) shows the clock d,
2B shows the output g of the NAND gate 6 inputted as a clear pulse, FIG. 2C shows the day code clock h, and FIG. 2D shows the latch pulse k.

The decoded data j is latched by the D flip-flop 10 by the latch pulse k. Here, since the latch pulse k is output twice per 1 bit of the decoded data j as described above, it should be latched in the D flip-flop 10 at the time of the substantially central position of the first half and the latter half of the decoded data j. become.

The latch pulse k is the D flip-flop 11
To the latch output l of the D flip-flop 10.
(L) is latched by the D flip-flop 11 with a latch pulse k
Latched by to obtain the latch output m of the D flip-flop 11. The latch output m may be decoded data, and the latch output m is also referred to as decoded data m. l
Alternatively, when m is used as the decoded data, it is necessary to perform the subsequent processing in consideration of the fact that the latch pulse k is output twice per 1 bit of the decoded data.

The inverted outputs l (ell) 'and m'of the D flip-flops 10 and 11 are supplied to the exclusive OR circuit 14 to perform an exclusive OR operation and output as an error signal r. The decoded data m is latched in the D flip-flop 12 at the rising edge of the decode clock h, and the latch output is output as the data p. The error signal r is latched in the D flip-flop 13 at the rising edge of the decode clock h, and the latch output is latched by the error flag s.
Output as.

The data p is converted into n-bit parallel data t by the shift register 15 having the same number of bits as the sync pattern bit number n, and the comparator 16 compares the sync pattern with the bit pattern of the parallel data t to match. Then, the comparator 16 outputs the coincidence signal u.

On the other hand, the error flag s also corresponds to the shift register 1
7, the parallel signal v is converted into an n-bit parallel signal v, and the parallel signal v is NOR-operated in the NOR gate 18 to check whether an error has occurred in consecutive n bits. The output w of the NOR gate 18 has a high potential only when no error occurs in n bits.

The coincidence signal u and the output w from the comparator 16 are ANDed in the AND gate 19 and output as a sync pattern detection signal x.

In the present embodiment constructed as described above,
The frequency divider 4 outputs a clock d synchronized with the A / D conversion clock c and having the same frequency as the sample clock of the muse signal. On the other hand, the A / D converter 1 samples the muse signal a by the A / D conversion clock c,
Converted to digital data. This digital data is binarized at the center level by the comparator 2. Two
The binarized signal is latched by the D flip-flop 3 and the input data e is output.

Therefore, the muse signal is converted by the A / D converter 1 and the comparator 2D flip-flop 3 into the input data e which is binarized at the center level.

The clock d is counted by the counter 5, the counter 5 is chip-selected by the inverted input data e ', and is cleared by the inverted data of the inverted data e', so that the output f of the counter 5 becomes high potential. This is when the input data e is continuously low level for 9 samples or more by the 16.2 MHz clock. In this case, in the 564 line, only immediately after the HD period,
That is, this state occurs only when the first 1 bit of the control address signal from the sample number 12 in FIG.

Therefore, the NAND gate 6 can AND the output f and the input data e to specify the latter half of the first bit of the control address signal. The frequency divider 8 is cleared by the output g of the NAND gate 6, and the clock d is generated in the frequency divider 8.
Is divided by six. The reason why the frequency is divided by 6 is that one bit is specified by 6 samples. The output divided by 6 becomes the decode clock h.

Since the phase of the decode clock h is delayed by the counter 5 with respect to the input data e, the input data e is delayed by 4 samples by the shift register 7, and the phase is matched by this delay. ,
The output i is in phase. Here, in effect, the decode clock h is a decode clock that combines biphase data.

The output i and the decode clock h are subjected to the exclusive OR operation in the exclusive OR circuit 9 to obtain the decoded data j. Of course, the decoded data j may be taken out as an output.

When output as the decoded data j, the input data e may change due to the influence of jitter or the like, and the edge may shift by about one sample. For this,
As shown in FIG. 3A, the input data e has a deviation. In FIG. 3A, the solid line shows the actual input data e, and the broken line shows the original input data e when there is no jitter. FIG. 3B shows the decode clock h. As a result, the decoded data j has an error as shown by the broken line in FIG.

Therefore, at the timing shown in FIG. 2 (d) and FIG. 3 (d) from the frequency divider circuit 8, the latch pulse k
Is output, and the decoded data j is D by the latch pulse k.
It is latched in the flip-flop 10. Therefore, since the first half and the second half of the decoded data j are latched at the substantially central positions thereof, the latch output 1 (ell) is not affected by the jitter. Therefore, the latch output l (L) of the D flip-flop 10 may be output as the decoded data instead of the decoded data j.

The output 1 (L) is latched in the D flip-flop 11 by the latch pulse k. The latch output m of the D flip-flop 11 is also not affected by the jitter. Therefore, the latch output m of the D flip-flop 10 may be output as the decoded data instead of the decoded data j and the latch output 1 (L).

Further, since the decoded data j is latched twice by the D flip-flops 10 and 11 as described above, the exclusive OR circuit 14 latches the output l.
The error signal r is obtained by taking the exclusive OR of (ell) and m. Here, the decrypted data is 〃1〃, 〃0
Since it is output as the data of "", the error signal r becomes a high potential when the first half part and the second half part of the decoded data are different, which indicates that there is an error.

Next, the latch output m and the error signal r
By the decode clock h.
The data p and the error flag s are obtained at the same timing by being latched respectively in and.

On the other hand, since there is an n-bit sync pattern at the beginning of the control address signal, the data p is converted into n-bit parallel data t by the shift register 15 by the decode clock h, and the sync pattern by the comparator 16. And a match is detected.

Since the error flag s is output with a high probability except for 546 lines, the error flag s is converted into n-bit parallel data v by the shift register 17 by the decode clock h, and the converted parallel data v is NOR operation is performed in the NOR gate 18. Therefore, during the n bits, when the error flag s is continuously at the low level, the output of the NOR gate 18 becomes the high level, and it is detected that the error has not continued for n bits.

The coincidence detection output u from the comparator 16 and the output w from the NOR gate 18 are logically ANDed to output a sync pattern detection output x.

[0037]

As described above, according to the bi-phase data decoding circuit of the present invention, a decode clock can be obtained without using a PLL circuit, and bi-phase data can be decoded with a simple configuration. In addition, the phase adjustment is not complicated and the number of adjustment points is small.

There is also an effect that decoded data that is not affected by jitter can be obtained. Furthermore, there is an effect that the sync pattern can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 4 is a schematic diagram showing the format of bi-phase encoded control address data.

[Explanation of symbols]

 1 A / D converter 2 and 16 Comparator 3, 10-13 D flip-flop 4 Frequency divider 5 Counter 6 NAND gate 7 4-bit shift register 8 Frequency divider circuit 9 and 14 Exclusive OR circuit 15 and 17 Shift register 18 NOR gate 19 And gate

Claims (3)

[Claims] 1. A frequency division means for dividing a sample clock of a muse signal by a frequency division ratio based on the number of samples of the muse signal corresponding to 1 bit of the biphase data, and a muse signal. Is provided with a binarizing means for binarizing the signal at the center level thereof, and a first exclusive OR operation means for inputting an output from the binarizing means and an output from the frequency dividing means, and a first exclusive OR operation A bi-phase data decoding circuit characterized in that the output of the means is decoded data. 2. The bi-phase data decoding circuit according to claim 1, wherein the latch pulse generating means outputs the latch pulse at substantially the center positions of the first half and the second half of the output of the frequency dividing means, and the latch pulse generating means. And a first latch means for latching the output from the first exclusive OR operation means by the output latch pulse of the first exclusive OR operation means, and the output of the first latch means is used as the decoded data instead of the output of the first exclusive OR operation means. A bi-phase data decoding circuit characterized by: 3. The bi-phase data decoding circuit according to claim 2, wherein the second latch means for latching the output of the first latch means by the output latch pulse from the latch pulse generating means, and the first and second latch means. To the output of the second exclusive OR operation means, the coincidence detection means for detecting that the data based on the output of the second latch means coincides with the sync pattern, and the output from the second exclusive OR operation means. An error flag non-detecting means for detecting that a predetermined number of consecutive signals are not generated, and a logical product calculating means for performing a logical product operation on the output of the coincidence detecting means and the detection output of the error flag non-detecting means. A biphase data decoding circuit, characterized in that the output of the product calculation means is a sync pattern detection output.