JP2550755B2 - Bit synchronization judgment circuit - Google Patents

Description

The present invention relates to a bit synchronization determination circuit used in a bit synchronization circuit for a PCM bit stream signal.

[Conventional technology]

Conventionally, this type of bit synchronization determination circuit is composed of an independent bit synchronization determination circuit and a bi-phase (Biφ) code ambiguity circuit. The bit synchronization determination circuit is composed of an analog circuit, and integrates the number of coincidence of the symbol timing and the phase of the internal clock, and makes a determination through a comparator. The Biφ code ambiguity circuit is composed of a digital circuit, and when the first half 1/2 symbol data and the latter half 1/2 symbol data in one bit continue as the same symbol state to some extent, the internal clock is inverted, Sync ambiguity was removed.

[Problems to be Solved by the Invention]

The above-mentioned conventional bit synchronization determination circuit requires an independent bit synchronization determination circuit and a Biφ code ambiguity circuit. Moreover, depending on the data content at the time of the Biφ code, a 1-bit data section is erroneously detected. Nevertheless, there is a drawback in that bit locking may be determined.

[Means for solving the problem]

The bit synchronization determination circuit of the present invention includes a register that outputs input data with a delay of half a symbol cycle, and outputs the input data as it is when the input data is NRZ data and when the input data is biphase data. A buffer that inverts and outputs the input data, an adder circuit that inputs the output of the buffer and the output of the register, and an absolute value of the output data of the adder circuit in the first half of the cycle of the synchronization clock of the input data. An arithmetic circuit that outputs with a minus sign and outputs the absolute value of the output data of the adder circuit in the latter half, an integrating circuit that adds the data output by this arithmetic circuit for a predetermined period, and the output data of this integrating circuit And a predetermined first threshold value are compared, and a comparison result is output as information indicating the synchronization / asynchronization of the synchronization clock. And a second comparison circuit for comparing the output data of the integration circuit with a predetermined second threshold, and the synchronous clock based on the comparison result of the second comparison circuit. And a logic circuit for inverting and eliminating code ambiguity of biphase data.

 The arithmetic circuit may be a ROM arithmetic circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, 1 is a register circuit for input signals, 2
Is a 3-state buffer circuit, 3 is a 3-state inversion buffer circuit, 4 is an inversion circuit, 5 is an adder circuit for the former and latter half symbols, 6 is a ROM operation circuit, 7 is an adder circuit for integration, and 8 is a register with clear. A circuit, 9 is a comparison circuit for LOCK judgment, 10 is a comparison circuit for Biφ code ambiguity judgment, 11 is a register circuit for status output, 12 is an n frequency divider, and 13 is an exclusive logic circuit.

FIGS. 2 (a) and 2 (b) are timing charts when unlocked and locked when the PCM signal input in the embodiment of FIG. 1 is NRZ data, and FIGS. 2 (c) and (d). ) Is a flowchart at the time of unlocking and locking at the same time when it is bi-phase data.

The input PCM signal is latched in the register 1 at the rising edge of the doubled internal clock signal. Data output in the first half and 3-state buffer 2 for NRZ signals
In the case of the Biφ signal, the adder 5 adds the latter half data output through the 3-state buffer 3. The absolute value of this addition result is obtained by the ROM calculator 6.

Now, in the NRZ data, the data is 0,1,0,1,0,1 ……
Assuming that there is a data change as described above, the result becomes 0 when the latter half data B0 of 0 and the first half data A1 of the next 1 are added. In this way, the comparison data C obtained by adding the second half data and the first half data on both sides of the data boundary to obtain the absolute value
Then, when the normal symbol data S obtained by adding the first half data and the second half data in the data section are added over n symbols, S = | A0 + B0 | + | A1 + B1 | + | A0 + B0 | + ... = n K (| A0 + B0 | = | A1 + B1 | = K) C = | B0 + A1 | + | B1 + A0 | + | B0 + A1 | + ... = 0 (| B0 + A1 | = | B1 + A0 | = 0). See Figure 3 for definitions of A0, B0, A1 and B1.

Here, when the adder circuit 5 outputs each term of C,
That is, when the synchronous clock is at a high level, the output of the adder 7 for integration becomes "S-C" by taking the 2's complement in the ROM arithmetic circuit 6, and the n-minute cycle 12 divides the synchronous clock by n and registers. Immediately before 8 is cleared, the contents of register 8 are SC = | A0 + B0 |-| B0 + A1 | + | A1 + B1 | = nK.

The value of S-C becomes smaller as the rate of data change (data transition density) becomes lower, but if there is a certain degree of transition, it is possible to determine bit synchronization by comparing the value of S-C with the threshold value.

Therefore, the comparator 9 compares the output of the register 8 after integrating S-C for n symbol intervals with a preset bit lock threshold value to make a bit synchronization lock determination.

In the case of Biφ data as well, lock determination can be performed in the same manner as NRZ data. If the Biφ data is locked by shifting by 1/2 symbol, the value of S−C becomes negative, and this can be used to remove the Biφ code ambiguity. First, the comparator 10 compares the output of the register 8 with a preset negative threshold value for removing the ambiguity of Biφ by the comparator 10 to determine the pseudo-lock state of Biφ data. When the pseudo lock is determined,
The exclusive clock circuit 13 inverts the timing of the symbol clock, and apparently shifts by 1/2 symbol to obtain a normal locked state. With this method, it is possible to remove the ambiguity during the bi-phase simultaneously with the bit lock determination.

〔The invention's effect〕

As described above, according to the present invention, the normal symbol data obtained by adding the former half symbol data and the latter half symbol data in one symbol to obtain the absolute value, and Add the difference data between the half symbol data of the former symbol and the half symbol data of the latter half of the latter symbol and the comparison data that is the absolute value by adding the half symbol data of the latter symbol centered around the boundary of the latter symbol Then, the bit synchronization can be determined by comparing with the first threshold value, and only the second comparison circuit and the logic circuit which inverts the synchronization clock are added to each circuit necessary for determining the bit synchronization. At the time of Biφ code, there is an effect that code ambiguity can be removed at the same time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are input in the embodiment of FIG.
Timing charts for unlocking and locking when the PCM signal is NRZ data, FIGS. 2 (c) and 2 (d) are timing charts for unlocking and locking when bi-phase data are used, and FIG. The figure is a diagram for explaining the definitions of A0, B0, A1, and B1 in the embodiment of FIG. 1 ... Register circuit, 2 ... 3-state buffer circuit, 3 ... 3-state inversion buffer circuit, 4 ... Inversion circuit, 5 ... Addition circuit, 6 ... ROM operation circuit, 7 ... Addition circuit, 8 ... Register circuit, 9,10 ... Comparison circuit, 11 ...
… Register circuit, 12 …… n frequency divider circuit, 13 …… Exclusive OR circuit.

Claims (2)

(57) [Claims] 1. A register for outputting input data delayed by a half cycle of a symbol period, the input data being output as it is when the input data is NRZ data, and the input data being output when the input data is biphase data. A buffer that inverts and outputs, an adder circuit that inputs the output of this buffer and the output of the register, and in the first half of the cycle of the synchronous clock of the input data, the absolute value of the output data of the adder circuit is taken and a negative sign is added. In the latter half, an arithmetic circuit that takes the absolute value of the output data of the adder circuit and outputs it, an integrating circuit that adds the data output by this arithmetic circuit for a predetermined period, and the output data of this integrating circuit and the predetermined value A first comparison circuit that outputs a comparison result obtained by comparing the first threshold value as information indicating synchronization / asynchronization of the synchronization clock. And a second comparison circuit that compares the output data of the integration circuit with a predetermined second threshold value, and the synchronous clock is inverted based on the comparison result of the second comparison circuit to generate the biphase data. And a logic circuit for removing the code ambiguity of the bit synchronization determination circuit. 2. The bit synchronization determination circuit according to claim 1, wherein the arithmetic circuit is a ROM arithmetic circuit.