JPH06189555A - Three-value level inverter controller - Google Patents

Abstract

PURPOSE:To improve reliability in a three-value level inverter controller, by forming a simple structure that protects series connected switching elements from concurrent switching operation even if a direct-shift command from a mode '1' to a mode '-1' is generated. CONSTITUTION:A three-level inverter controller includes a mode direct-shift detecting circuit 18 for detecting the timing when an output of a control command 17 is shifted directly from a mode '1' to a mode '-1' and vice versa, and a mode-'0' inserting circuit 19 for inserting, upon output from that circuit 18, a mode '0' between these shifting modes of the control command 17 during the time (Ts) that is previously set and not less than a minimum feasible time of switching for transistors 2 to 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary level inverter control device which operates by employing, for example, a pulse width modulation method.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing the structure of a conventional three-level inverter control device of this type. In the figure,
1 is a DC power supply, 2 to 5 are transistors as switching elements connected in series between the positive side terminal P and the negative side terminal N of the DC power supply 1, and 6 to 9 are transistors 2 to 5 respectively. Anti-parallel connected diodes, 1
Reference numerals 0 and 11 are capacitors connected in series between the positive side terminal P and the negative side terminal N, and the connection point between them is drawn out as the midpoint terminal 0. 12 is transistors 2 and 3
Is a diode connected between the connection point of and and the midpoint terminal 0 with the polarity shown, and 13 is a diode connected between the connection point of the transistors 4 and 5 and the midpoint terminal 0 with the polarity shown. is there.

In the figure, a portion surrounded by a dotted line is a unit inverter 15 having 14 as an output terminal. In the case of a single-phase inverter, two unit inverters 15 are connected in parallel to the DC power source 1 to form U and V. A single-phase AC voltage is obtained from each output terminal 14. Further, in the case of a three-phase inverter, three unit inverters 15 are connected in parallel to the DC power supply 1, and a three-phase AC voltage is obtained from each of the U, V, and W output terminals 14. A PWM control circuit 16 supplies a gate signal to each of the transistors 2 to 5 based on a control command 17.

Next, the operation will be described. Now, assuming that the voltage between the DC terminals P and N is 2 Ed, the capacitors 10 and 1
The charging voltage of 1 is Ed, which is equal to each other. In this state, the potential of the output terminal 14 can be changed by switching the switching states (ON and OFF) of the transistors 2 to 5. When the voltage for a single phase generated between the output terminal 14 and the midpoint terminal 0 is V _UO , the level changes as shown in the table of FIG. 6 depending on the switching states of the transistors 2 to 5.

As shown in FIG. 6, the three-level inverter can output three kinds of voltages according to the switching states of the transistors. That is, when a switching state in which V _UO = Ed (this is referred to as mode 1),
And _UO = 0 and becomes mode 0, become mode (-1) V _UO = -Ed.

In an actual device, one of the three modes is sequentially selected and switched based on the control command 17 so as to obtain a desired AC output voltage, and ON / OFF control of each of the transistors 2 to 5 is performed by pulse width modulation. Is to translate.

[0007]

The conventional three-value level inverter control device is configured as described above, and the switching state is the mode 1 depending on the control method applied.
From the mode to the mode (-1) or directly from the mode (-1) to the mode 1 may occur. For example, JP-A-3-
When performing the capacitor voltage control described in Japanese Patent No. 293971, the switching state changes from mode 1 to mode (-1) or from mode (-1) depending on the voltage states of the capacitors 10 and 11 shown in FIG. It may change to mode 1.

When the switching state changes as described above, it is necessary that the transistors 2 and 3 connected in series with each other and the transistors 4 and 5 are changed from on to off or from off to on at the same time. in this way,
In order to switch the transistors connected in series at the same time, it is necessary to exactly match the rising and falling times of the gate signal to each transistor. This is because if there is a deviation in these times, an overvoltage is applied to one of the transistors connected in series, the voltage duty becomes non-uniform, and the reliability deteriorates. Therefore, special consideration must be given to the design of the PWM control circuit 16 that creates the gate signal to the transistor, resulting in a complicated and expensive device.

The present invention has been made in order to solve the above problems, even if the mode 1 to the mode (-
Even if a direct transfer command such as 1) is issued,
An object of the present invention is to obtain a three-value level inverter control device having a simple structure and high reliability.

[0010]

In the three-level inverter control device according to the present invention, the output of the control command is from mode 1 to mode (-1) or from mode (-1) to mode 1.
When there is an output from the mode direct transition detection means for detecting the timing of direct transition to the mode direct transition detection means, the mode 0 is set to the minimum switching of the switching element between the direct transition modes of the output of the control command. It is provided with a mode 0 inserting means for inserting a preset time which is longer than the possible time.

[0011]

According to the present invention, when a command to directly switch the switching state from the mode 1 to the mode (-1) is issued, this is detected and the mode 0 of the mode 0 having the minimum time width necessary for the switching operation is detected. An operation is inserted and, for example, the mode 1 is switched to the mode 0 to the mode (-1).

[0012]

EXAMPLES Example 1. 1 is a circuit diagram showing the configuration of a three-level inverter control device according to a first embodiment of the present invention. In the figure, the same parts as those of the related art are designated by the same reference numerals and the description thereof will be omitted. The output of control command 17 is mode 1 for 18
To a mode (-1) or from a mode (-1) to a mode 1 directly detects a mode direct transition detection circuit, 19 operates by a signal from the mode direct transition detection circuit 18 and outputs a control signal of mode 0. This is a mode 0 insertion circuit to be inserted.

Next, the operation will be described with reference to the flowchart of FIG. This is performed by S / W processing by a microcomputer or DSP, and while inputting the control command 17, the time is monitored by using a timer built in the microcomputer or an external device, and the current time is the time when the switching state of the transistor changes. That is, it is determined whether or not the time has come to change the mode (S
1). If it is not at the time of mode change (NO in S1), the gate signal corresponding to the mode at that time is output (S2). If it is the time of mode change (YES in S1), it is determined whether the mode change is from mode 1 to mode (-1) or from mode (-1) to mode 1. (S3).

If the flow of S3 is NO, that is, the mode change is mode 1 → mode 0, mode 0 → mode (-
1), mode (−1) → mode 0 or mode 0 → mode 1, the gate signal corresponding to the changed mode is output as it is (S4). If the flow of S3 is YES, that is, if the mode change is either mode 1 → mode (−1) or mode (−1) → mode 1, the switching state is set to mode 0 (S5),
The output time is set to T _S (S6), and the gate signal corresponding to mode 0 is output (S7). Where time T
_{As S} , a value that is as small as possible is set for a minimum switching time of the transistor or longer.

FIG. 3 is a time chart showing the gate signals g1, g2, g3 and g4 to the transistors 2 to 5 when a change from mode 1 to mode (-1) is detected.
As can be seen from this figure, the same change time point of the gate signal g2 that should change from H to L at the same time as the gate signal g1 should be delayed by the time T _S. Similarly, the gate signal g4 which should originally change from L to H at the same time as the gate signal g3
The same change point of is delayed by the time T _S. FIG. 4 is a time chart showing a gate signal to each transistor when a change from mode (-1) to mode 1 is similarly detected.

As a result, since there is no simultaneous switching command for the series elements, the problem of non-uniform voltage duty that may occur due to uncertainties in the switching timing of both elements is solved, and reliability is improved. In addition, although the output voltage waveform is changed strictly by the insertion of the mode 0,
Since the insertion time T _S of the mode 0 according to the present invention can be set sufficiently small as compared with the duration of one mode originally commanded, there is no problem.

Although the operation of the unit inverter 15 has been described above, as described above, when two or three unit inverters 15 are connected in parallel to operate as a single-phase or three-phase inverter, each phase is operated. The processing described above may be performed for each of them.

Example 2. Although the case where the transistor is used as the switching element has been described in the first embodiment, the present invention is not limited to this, and may be a GTO, an IGBT, or the like.

Example 3. In the above embodiment, mode 0
Although the S / W process is used to insert the above, each functional element may be configured by H / W.

[0020]

As described above, the present invention is provided with the predetermined mode direct shift detecting means and the mode 0 inserting means. Therefore, even when a direct shift command such as from mode 1 to mode (-1) is issued. Even in this case, it is possible to avoid simultaneous switching of the series-connected switching elements with a simple configuration, and reliability is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a three-level inverter control device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the three-value level inverter control device of FIG.

FIG. 3 is a time chart showing a gate signal in FIG. 1 when a control command for direct transition from mode 1 to mode (−1) is issued.

FIG. 4 is a time chart showing a gate signal in FIG. 1 when a control command for direct transition from mode (−1) to mode 1 is issued.

FIG. 5 is a circuit diagram showing a configuration of a conventional three-level inverter control device.

FIG. 6 is a table showing a relationship between a switching state (mode) of a transistor and an output voltage V _UO in a three-level inverter.

[Explanation of symbols]

 1 DC power supply P Positive side terminal N Negative side terminal 2-5 Transistors 6-9, 12, 13 Diode 10, 11 Capacitor 0 Midpoint terminal 14 Output terminal 15 Unit inverter 16 PWM control circuit 17 Control command 18 Mode direct shift detection circuit 19 Mode 0 insertion circuit

Claims (1)

[Claims] 1. A capacitor having a midpoint terminal connected between DC terminals, four switching elements connected in series between the DC terminals, and antiparallel connected to each of the switching elements. A diode, and a diode connected between the connection point of the two switching elements on the DC positive side and the connection point of the two switching elements on the DC negative side, and the midpoint terminal of the capacitor, respectively. A three-value level inverter for obtaining an output voltage from a central connection point of the four switching elements, wherein the output voltage is a positive level based on a control command, a mode 1 is a negative level mode (-1), and a zero level. Mode 0
In the three-value level inverter control device that sequentially selects and switches any of the above, and controls the switching of each of the switching elements according to each mode, the output of the control command is from mode 1 to mode (-1) or from mode (-1). When there is an output from the mode direct transition detection means for detecting the timing of direct transition to the mode 1, and the output from this mode direct transition detection means, the mode 0 is set to the switching element between the direct transition modes of the output of the control command. And a mode 0 insertion means for inserting a preset time that is equal to or longer than the minimum switchable time of the three-value level inverter control device.