JP3104736B2 - Bridge type inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bridge type, a half bridge type or a polyphase inverter device.

[0002]

2. Description of the Related Art When a switch of a bridge type inverter for converting DC to AC is turned on / off, switching loss occurs. To solve this kind of problem, partial resonance is used to switch the switch to ZCS (Zero Current Switching) or ZVS.
(Zero voltage switching) has been proposed to reduce switching loss, surge voltage and noise. However, there is a demand for an inverter device capable of reliably and easily reducing the loss of not only the main switch but also the partial resonance switch.

Accordingly, an object of the present invention is to provide a bridge type inverter device which can meet the above demand.

[0004]

In order to achieve the above object, the invention according to claim 1 will be described with reference to the reference numerals in the drawings showing an embodiment. Switch circuits are connected to each other, and a current in a first direction and a second current opposite to the first direction are supplied to the load by the switch circuits.
In a bridge-type or half-bridge-type or multi-phase bridge-type inverter device configured to flow a current in the direction of, the switch circuit is connected between one end and the other end of the DC power supply 1. Second main switch TR1
, TR2 and first and second auxiliary switches S1, S2 connected between one end and the other end of the DC power supply 1.
2 and the first and second switches TR1,
First and second diodes D connected in anti-parallel to TR2
1, D2 and the first and second auxiliary switches S1, S2
A third and a fourth diode D3 connected in anti-parallel to
D4 and the first and second main switches TR1, TR2.
And the first and second auxiliary switches S1
, S2 and a resonance capacitor C1 connected between the interconnection middle points of the first and second auxiliary switches S3 and S4 in parallel with the resonance capacitor C1 via an anti-parallel circuit of third and fourth auxiliary switches S3 and S4. And a resonance reactor L1
And first and second main control pulses for controlling the first and second main switches TR1 and TR2 and first, second, third and fourth auxiliary switches (S1, S2, S3,
The present invention relates to an inverter device provided with a control circuit for generating first, second, third and fourth auxiliary control pulses for controlling S4). According to a second aspect, the control circuit of the first aspect includes first and second control circuits.
Are alternately generated with a predetermined time interval Ta therebetween, and the predetermined time interval Ta
Is set to a time width corresponding to 0 to 90 degrees or more of the sinusoidal resonance current waveform based on 1 and the reactor L1, and at the same time as or before the trailing edge of the first control pulse, Second and fourth moving switches S2, S4
Is turned on, the second auxiliary switch S2 is turned off at the same time as or after the leading edge of the second main control pulse, and the second auxiliary switch S2 is turned on.
From the point at which the switch is turned off.
When the time corresponding to the section of .about.180 degrees has elapsed, the fourth auxiliary switch S4 is naturally or forcibly switched to the off state, and is simultaneously or before the trailing edge of the second main control pulse. At this time, the first and third auxiliary switches S1
, S3 are turned on, and at the same time as or after the leading edge of the first main control pulse, the first auxiliary switch S1 is turned off, and the first auxiliary switch S1 is turned off. The third auxiliary switch S3 is naturally or forcibly switched to the off state when a time corresponding to the section of 90 to 180 degrees of the resonance current waveform elapses from the time when the switch is turned off. Is desirable. According to a third aspect of the present invention, one or a plurality of switch circuits are connected between one end and the other end of the DC power supply, and a current in a first direction and a second current opposite thereto are supplied to the load by the switch circuits. In a bridge-type, half-bridge-type, or multi-phase bridge-type inverter device configured to flow a current in the direction of, at least one of the switch circuits is connected between one end and the other end of the DC power supply 1. The first and second main switches (TR1, TR2) comprise a series circuit of first and second main switches TR1, TR2.
A) a main conversion circuit having a connection midpoint connected to a load, and a series circuit of first and second auxiliary switches S1 and S2 connected between one end and the other end of the DC power supply 1. First and second diodes D1, D2 connected in anti-parallel to the first and second switches TR1, TR2, and third and second diodes D1, D2 connected in anti-parallel to the first and second auxiliary switches S1, S2. Fourth diodes D3 and D4, and fifth and sixth diodes D3 and D4 connected between one end and the other end of the DC power supply 1 in the same direction as the third and fourth diodes D3 and D4. And a series circuit of diodes Da and Db
A resonance capacitor C1 connected between an interconnection point of the second main switches TR1 and TR2 and an interconnection point of the fifth and sixth diodes Da and Db; A reactor L1 connected between an interconnection midpoint of the main switches TR1 and TR2 of the first and second sub-switches S1 and S2;
And third and fourth auxiliary switches S3, connected between the interconnection midpoint of the second and third auxiliary switches S1, S2 and the interconnection midpoint of the fifth and sixth diodes Da, Db.
S4 and a capacitor charging circuit connected in parallel with the fifth diode Da or the sixth diode Db, and for controlling the first and second main switches TR1 and TR2. For controlling the first and second main control pulses and the first, second, third and fourth auxiliary switches (S1, S2, S3, S4). And a control circuit for generating the auxiliary control pulse. According to a fourth aspect of the present invention, the control circuit of the third aspect generates the first and second main control pulses alternately with a predetermined time interval Ta therebetween, and the predetermined time interval T
a is set to a time width corresponding to 0 to 90 degrees or more of the sinusoidal resonance current waveform based on the capacitor C1 and the reactor L1, and at the same time as or after the trailing edge of the first main control pulse. At the previous time, the second and fourth auxiliary switches S2 and S4 are turned on, and the second and fourth auxiliary switches S2 and S4 are turned on.
At the same time as or after the leading edge of the main control pulse, the second auxiliary switch S2 is turned off, and the resonance current waveform starts from the time when the second auxiliary switch S2 is turned off. When the time corresponding to the 90 to 180 degree section has elapsed, the fourth auxiliary switch S4 is turned off naturally or forcibly, and simultaneously with or after the trailing edge of the second main control pulse. The first and third auxiliary switches S1 and S3 are controlled to be turned on at an earlier time, and the first auxiliary switch S1 is controlled at the same time as or after the leading edge of the first main control pulse. Is turned off, and the third auxiliary switch S3 is turned on when a time corresponding to the 90 to 180 degree section of the resonance current waveform has elapsed since the first auxiliary switch S1 was turned off.
Preferably, it is configured to naturally or forcibly turn the switch off. In the invention according to claim 6, at least one switch circuit is connected between one end and the other end of the DC power supply, and a current in a first direction and a second current opposite thereto are supplied to the load by the switch circuit. In a bridge-type, half-bridge-type, or multi-phase bridge-type inverter device configured to flow a current in one direction, the first and second switch circuits are connected between one end and the other end of the DC power supply 1. 2 main switch TR1 and a series circuit of TR2, the first and second main switches (TR1
, TR2) and a series circuit of a first and a second auxiliary switch S1, S2 connected between one end and the other end of the DC power supply 1, and a main conversion circuit having an interconnection midpoint connected to a load. And first and second diodes D1, D2 connected in anti-parallel to the first and second switches TR1, TR2.
And a series connection of a third and a fourth diode D3, D4 connected between one end and the other end of the DC power supply 1 in the same direction as the first and second diodes D1, D2. A first and second auxiliary switch S1, S2 arranged in a series circuit and connected in series with each other between the first and second auxiliary switches S1, S2. Of the first and second reactors L1a and L1b and the third and third reactors L1a and L1b.
And a resonance capacitor C1 connected between the interconnection point of the fourth diodes D3 and D4, and a third auxiliary switch connected in parallel to the first reactor L1a and the capacitor C1. S3, a fourth auxiliary switch S4 connected in parallel to the second reactor L1b and the capacitor C1 with a direction opposite to that of the third auxiliary switch S3, Diode D3
Or a capacitor charging circuit 7 connected in parallel with the fourth diode D4 and for controlling the first and second main switches TR1, TR2.
And first, second, third, and fourth auxiliary controls for controlling the second main control pulse and the first, second, third, and fourth auxiliary switches (S1, S2, S3, S4). The present invention relates to an inverter device provided with a control circuit for generating pulses. According to a seventh aspect, the control circuit of the sixth aspect generates the first and second main control pulses alternately with a predetermined time interval Ta therebetween.
The predetermined time interval Ta is equal to the time between the capacitor C1 and the second
Of the sinusoidal resonance current waveform based on the reactor L1b
The second auxiliary switch S2 is turned on at the same time as or before the trailing edge of the first control pulse.
At the same time as or after the leading edge of the second main control pulse, the second auxiliary switch S2 is turned off, and the leading edge of the second main control pulse and the second auxiliary switch S2 are controlled. The fourth auxiliary switch S4 is turned on between the time when the switch S2 is turned off and the 90-180 degree section of the resonance current waveform between the capacitor C1 and the second reactor L1b from this time. At the point in time when the time corresponding to elapses, the fourth auxiliary switch S4 is naturally or forcibly turned off, and at the same time as or before the trailing edge of the second main control pulse, the fourth auxiliary switch S4 is turned off. The first auxiliary switch S1 is turned on, and the first auxiliary switch S1 is turned off at the same time as or after the leading edge of the first main control pulse. The leading edge of the main control pulse and the first complement The third auxiliary switch S3 is turned on between the time when the auxiliary switch S1 is turned off, and the capacitor C1, the first reactor L1a, the 90-180 degree section of the resonance current waveform from this time. It is desirable that the third auxiliary switch S3 be naturally or forcibly switched to the off state at the time when the time corresponding to has elapsed. It is desirable to provide a charging circuit for the capacitor C1 as described in claims 5 and 8.

[0005]

According to the invention of each claim, the first aspect is as follows.
The resonance current can be made to flow accurately by the functions of the fourth to fourth auxiliary switches S1 to S4, and the ZVS effect of the first and second main switches TR1 and TR2 can be reliably obtained. The ZV of the first to fourth auxiliary switches S1 to S4
An S or ZCS effect can also be obtained. In addition, ZVS or ZCS is a simple circuit that does not use the midpoint potential of the DC power supply.
The effect can be obtained.

[0006]

First Embodiment Next, a bridge type inverter device according to a first embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, this inverter device is configured to convert a DC voltage of a DC power supply 1 into an AC by a bridge type inverter circuit and supply the AC to a load 2. The DC power supply 1 includes a rectifier circuit or a battery, and the load 2 includes, for example, an output transformer 3 and a load circuit 4 connected thereto.

The inverter circuit includes first, second, third, and fourth main switches TR1,
TR2, TR3, TR4 and the first, second, third, fourth,
Fifth, sixth, seventh and eighth diodes D1, D2, D
, D4, D5, D6, D7, D8, as well as the first, second, third, fourth, fifth, sixth, seventh and eighth auxiliary switches S1, S2, S3, S4, S5, S6, S7,
S8, the first and second capacitors C1, C2, and the first
And second reactors L1 and L2.

The first to fourth main switches TR1 to TR4 and the first, second, fifth and sixth auxiliary switches S1, S2
, S5 and S6 are constituted by bipolar transistors. However, the third, fourth, seventh and eighth auxiliary switches S3, S4, S7, S8 are constituted by thyristors. The first main switch TR1 is connected between one end of the power supply 1 and one end of the load 2, the second main switch TR2 is connected between one end of the load 2 and the other end of the power supply 1, The main switch TR3 is connected between one end of the power supply 1 and the other end of the load 2, and the fourth main switch TR4 is connected between the other end of the load 2 and the other end of the power supply 1. The series circuit of the first and second main switches TR1 and TR2 functions as a first main conversion circuit, and the series circuit of the third and fourth main switches TR3 and TR4 functions as a second main conversion circuit.

First, second, third, fourth, fifth, sixth, seventh and eighth diodes D1, D2, D3, D4, D5
, D6, D7, D8 are the first and second main switches TR1
, TR2, the first and second auxiliary switches S1, S2, the third and fourth main switches TR3, TR4, and the fifth and sixth auxiliary switches S5, S6 are connected in parallel in the reverse direction. The first to fourth main switches TR1 to TR1
TR4 and the first, second, fifth and sixth auxiliary switches S
In the case where 1, S2, S5 and S6 are insulated gate (MOS) field effect transistors having a structure in which the sources are connected to the substrate, the diodes incorporated therein can be D1 to D8. .

The first and second auxiliary switches S1 and S2 are connected in series between one end and the other end of the power supply 1, and the fifth and sixth auxiliary switches S5 and S6 are also connected to one end of the power supply 1 and the other. The terminals are connected in series with each other. The third and fourth auxiliary switches S3, S4 form an anti-parallel circuit with each other, which is connected via the first reactor L1 to the interconnection point of the first and second main switches TR1, TR2 with the first and the second. The two auxiliary switches S1 and S2 are connected between the interconnection middle points. First capacitor C1
Is connected in parallel to the anti-parallel circuit of the third and fourth auxiliary switches S3 and S4 and the series circuit of the first reactor L1. The fifth and sixth auxiliary switches S5 and S6 are connected in series between one end and the other end of the power supply 1. The seventh and eighth auxiliary switches S7 and S8 form an anti-parallel circuit, and this anti-parallel circuit is connected via a second reactor L2 to the middle point of the interconnection of the third and fourth main switches TR3 and TR4. The fifth and sixth auxiliary switches S5 and S6 are connected between the interconnection middle points. The second capacitor C2 is connected between the interconnection midpoint of the third and fourth main switches TR3, TR4 and the interconnection midpoint of the fifth and sixth auxiliary switches S5, S6. In FIG. 1, a first switch circuit (first
And a second switch circuit (second half-bridge circuit) 5b surrounded by a dotted line on the right side of the load 2 have the same configuration.

In FIG. 1, some of the interconnecting lines are omitted for the sake of illustration, but each of the switches TR1 to TR4
, S1 to S8 have their control terminals (bases) or gates connected to the control circuit 6. As shown in FIG. 2, the control circuit 6 includes first, second, third, and fourth main control pulse generation circuits 7, 8, 9, 10, and first to eighth auxiliary control pulse generation circuits. Circuits 11, 12, 13, 14, 15, 16, 1
7 and 18, an oscillator 19, and a phase control circuit 20. The first and second main control pulse generation circuits 7 and 8 are controlled by the oscillator 19 to generate the first and second main control pulses shown in FIGS. To the bases of the main switches TR1 and TR2. The third and fourth main control pulse generation circuits 9 and 10 are controlled by the oscillator 19 and the phase control circuit 20 to generate the third and fourth main control pulses shown in FIGS. It supplies to the bases of the third and fourth main switches TR3, TR4. The first and second main control pulses and the third and fourth main control pulses are the same except that they have a phase difference therebetween. FIG. 3 (A)
The first and second main control pulses of FIG. 3B alternately occur with a time interval Ta, and the third and fourth main control pulses of FIGS. 3C and 3D also have a time interval Ta. And occur alternately. This time interval Ta is determined by the auxiliary switches S3, S4, S7 while the capacitors C1, C2 are charged.
, S8 are turned on, and the time required until almost all of the charges of C1 and C2 are released in the resonance operation is set. That is, Ta is set to a time width of 0 to 90 degrees or more of the sinusoidal resonance current waveform.

First and third auxiliary control pulse generating circuits 1
1, 13 are connected to the second main control pulse generation circuit 8,
As shown in FIGS. 3 (E) and 3 (G), a pulse longer than the mutual time interval (dead time) Ta of the main control pulse is synchronized with the trailing edge time t6 of the second main control pulse in FIG. 3 (B). Occur. The width of the first auxiliary control pulse supplied to the first auxiliary switch S1 is the width from time t6 to at least time t7 in FIG. 3 and before the trailing edge time t12 of the first main control pulse. Desirably the width. The width of the third auxiliary control pulse supplied to the third auxiliary switch S3 is the width from time t6 to at least the trailing edge time t8 of the first auxiliary control pulse and the width of the third auxiliary control pulse after the first main control pulse. It is desirable that the width be before the edge time t12. The second and fourth auxiliary control pulse generation circuits 14 are connected to the first main control pulse generation circuit 7, and the second and fourth auxiliary control pulse generation circuits 7
As shown in FIG. 3H, a pulse longer than the mutual time interval (dead time) Ta is generated in synchronization with the trailing edge time t0 of the first main control pulse in FIG. The width of the second auxiliary control pulse supplied to the second auxiliary switch S2 is t0 in FIG.
It is desirable that the width be from the time point to at least the time point t1 and before the trailing edge time point t6 of the second main control pulse. Also, a fourth auxiliary switch S
4, the width of the fourth auxiliary control pulse is from at time t0 to at least the trailing edge time t2 of the second auxiliary control pulse, and the width of the trailing edge time t2 of the second main control pulse.
It is desirable that the width be less than 6. 5th to 8th
The auxiliary control pulse generation circuits 15 to 18 are connected to the third and fourth main control pulse generation circuits 10 as shown in FIG. 2, and the first and second main control of the first to fourth auxiliary control pulses are performed. The fifth to eighth auxiliary control pulses are formed such that a relationship similar to the relationship between the pulses is obtained between the third and fourth main control pulses.

[0013]

[Operation] The basic operation of the inverter circuit shown in FIG. 1 is the same as that of a known inverter. That is, while the first and fourth main switches TR1 and TR4 are simultaneously turned on, a current in the first direction is generated by a circuit including the power supply 1, the first main switch TR1, the load 2, and the fourth main switch TR4. Flow to load 2
During the period when the third main switches TR2 and TR3 are simultaneously turned on, a current in the second direction flows through the load 2 by a circuit including the power supply 1, the third main switch TR3, the load 2, and the second main switch TR2. .

Next, the first to fourth main switches TR1 to TR
The operation of R4 during the turn-on and turn-off periods will be described. However, the operation during the period of turning off the first main switch TR1 and the period of turning on the second main switch TR2 shown at t0 to t3 in FIG. 3, the turning off of the second main switch TR2 shown at t6 to t9 and the first The operation during the turn-on period of the main switch TR1, the operation during the turn-off period of the third main switch TR3 and the turn-off of the fourth main switch TR4, the turn-off operation of the fourth main switch TR4 and the third main switch TR3 Since the operation during the turn-off period is substantially the same, the operation during the period t0 to t3 in FIG. 3 will be described in detail with reference to FIG. 4, and the description of the operation during the other periods will be omitted.

[0015]

[Capacitor charging operation] In this embodiment, the first and second capacitors are charged.
It is necessary to charge the capacitors C1 and C2 in advance, for example, in the direction shown in FIG. In order to perform this charging, the second and fifth auxiliary switches S2 and S5 are turned on in synchronization with the ON periods of the first and fourth main switches TR and TR4. Of course, the first auxiliary switch S1 and the second
And the third main switch TR3 and the sixth auxiliary switch S6 can be simultaneously turned on. Since the charging energy of the capacitors C1 and C2 repeats the resonance operation with L1 and L2 and decreases with the lapse of time due to the loss, the first, second, third, and so on are sometimes used.
S2, S1 in synchronization with the fourth main switches TR1 to TR4.
, S5 and S6 are turned on to replenish energy.

[0016]

[Turn-off and turn-on operations] FIG. 4 shows the state of each part of FIG. 1 in the section from t0 to t3 in FIG. 3 and the vicinity thereof when the load circuit 4 is unloaded and the load 2 is a delayed load of only a transformer. When the first main switch TR1 is turned off at time t0 when the first capacitor C1 is almost charged to the power supply voltage V, and the second and fourth auxiliary switches are turned on, the first capacitor C1 is charged. When the energy is between the first capacitor C1, the first reactor L1 and the fourth
And the voltage Vc1 of the first capacitor C1 drops in a 90-180 degree sine wave section as shown in FIG. 4 (F). At this time, since the second auxiliary switch S2 is on, the voltage Vc1 of the first capacitor C1 is applied to both ends of the second main switch TR2, and as shown in FIG. From t1 to t1, the voltage Vtr2 of the second main switch TR2 decreases toward zero. Also, the first main switch TR1
Of the second main switch TR2 from the power supply voltage V
4G, and gradually rises as shown in FIG. 4 (G). The first capacitor C1 and the first capacitor
The resonance current I1 of the closed circuit composed of the reactor L1 and the fourth auxiliary switch S4 is from t0 to t0 as shown in FIG.
In the interval t1, the sine wave flows with a waveform in the range of 0 to 90 degrees. At time t1, the voltage Vc1 of the first capacitor C1
Becomes zero, the reverse bias of the second diode D2 is released, and the current I1 due to the release of the stored energy of the first reactor L1 is commutated to the second auxiliary switch S2,
The first reactor L1, the fourth auxiliary switch S4 and the second
Flows as a circulating current through the closed circuit of the auxiliary switch S2 and the second diode D2. During the period from t1 to t2, the voltage of the first capacitor C1 is zero volt, and the voltage Vtr2 of the second main switch TR2 is also zero volt. Therefore,
When the second main switch TR2 is turned on at, for example, t1 selected from the period from t1 to t2, ZVS is achieved. At t0, the ZVS of the first main switch TR1 is achieved. When the second auxiliary switch S2 is turned off at time t2 after the time t1 at which the second main switch TR2 is turned on, the first
The resonance between the reactor L1 and the first capacitor C1 occurs again, and the first capacitor C1 is charged in the opposite direction to that in FIG. 1, and the voltage Vc1 changes toward -V as shown in FIG. I do. As shown in FIG. 4 (E), the resonance current I1 changes with a sine wave in the 90-180 degree section between t2 and t3, and becomes zero at the time t3. Fourth auxiliary switch S
Since 4 is a thyristor, it has a function of turning off naturally when the current becomes zero. In FIG. 4, the ON control time width of the fourth auxiliary switch S4 is set to t0 to t3.
It is also possible to use an on-control pulse shorter than this, and to generate this short on-control pulse as a trigger signal in synchronization with time t0. FIG. 4 shows the fourth auxiliary switch S4.
Although the resonance current I1 of (E) flows, it turns on and off when the currents of t0 and t3 are zero, so that the switching loss is substantially zero. Also, the current at the turn-on time t0 of the second auxiliary switch S2 is zero, and ZCV is achieved, and since this voltage Vs2 gradually increases from the turn-off time t2, ZVS is achieved.

As is apparent from the above description, when the first main switch TR1 is turned off and the second main switch TR2 is turned on, ZVS is achieved to reduce the switching loss, and the second auxiliary switch S2 is connected to ZVS, Since the fourth auxiliary switch S4 is turned on / off by ZCS,
Switching loss here is also reduced.

When the second main switch TR2 is turned off, the first and third auxiliary switches S1, S3 are turned on, and the resonance of the first capacitor C1, the third auxiliary switch S3, and the first reactor L1. A circuit is formed. In this circuit, a current I1 corresponding to the interval t0 to t1 and t2 to t3 in FIG. 4 flows, and a current corresponding to the interval t1 to t2 in FIG. 4 is supplied to the first reactor L1 and the first reactor L1. Diode D
1 and the first auxiliary switch S1 and the third auxiliary switch S3
And the same operation and effect as in FIG. 4 can be obtained. Further, the same operation as in the first switch circuit 5a occurs in the second switch circuit 5b.

In FIG. 4, the load is described as no load.
Can be regarded as a resistance, a current corresponding to the voltage applied to the load 2 is applied to the first to fourth main switches TR1 to TR4.
Flow through. At this time, even if the storage current of the main switches TR1 to TR4 flows, the voltage immediately after the turn-off time changes sinusoidally, so that the power loss based on the product of the current and the voltage is small. When the load 2 is a delay load including an inductance, for example, the first main switch T
When R1 is turned off, the current (stored energy) flowing to the load 2 is calculated from the load 2, the second capacitor C2, the seventh auxiliary switch S7, the power supply 1, the fourth diode D4, and the first capacitor C1. When the first and second capacitors C1 and C2 are completely discharged, the second and fifth diodes D2 and D5 become forward biased, and the load 2, the fifth diode D5 and the power supply 1 It flows in the circuit of the second diode D2. When the load 2 is an advanced load, the first main switch TR1 is turned on during the ON period of the first main switch TR1.
The first main switch TR1 is turned off while the current is flowing through the diode D1, and the second and fourth auxiliary switches S2 are turned off.
, S4 are turned on, the load 2 and the first reactor L1
, A fourth auxiliary switch S4, a third diode D3, a power supply 1, an eighth diode D8, and a seventh auxiliary switch S.
When a current flows through a circuit composed of the first and second reactors L1 and L2 and the currents of the first and second reactors L1 and L2 rise until they become equal to the load current, the diodes D1 and D6
Cut off.

[0020]

Second Embodiment Next, a bridge-type inverter device according to a second embodiment of the present invention will be described with reference to FIGS. However, in FIG. 5 and FIGS. 7 to 11 described later, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. The inverter circuit of FIG. 5 further includes two resonance circuit forming diodes Da and Db, which can be referred to as fifth and sixth diodes, to the inverter circuit of FIG.
The capacitor C1 and the third and fourth auxiliary switches S3, S
4 is changed, and a charging circuit 7 is further provided.

The series circuit of the two diodes Da and Db is connected between one end of the power supply 1 and the other end. The capacitor C1 is connected between the interconnection point of the first and second main switches TR1, TR2 and the interconnection point of the diodes Da, Db. Reactor L1 is connected between the interconnection point of the first and second main switches TR1, TR2 and the interconnection point of the first and second auxiliary switches S1, S2. Third and fourth auxiliary switches S3, S4
Are connected to the first and second auxiliary switches S1 and S2.
Is connected between the middle point of the interconnections of the diodes Da and Db. The charging circuit 7 includes a resistor or a switch, and is connected to the diode Db in parallel.

The bridge type inverter device shown in FIG.
And a combination of a first switch circuit (first half bridge circuit) 5a on the left side and a second switch circuit (second half bridge circuit) 5b on the right side of the load 2. First
Since the second switch circuits 5a and 5b have the same circuit configuration, the second switch circuits 5a and 5b have the same circuit configuration in FIG. 5 and FIG.
A detailed description of the switch circuit 5b will be omitted.

[0023]

[Operation] The basic operation of the inverter circuit of FIG. 5 is the same as that of the inverter of FIG. That is, while the first and fourth main switches TR1 and TR4 are simultaneously turned on, a current in the first direction is generated by a circuit including the power supply 1, the first main switch TR1, the load 2, and the fourth main switch TR4. Flow to load 2
During the period when the third main switches TR2 and TR3 are simultaneously turned on, a current in the second direction flows through the load 2 by a circuit including the power supply 1, the third main switch TR3, the load 2, and the second main switch TR2. .

Next, the first to fourth main switches TR1 to T
The operation during the turn-on and turn-off periods of R4 is shown in FIG. 6 showing the period corresponding to the period t0 to t3 in FIGS.
This will be described with reference to FIG. Note that the turn-off and turn-on operations in the other sections are substantially the same as those in FIG. 6, and a description thereof will be omitted.

[0025]

[Capacitor charging operation] In this embodiment, the first and second capacitors are charged.
It is necessary to charge the capacitors C1 and C2 in advance in, for example, the direction shown in FIG. To perform this charging, the first main switch TR1 is turned on before starting the inverter operation. Thus, the capacitor C1 is charged by the circuit including the first main switch TR1, the capacitor C1, and the charging circuit 7. The decrease in the charge of the capacitor C1 due to the loss during the repetition of the resonance operation is supplemented during the ON period of the first main switch TR1 during the operation of the inverter.

[0026]

[Turn-off and turn-on operations] FIG. 6 shows the state of each part in FIG. 5 when the load circuit 4 is unloaded and the load 2 is a delayed load of only a transformer. First capacitor C
1 is substantially charged to the power supply voltage V, t
At time 0, when the first main switch TR1 is turned off and the second and fourth auxiliary switches are turned on, the energy of the first capacitor C1 is changed to the first capacitor C1, the first reactor L1, and the second Auxiliary switch S2 and diode D
6 and the first capacitor C
As shown in FIG. 6F, the voltage Vc1 of 1
It decreases in the waveform of the 180-degree section. At this time, the diode D
6 is on, the voltage Vc1 of the first capacitor C1 is applied to both ends of the second main switch TR2, and the second main switch TR2 is switched between t0 and t1 as shown in FIG. The voltage Vtr2 of the switch TR2 decreases toward zero.
The voltage Vtr1 of the first main switch TR1 has a value obtained by subtracting the voltage Vtr2 of the second main switch TR2 from the power supply voltage V, and slowly rises as shown in FIG. As shown in FIG. 6E, the resonance current I1 of the series resonance circuit of the first capacitor C1 and the first reactor L1 flows with a waveform of a sine wave of 0 to 90 degrees in the interval t0 to t1. . When the voltage Vc1 of the first capacitor C1 becomes zero at the time t1, the reverse bias of the second diode D2 is released, and the current I1 due to the release of the stored energy of the first reactor L1 becomes equal to the first reactor L1 and the second reactor L1.
Flows as a circulating current through the closed circuit of the auxiliary switch S2 and the second diode D2. During the period from t1 to t2, the voltage of the first capacitor C1 is zero volt, and the voltage Vtr2 of the second main switch TR2 is also zero volt. Therefore,
When the second main switch TR2 is turned on at, for example, t1 selected from the period from t1 to t2, ZVS is achieved. At t0, the ZVS of the first main switch TR1 is achieved. When the second auxiliary switch S2 is turned off at time t2 after the time t1 at which the second main switch TR2 is turned on, the first
The LC series resonance occurs again due to the closed circuit of the reactor L1, the fourth auxiliary switch S4, and the first capacitor C1, and the first capacitor C1 is charged in the opposite manner to FIG. It changes toward -V as shown in F). The resonance current I1 is between t2 and t2 as shown in FIG.
During the period t3, the sine wave changes in the 90-180 degree section, and becomes zero at the time t3. Since the fourth auxiliary switch S4 is a thyristor, it has a function of turning off naturally when the current becomes zero. In FIG. 6, the ON control time width of the fourth auxiliary switch S4 is from t0 to t3. However, an ON control pulse shorter than this is used, and this short ON control pulse is used as a trigger signal to synchronize at the time t0, t1, or t2. Can also be generated. The resonance current I1 shown in FIG. 6E flows through the fourth auxiliary switch S4.
Since switching on and off at zero current at 0, t3, switching losses are substantially zero. Further, the current at the turn-on time t0 of the second auxiliary switch S2 is zero and ZCS is achieved, and the voltage Vs2 gradually increases from the turn-off time t2 as shown in FIG. ZVS is achieved.

As is apparent from the above, when the first main switch TR1 is turned off and the second main switch TR2 is turned on, ZVS is achieved to reduce switching loss, and the second auxiliary switch S2 is connected to the ZCS and Since the ZVS and the fourth auxiliary switch S4 are turned on and off by the ZCS, the switching loss here is also reduced.

When the second main switch TR2 is turned off, the first and third auxiliary switches S1 and S3 are turned on, and the first capacitor C1, the diode Da, the first auxiliary switch S1 and the first reactor L1 are turned on. Is formed, a current I1 corresponding to the interval t0 to t1 in FIG. 6 flows through the circuit, and a current I1 corresponding to the interval t1 to t2 in FIG. 6 is supplied to the first reactor L1 and the first reactor L1. The resonance current I1, which flows through a closed circuit composed of the diode D1 and the first auxiliary switch S1 and corresponds to the section between t2 and t3 in FIG. 6, is the reactor L1, the capacitor C1, and the third auxiliary switch S1.
3, and the same operation and effect as in FIG. 6 can be obtained. A similar operation occurs in the second switch circuit 5b.

In FIG. 6, the load is described as no load.
Can be regarded as a resistance, a current corresponding to the voltage applied to the load 2 is applied to the first to fourth main switches TR1 to TR4.
Flow through. At this time, even if the storage current of the main switches TR1 to TR4 flows, the voltage immediately after the turn-off time changes sinusoidally, so that the power loss based on the product of the current and the voltage is small. When the load 2 is a delay load including an inductance, for example, the first main switch T
When R1 is turned off, the current (stored energy) flowing through the load 2 continuously flows through a circuit including the load 2, the second switch circuit 5b, the power supply 1, the diode D6, and the first capacitor C1. When C1 is completely discharged, the second
Becomes a forward bias, and flows through the load 2, the second switch circuit 5b, the power supply 1, and the second diode D2. If the load 2 is a leading load, the first
When the first main switch TR1 is turned off and the second and fourth auxiliary switches S2 and S4 are turned on while the first diode D1 is flowing while the main switch TR1 is on, the load 2 and the first When a current flows through a circuit consisting of the reactor L1, the second auxiliary switch S2, the power supply 1 and the second switch circuit 5b, and the current of the reactor L1 rises until it becomes equal to the load current, the diode D1 is cut off.

[0030]

Third Embodiment Next, an inverter device according to a third embodiment will be described with reference to FIGS. The circuit shown in FIG. 7 includes a capacitor C1, reactors L1a and L1b, third and fourth capacitors.
The connection of the auxiliary switches S3 and S4 is changed, and a charging circuit 7 is added. That is, the first and second reactors L1a and L1b are connected in series between the first and second auxiliary switches S1 and S2. Capacitor C1 is connected between the interconnection point of the two reactors L1a and L1b and the interconnection point of the third and fourth diodes D3 and D4. The third auxiliary switch S3 is connected in parallel with the capacitor C1 and the first reactor L1a, and the fourth auxiliary switch S4 is connected in parallel with the capacitor C1 and the second reactor L1b.
The charging circuit 7 comprises a resistor or a switch and is connected in parallel to the fourth diode D4. In FIG. 7, the rest is the same as in FIG.

[0031]

[Operation] The inverter operation by turning on and off the first and second main switches TR1 and TR2 is the same as the circuit of FIG. In the inverter device of FIG. 7, it is necessary to charge the capacitor C1 in advance as in the case of FIG. For this reason, the first main switch TR1 is turned on, and a charging current flows through a circuit composed of the first main switch TR1, the capacitor C1 and the charging circuit 7. Next, assuming that the capacitor C1 is charged with the polarity shown in FIG. 7, the operation of the circuit shown in FIG. 7 in a section corresponding to the section between t0 and t3 in FIGS. 3 and 4 will be described with reference to FIG.

FIG. 8 shows the state of each part in FIG. 7 when the load circuit 4 is unloaded and the load 2 is a delayed load of only a transformer. The first capacitor C1 is substantially connected to the power supply voltage V
When the first main switch TR1 is turned off and the second auxiliary switch S2 is turned on at time t0, the energy of the first capacitor C1 is reduced by the first capacitor C1 and the second capacitor. The voltage Vc1 of the first capacitor C1 is discharged by a resonance circuit including the reactor L1b, the second auxiliary switch S2, and the fourth diode D4, and the voltage Vc1 of the sine wave is 90 to 180 degrees as shown in FIG. Decreases in waveform. At this time, since the fourth diode D4 is on, the voltage Vc1 of the first capacitor C1 is applied to both ends of the second main switch TR2.
As shown in (H), the second main switch TR is set between t0 and t1.
2 voltage Vtr2 drops toward zero. Also, the first
The voltage Vtr1 of the main switch TR1 is changed from the power supply voltage V to the second
The value obtained by subtracting the voltage Vtr2 of the main switch TR2 is slowly raised as shown in FIG. The resonance current I1 of the closed circuit including the first capacitor C1, the second reactor L1b, the second auxiliary switch S2, and the fourth diode D4 has a sine wave in the interval t0 to t1 as shown in FIG. Flows in the range of 0 to 90 degrees. When the voltage Vc1 of the first capacitor C1 becomes zero at time t1, the reverse bias of the second diode D2 is released, and the current I1 due to the release of the energy stored in the second reactor L1b is reduced to the second reactor L1b and the second reactor L1b. Flows as a circulating current through the closed circuit of the auxiliary switch S2 and the second diode D2. During the period from t1 to t2, the first capacitor C1
Is zero volt, and the voltage Vtr2 of the second main switch TR2 is also zero volt. Therefore, when the second main switch TR2 is turned on at, for example, t1 selected from the period from t1 to t2, ZVS is achieved. At t0, the ZVS of the first main switch TR1 is achieved. Second
The second auxiliary switch S2 is turned off at time t2 after the time point t1 when the main switch TR2 is turned on, and the fourth auxiliary switch S4 is turned off.
At the same time as or immediately before t2, resonance occurs again in the closed circuit of the second reactor L1b, the fourth auxiliary switch S4 and the first capacitor C1, and the first capacitor C1
1 is charged in the opposite manner to FIG. 7, and this voltage Vc1 is
As shown in FIG. As shown in FIG. 8E, the resonance current I1 has a sine wave of 90 during the period from t2 to t3.
It changes in the waveform of the 180-degree section, and becomes zero at time t3. Since the fourth auxiliary switch S4 is a thyristor,
It has the function of turning off naturally when the current becomes zero. In FIG. 8, the ON control time width of the fourth auxiliary switch S4 is set to t3 immediately before t2, but is set to t3 immediately before t2.
Short on-control pulses up to immediately after 2 can also be used. The resonance current I1 shown in FIG. 8 (E) flows through the fourth auxiliary switch S4, but turns off when the current is zero.
CV is achieved. When the second auxiliary switch S2 is turned on, the current is zero, so that ZCS is achieved, and since this voltage Vs2 gradually increases from the turn-off time t2, ZVS is achieved.

As is apparent from the above description, when the first main switch TR1 is turned off and when the second main switch TR2 is turned on, ZVS is achieved to reduce the switching loss, and the second auxiliary switch S2 is connected to the ZCS and ON / OFF by ZVS, and the fourth auxiliary switch S4 is set to ZC
Since it is turned off at S, the switching loss here is also reduced.

When the second main switch TR2 is turned off, the first auxiliary switch S1 is turned on and the first capacitor C1, the third diode D3, the first auxiliary switch S1, and the first reactor L1a are connected. A resonance circuit is formed, and a current I corresponding to a section between t0 and t1 in FIG.
1 flows. A current corresponding to a section between t1 and t2 in FIG. 8 flows through a circuit including the first reactor L1, the first diode D1, and the first auxiliary switch S1. T2 in FIG.
The current corresponding to the section t3 flows in a closed circuit including the first reactor L1a, the capacitor C1, and the third auxiliary switch S3. Further, the same operation as in the first switch circuit 5a occurs in the second switch circuit 5b.

In FIG. 8, the load is described as no load.
Can be regarded as a resistance, a current corresponding to the voltage applied to the load 2 is applied to the first to fourth main switches TR1 to TR4.
Flow through. At this time, even if the storage current of the main switches TR1 to TR4 flows, the voltage immediately after the turn-off time changes sinusoidally, so that the power loss based on the product of the current and the voltage is small. When the load 2 is a delay load including an inductance, for example, the first main switch T
When R1 is turned off, the current (stored energy) flowing through the load 2 continues to the circuit including the load 2, the second switch circuit 5b, the power supply 1, the fourth diode D4, and the first capacitor C1. When the first capacitor C1 is completely discharged, the second diode D2 becomes forward-biased and flows through the load 2, the second switch circuit 5b, the power supply 1, and the second diode D2. When the load 2 is an advanced load, the first main switch TR1 is turned on during the ON period of the first main switch TR1.
When the first main switch TR1 is turned off and the second auxiliary switch S2 is turned on while a current is flowing through the diode D1, the load 2, the second reactor L1b, the second auxiliary switch S2, the power supply 1 When a current flows through the circuit including the second switch circuit 5b and the current of the second reactor L1b rises until it becomes equal to the load current, the diode D1 is cut off.

[0036]

Fourth Embodiment Next, a half-bridge type inverter device shown in FIG. 9 will be described. The inverter circuit of FIG.
Of the inverter device is replaced with first and second power supply capacitors Ca and Cb having the same capacity. That is, the first and second power supply capacitors Ca and C are connected between one end and the other end of the power supply 1.
The series circuit of b is connected, and the other end (right end) of the load 2 is connected to these connection midpoints.

In this half-bridge type inverter circuit, first, the first and second power supply capacitors Ca,
Cb is charged to half the value of the voltage V of the power supply 1. In this state, when the first main switch TR1 is turned on and the second main switch TR2 is turned off, the first power switch 1, the first main switch TR1, the load 2, and the second power supply capacitor Cb are connected to the first main switch TR1. And the second power supply capacitor Cb is charged. Further, the first power supply capacitor Ca, the first main switch TR1 and the load 2
The discharge current in the first direction flows in the circuit consisting of At this time, a voltage of V / 2 is applied to the load 2. Next, the second
During the ON period of the main switch TR2, the power supply 1, the first power supply capacitor Ca, the load 2, and the second main switch T2
A current in the second direction flows in the circuit including R2, and a discharge current in the second direction flows in the circuit including the second power supply capacitor Cb, the load 2, and the second main switch TR2. Also in the half-bridge type inverter of FIG. 9, since the capacitor C1, the reactor L1, and the like are provided as in FIG. 1, the same effect as in FIG. 1 can be obtained.

[0038]

Fifth Embodiment Next, a three-phase bridge type inverter device shown in FIG. 10 will be described. In this embodiment, the first
The second and third switch circuits 5b and 5c having the same configuration as the switch circuit 5a are connected. Each switch circuit 5
Output lines of the respective phases are derived from the connection points of the first and second main switches at a, 5b, and 5c, and are connected to the three-phase load 2. First to third phase switch circuits 5a, 5
As is well known, b and 5c are driven at an angle interval of 120 degrees. Also in this three-phase inverter, the switch circuits 5a, 5b, and 5c of each phase are configured the same as the switch circuit 5a of FIG.

[0039]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The half-bridge inverter device of FIG. 9 or the three-phase bridge inverter device of FIG. 10 can be configured using the switch circuit 5a of FIGS. (2) In FIGS. 4 and 6, the second auxiliary switch S
2 can be set to the same time t1 as the time when the second main switch TR2 is turned on. (3) In FIG. 6, the ON point of the fourth auxiliary switch S4 can be the same as or immediately before the OFF point t2 of the second auxiliary switch S2. (4) In FIGS. 4, 6 and 8, the off point of the second auxiliary switch S2 can be shifted to t1 so that the period from t1 to t2 is made substantially zero. (5) When the charging circuit 7 is a switch such as a transistor in FIGS. 5 and 7, the first main switch TR1 is used.
At the same time, the capacitor is turned on to charge the capacitor C1. Also,
The charging circuit 7 is connected in parallel with the diode Da or D3, and can charge the capacitor C1 so that the left side of the capacitor C1 becomes positive during the ON period of the second main switch TR2. Before starting, an independent charging circuit can be directly connected to both ends of the capacitor C1 for charging, and then the charging circuit can be disconnected. Alternatively, as shown in FIG. 11, a charging circuit 7 may be connected in parallel with the diode Da to charge during the ON period of the second main switch TR2. In FIG. 7, the charging circuit 7 can be connected in parallel with the diode D3. (6) A capacitor for reducing voltage rise at turn-off or for absorbing noise can be connected in parallel with the main switches TR1 and TR2. (7) Main switches TR1 to TR4, auxiliary switch S1
S8 can be semiconductor switches such as FETs. (8) In each embodiment, as shown in FIG. 12, the leading edge of the first and third auxiliary control pulses for controlling the first and third auxiliary switches S1 and S3 is set after the second main control pulse. The leading edge of the second and fourth auxiliary control pulses for controlling the second and fourth auxiliary switches S2 and S4 is set to a point in time before the edge and before the trailing edge of the first main control pulse. Can be time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an inverter device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a control circuit of FIG. 1 in principle.

FIG. 3 is a voltage waveform diagram showing a state of each unit in FIG. 2;

FIG. 4 is a diagram showing a state of each unit in FIG. 1;

FIG. 5 is a circuit diagram showing an inverter device according to a second embodiment.

6 is a diagram showing a state of each unit in FIG. 5;

FIG. 7 is a circuit diagram showing an inverter device according to a third embodiment.

FIG. 8 is a circuit diagram showing a state of each unit in FIG. 7;

FIG. 9 is a diagram illustrating an inverter device according to a fourth embodiment.

FIG. 10 is a diagram showing an inverter device according to a fifth embodiment.

FIG. 11 is a circuit diagram showing an inverter device according to a modification.

FIG. 12 is a waveform diagram showing a control pulse according to a modification.

[Explanation of symbols]

 TR1 to TR4 Main switch S1 to S4 Auxiliary switch C1, C2 Capacitor L1, L2 Reactor

Claims (8)

(57) [Claims] 1. One or more switch circuits are connected between one end and the other end of a DC power supply, and the switch circuits supply a load with a current in a first direction and a current in a second direction opposite thereto. In a bridge-type, half-bridge-type, or multi-phase bridge-type inverter device configured to flow a current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). It comprises a series circuit of first and second main switches (TR1, TR2), and the first and second main switches (TR1, T2)
R2), a main conversion circuit having an interconnection midpoint connected to a load, and first and second auxiliary switches (S1, S2) connected between one end and the other end of the DC power supply (1). And a first and second diode (D1, D2) connected in anti-parallel to the first and second switches (TR1, TR2).
And third and fourth diodes (D3, D4) connected in anti-parallel to the first and second auxiliary switches (S1, S2).
And an interconnection midpoint between the first and second main switches (TR1, TR2) and the first and second auxiliary switches (S1,
A resonance capacitor (C1) connected between the interconnection middle point of S2) and an antiparallel of third and fourth auxiliary switches (S3, S4) in parallel with the resonance capacitor (C1). A resonance reactor (L1) connected via a circuit, and the first and second main switches (TR1, TR2).
And first and second main control pulses for controlling
Second, third and fourth auxiliary switches (S1, S2, S3
, S4), a control circuit for generating first, second, third, and fourth auxiliary control pulses is provided. 2. The control circuit according to claim 1, wherein the first and second main control pulses are alternately generated at a predetermined time interval (Ta) between the first and second main control pulses. C1) and the reactor (L1) are set to have a time width corresponding to 0 to 90 degrees or more of the sinusoidal resonance current waveform based on the reactor (L1), and at the same time as or before the trailing edge of the first control pulse. At the time, the second and fourth moving switches (S2, S4) are controlled to be turned on, and at the same time as or after the leading edge of the second main control pulse, the second auxiliary switch (S2, S4) is turned on. S2) is turned off, and the fourth auxiliary switch (S2) is turned off, and the time corresponding to the 90 to 180 degree section of the sinusoidal resonance current waveform elapses from the time when the second auxiliary switch (S2) is turned off. Of the auxiliary switch (S4) of natural or forced The first and third auxiliary switches (S1, S3) are turned on at the same time as or before the trailing edge of the second main control pulse; The first auxiliary switch (S1) is turned off at the same time as or after the leading edge of the main control pulse, and from the time when the first auxiliary switch (S1) is turned off. The third auxiliary switch (S3) is configured to be naturally or forcibly turned off when a time corresponding to a 90 to 180 degree section of the sinusoidal resonance current waveform has elapsed. The inverter device according to claim 1, wherein 3. One or more switch circuits are connected between one end and the other end of the DC power supply, and the switch circuits apply a current in a first direction and a current in a second direction opposite to the load to a load. In a bridge-type, half-bridge-type, or multi-phase bridge-type inverter device configured to flow a current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). The first and second main switches (TR1, TR2) are composed of a series circuit, and the first and second main switches (TR1, TR2) are connected in series.
2) a main conversion circuit whose middle point is connected to a load, and first and second auxiliary switches (S1, S2) connected between one end and the other end of the DC power supply (1). And a first and second diode (D1, D2) connected in anti-parallel to the first and second switches (TR1, TR2).
And third and fourth diodes (D3, D4) connected in anti-parallel to the first and second auxiliary switches (S1, S2).
And fifth and sixth diodes (D3, D4) connected in the same direction as the third and fourth diodes (D3, D4) between one end and the other end of the DC power supply (1). Da, Db)
And a middle point of the interconnection between the first and second main switches (TR1, TR2) and the fifth and sixth diodes (Da, D).
b) a resonance capacitor (C1) connected between the interconnection middle points of the first and second main switches (TR1, TR2); and a first and second auxiliary. Switch (S1,
A reactor (L1) connected between the interconnection midpoint of S2), the interconnection midpoint of the first and second auxiliary switches (S1, S2), and the fifth and sixth diodes (Da). , Db
) And an anti-parallel circuit of third and fourth auxiliary switches (S3, S4) connected between them and the first and second main switches (TR1, TR2).
And first and second main control pulses for controlling
Second, third and fourth auxiliary switches (S1, S2, S3
, S4), a control circuit for generating first, second, third, and fourth auxiliary control pulses is provided. 4. The control circuit alternately generates the first and second main control pulses at a predetermined time interval (Ta) between the first and second main control pulses. C1) and the reactor (L1) are set to have a time width corresponding to 0 to 90 degrees or more of the sinusoidal resonance current waveform based on the reactor (L1), at the same time as or before the trailing edge of the first main control pulse. At the point of time, the second and fourth auxiliary switches (S2, S4) are turned on, and at the same time as or after the leading edge of the second main control pulse, the second auxiliary switch (S2, S4) is turned on. (S2) is turned off, and when the time corresponding to the 90 to 180 degree section of the sinusoidal resonance current waveform has passed since the second auxiliary switch (S2) was turned off, the second auxiliary switch (S2) was turned off. 4 Auxiliary switch (S4) is natural or forced The first and third auxiliary switches (S1, S3) are turned on at the same time as or before the trailing edge of the second main control pulse, and The first auxiliary switch (S1) is controlled to be turned off at the same time as or after the leading edge of one main control pulse, and the first auxiliary switch (S1) is turned off. The third auxiliary switch (S3) is turned off naturally or forcibly when a time corresponding to a 90 to 180 degree section of the sinusoidal resonance current waveform has elapsed from the time point (1). The inverter device according to claim 3, wherein: 5. A capacitor charging circuit connected to the fifth diode (Da) or the sixth diode (Db) in parallel for charging the capacitor (C1). Inverter device according to. 6. One or more switch circuits are connected between one end and the other end of the DC power supply, and the switch circuits apply a current in a first direction and a current in a second direction opposite to the load to a load. In a bridge-type, half-bridge-type, or multi-phase bridge-type inverter device configured to flow a current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). The first and second main switches (TR1, TR2) are composed of a series circuit, and the first and second main switches (TR1, TR2) are connected in series.
2) a main conversion circuit whose middle point is connected to a load, and first and second auxiliary switches (S1, S2) connected between one end and the other end of the DC power supply (1). And a first and second diode (D1, D2) connected in anti-parallel to the first and second switches (TR1, TR2).
And third and fourth diodes (D1 and D2) connected in the same direction as the first and second diodes (D1, D2) between one end and the other end of the DC power supply (1). D3, D4)
And a series circuit of the first and second auxiliary switches (S1, S2) and connected in series with each other between the first and second auxiliary switches (S1, S2). The first and second reactors (L1a, L1b), the interconnection midpoint of the first and second reactors (L1a, L1b), and the third and fourth diodes (D3, D4)
, A resonance capacitor (C1) connected between the first reactor (L1a) and the capacitor (C1).
), A third auxiliary switch (S3) connected in parallel to the second reactor (L3) and the capacitor (L3) having a direction opposite to that of the third auxiliary switch (S3). C
1) and a fourth auxiliary switch (S4) connected in parallel with the first and second main switches (TR1, TR2).
And first and second main control pulses for controlling
Second, third and fourth auxiliary switches (S1, S2, S3
, S4), a control circuit for generating first, second, third, and fourth auxiliary control pulses is provided. 7. The control circuit alternately generates the first and second main control pulses at a predetermined time interval (Ta) between the first and second main control pulses, and the predetermined time interval (Ta) corresponds to the capacitor ( C1) and the second reactor (L1b) are set to have a time width corresponding to 0 to 90 degrees or more of the sinusoidal resonance current waveform based on the second reactor (L1b), and at the same time as or after the trailing edge of the first control pulse. Also, the second auxiliary switch (S2) is controlled to be turned on at a time before, and the second auxiliary switch (S2) is controlled at the same time as or after the leading edge of the second main control pulse. Is turned off, and the fourth auxiliary switch (S4) is switched between the leading edge of the second main control pulse and the point at which the second auxiliary switch (S2) is turned off.
) Is turned on, and at the time when the time corresponding to the 90-180 degree section of the sinusoidal resonance current waveform of the capacitor (C1) and the second reactor (L1b) has elapsed from the time of the conversion, The fourth auxiliary switch (S4) is naturally or forcibly switched to the off state, and the first switch is simultaneously or earlier than the trailing edge of the second main control pulse.
Control of the auxiliary switch (S1) of the
At the same time as or after the leading edge of the main control pulse, the first auxiliary switch (S1) is turned off,
The third auxiliary switch (S3) is turned on between the leading edge of the first main control pulse and the off-state of the first auxiliary switch (S1). A capacitor (C1) and the first reactor (L1
a) the third auxiliary switch (S3) is turned off naturally or forcibly when a time corresponding to a section corresponding to 90 to 180 degrees of the sinusoidal resonance current waveform elapses. The inverter device according to claim 6, wherein: 8. A capacitor charging circuit (7) connected in parallel to the third diode (D3) or the fourth diode (D4) for charging the capacitor (C1). An inverter according to claim 6 or 7.