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JPH06177365A - Schottky barrier diode - Google Patents

Schottky barrier diode

Info

Publication number
JPH06177365A
JPH06177365A JP34558392A JP34558392A JPH06177365A JP H06177365 A JPH06177365 A JP H06177365A JP 34558392 A JP34558392 A JP 34558392A JP 34558392 A JP34558392 A JP 34558392A JP H06177365 A JPH06177365 A JP H06177365A
Authority
JP
Japan
Prior art keywords
schottky
layer
junction
junctions
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34558392A
Other languages
Japanese (ja)
Inventor
Takashi Suga
孝 菅
Shinji Kuri
伸治 九里
Masaru Wakatabe
勝 若田部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP34558392A priority Critical patent/JPH06177365A/en
Publication of JPH06177365A publication Critical patent/JPH06177365A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To dissolve troubles with regard to a P-N junction diode and a Schottky-junction diode and to provide a high breakdown voltage, high speed switching and low noise Schottky barrier diode. CONSTITUTION:A Schottky barrier diode is constituted into such a structure that P-N junctions J and Schottky junctions are alternately arranged on one surface of an N-type semiconductor substrate 1 and the P-N junctions, which are adjoined each other at the time of zero bias directly under the Schottky junctions, are overlapped with each other by a depletion layer and at the same time, the impurity concentration of an N-type semiconductor layer (a second epitaxial layer) 7 forming the Schottky junctions is made lower than that of an N-type internal semiconductor layer (a first epitaxial layer) 2 and the layer 7 is formed into a high-resistance layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高速スイッチング、低ノ
イズのショットキバリアダイオ−ドの構造に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky barrier diode structure having high speed switching and low noise.

【0002】[0002]

【従来技術】周知のようにショットキバリアダイオ−ド
の特性改善、特にスイッチング速度、順方向及び逆方向
特性の改善について開発が進められ種々のショットキバ
リアダイオ−ドが提案されている。
As is well known, various characteristics of Schottky barrier diodes have been developed and various Schottky barrier diodes have been proposed in order to improve the characteristics of the Schottky barrier diode, in particular, the characteristics of switching speed, forward direction and reverse direction.

【0003】図1は本願出願人が先に提案(特願平4−
58394号)した構造を示し、1はN型半導体基体、
2はエピタキシアル成長法等により基体1上に積層され
るN-型半導体層、3はN-層2に間隙Wを設けてストラ
イブ状に配列したP+領域でこれによりPN接合Jを形
成する。4はN-層2との間にショットキ接合を形成す
るショットキバリア金属(例Mo、Cr、Al等)、5
は前記P+領域3及びショットキバリア金属4に跨って
設けた電極金属(Al等)、6は半導体基体の他面に設け
た電極金属である。なお、電極金属5はショッ(2)ト
キバリア金属と同一でもよい。
FIG. 1 was first proposed by the applicant of the present application (Japanese Patent Application No. 4-
58394) and 1 is an N-type semiconductor substrate,
Reference numeral 2 is an N-type semiconductor layer laminated on the substrate 1 by an epitaxial growth method or the like, and 3 is a P + region in which a gap W is provided in the N-layer 2 and arranged in stripes, whereby a PN junction J is formed. To do. 4 is a Schottky barrier metal (eg Mo, Cr, Al, etc.) that forms a Schottky junction with the N − layer 2, 5
Is an electrode metal (such as Al) provided over the P + region 3 and the Schottky barrier metal 4, and 6 is an electrode metal provided on the other surface of the semiconductor substrate. The electrode metal 5 may be the same as the shovel (2) toki barrier metal.

【0004】上記の構造において、ショットキ接合の巾
Wあるいは面積を非常に小さくしてゆくと、逆方向電流
がPN接合の値に近くなり、且非常に小さい注入キャリ
ヤでPN接合と同じ様な正方向特性が得られ、且逆方向
回復時間がPN接合に比べて非常に短くなる。因みに図
2は図1の説明用の部分的拡大図でエピタキシアル層2
の不純物濃度9×1014Atoms/cm3(ρ=5Ω・cm)
を使用した時、(ゼロバイアス時)の空乏層巾は約0.
8μmである。PN接合部を表面から3μmの深さで、
実質的にP+部3の側面形状を直角に形状を整えたP+領
域3を、約1.5μmの間隔W(ショットキ接合巾)を
設けて、配列すると前述のようにゼロバイアス時にはP
N接合からN-側に約0.8μmの空乏層が伸びて空乏層
が重なりショットキ部と両側のPN接合にはさまれたチ
ャネル領域は実質的に空乏化している。
In the above structure, when the width W or the area of the Schottky junction is made extremely small, the reverse current becomes close to the value of the PN junction, and the injected carrier is very small and the same positive value as that of the PN junction. Directional characteristics are obtained, and the reverse recovery time is much shorter than that of the PN junction. Incidentally, FIG. 2 is a partially enlarged view for explaining the epitaxial layer 2 of FIG.
Impurity concentration of 9 × 10 14 Atoms / cm3 (ρ = 5Ω · cm)
When using, the depletion layer width (at zero bias) is about 0.
It is 8 μm. The PN junction is 3 μm deep from the surface,
When the P + regions 3 in which the side surface of the P + portion 3 is substantially right-angled are provided with an interval W (Schottky junction width) of about 1.5 μm and arranged, as described above, at the time of zero bias, P + region 3 is formed.
A depletion layer of about 0.8 μm extends from the N junction to the N − side, the depletion layers overlap each other, and the channel region sandwiched between the Schottky portion and the PN junctions on both sides is substantially depleted.

【0005】図3はダイオ−ドのVR−JR(逆方向電圧
−逆漏れ電流)特性図、図4はダイオ−ドのVF−JF
(順電圧降下−順電流)特性図、図5はnSec−Vs
uge(時間−サ−ジ電圧)特性図である。
FIG. 3 is a VR-JR (reverse voltage-reverse leakage current) characteristic diagram of the diode, and FIG. 4 is a VF-JF of the diode.
(Forward voltage drop-Forward current) characteristic diagram, FIG. 5 shows nSec-Vs
FIG. 9 is a characteristic diagram of age (time-surge voltage).

【0006】従来例構造の逆方向特性は図3(a)に示す
ように逆漏れ電流JRは〜10-5Amp/cm2程度に押
さえられ、通常のショットキ−バリアダイオ−ドのJR
が〜10-3Amp/cm2となるのに較べると、PN接
合の逆漏れ電流値にかなり近いすぐれた特性となること
が知られている。又順方向特性は図4(a)に示すよう
に順方向電流密度JF=150Amp/cm2の時VFは
0.9voltが得られ、PN接合ダイオ−ドのVF=1.1
〜1.3voltに較べ望ましい値となる。スイッチング特
性は、負荷がL負荷(1μH)の時は図5(a)に示す
ように、いったん逆方向にスイッチした後も、回路中の
C、Lと共振してリンギングを発生する。第1回目の共
振波形のピ−ク値Vsurgeが低い程望ましい。(3)従来
構造例では、Vsurge=180Vを示した。
As shown in FIG. 3 (a), the reverse characteristic of the conventional structure is such that the reverse leakage current JR is suppressed to about -10 -5 Amp / cm 2 and the conventional Schottky barrier diode JR is used.
Is about 10 −3 Amp / cm 2, it is known that the characteristics are very close to the reverse leakage current value of the PN junction. As for the forward characteristic, as shown in FIG. 4 (a), VF of 0.9 volt is obtained when the forward current density JF = 150 Amp / cm2, and VF of the PN junction diode is 1.1.
It is a desirable value compared to ~ 1.3 volt. As for the switching characteristics, when the load is an L load (1 μH), as shown in FIG. 5A, after switching in the reverse direction, ringing occurs in resonance with C and L in the circuit. The lower the peak value Vsurge of the first resonance waveform is, the more desirable. (3) In the conventional structure example, Vsurge = 180V is shown.

【0007】[0007]

【従来技術の問題点】然し乍ら従来技術は優れた特性を
工業的に得ようとすると前記の巾Wが極めて狭い。(W
≦2.0μm)しかも精度の高い制御性が要求され、製
造技術上の問題がある。
However, in the prior art, the width W is extremely narrow in order to obtain excellent characteristics industrially. (W
≦ 2.0 μm) In addition, controllability with high accuracy is required, which is a problem in manufacturing technology.

【0008】[0008]

【発明の目的】本発明の目的は従来のPN接合型及びシ
ョットキ接合型のダイオ−ドの問題点を解消し、高耐
圧、高速且つ低ノイズのダイオ−ドを提供することにあ
る。
SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems of the conventional PN junction type and Schottky junction type diodes, and to provide a diode with high breakdown voltage, high speed and low noise.

【0009】[0009]

【課題を解決するための本発明の手段】本発明はN型半
導体基体の一面にPN接合とショットキ接合を交互に配
置し、且つショットキ接合直下でゼロバイアス時隣接す
るPN接合が空乏層により重なるように構成すると共に
前記ショットキ接合を形成するN型半導体層(第2エピ
層)の不純物濃度を内部N型半導体層(第1エピ層)の
不純物濃度より低くしたことを特徴とする。
According to the present invention, PN junctions and Schottky junctions are alternately arranged on one surface of an N-type semiconductor substrate, and adjacent PN junctions immediately below a Schottky junction overlap with a depletion layer at zero bias. The N-type semiconductor layer (second epi layer) forming the Schottky junction has a lower impurity concentration than the internal N-type semiconductor layer (first epi layer).

【0010】[0010]

【実施例】図6は本発明の一実施例構造図、図7は本発
明の説明用の部分的拡大図で従来例と同一符号は同等部
分を示す。本発明は従来例と対比して明らかなようにN
型半導体基体1上に形成されてN-層2(第1エピタキ
シアル層)の上に更にこれより不純物濃度の低い高抵抗
のN--層7(第2エピタキシアル層)を形成し、該N--層
との間にショットキ接合を形成するようにしたものであ
る。周知のように逆方向に電圧Vを印加した時に出来る
空乏層の厚みWoは
FIG. 6 is a structural view of an embodiment of the present invention, and FIG. 7 is a partially enlarged view for explaining the present invention. The present invention shows that N
And a high resistance N-- layer 7 (second epitaxial layer) having a lower impurity concentration than the N-- layer 2 (first epitaxial layer) formed on the semiconductor substrate 1. A Schottky junction is formed with the N--layer. As is well known, when the voltage V is applied in the opposite direction, the thickness Wo of the depletion layer is

【0011】[0011]

【数1】 [Equation 1]

【0012】(4)上記数1で表される。即ち不純物濃
度N0が低い程空乏層W0は大きくなることを示してい
る。このことは従来構造のものでショットキ接合の巾
W、あるいは面積を小さくしてゆくとPN接合の逆流に
近づく理由は、ショットキ接合直下にPN接合の空乏層
が両側から形成され、2つのPN接合の空乏層の重なる
程度が大きいほどPN接合の逆流に近づくということで
ある。前記した様にショットキ接合直下のN型の不純物
濃度を低くするということは同じ印加電圧に対しては形
成される空乏層の巾が大きくなりその重なる程度も大き
くなることになる。従って図7ショットキ−メタルの巾
Wあるいは面積が同じであれば図2の構造よりも図7の
構造の方がPN接合も逆流に近くなる。また逆流を同じ
にするならば図7の構造のショットキ接合の巾Wあるい
は面積を図2のそれよりも大きくしてもよいということ
になる。このことは加工プロセスを容易にするという点
でメリットが大きい。
(4) It is expressed by the above equation 1. That is, it is shown that the lower the impurity concentration N0, the larger the depletion layer W0. This is because in the conventional structure, when the width W of the Schottky junction or the area thereof is reduced, the flow approaches the reverse flow of the PN junction because the depletion layer of the PN junction is formed directly below the Schottky junction from two sides. That is, the greater the overlapping degree of the depletion layers, the closer to the reverse flow of the PN junction. As described above, lowering the N-type impurity concentration immediately below the Schottky junction means that the width of the depletion layer formed increases and the degree of overlap increases with the same applied voltage. Therefore, if the Schottky metal of FIG. 7 has the same width W or area, the PN junction of the structure of FIG. 7 is closer to the reverse flow than the structure of FIG. Further, if the backflow is the same, the width W or area of the Schottky junction of the structure of FIG. 7 may be made larger than that of FIG. This has a great advantage in facilitating the processing process.

【0013】本発明構造は、N型10Ω・cm(NB=
4.5×1014Atows/cm3)の第2エピタキシアル層
7の約2.5μm厚みを第1エピタキシアル層2、5Ω
・cm(NB=1×1015Atows/cm3)12μm厚の
上に予め堆積した2重エピタキシアルシリコンウェハ−
を用いた。P+領域3の形成はイオン注入法或いはトレ
ンチエッチングに続くP+拡散処理で実質的に図7に示
すような形状を形成した。なお、ショットキ巾Wは2.
5μmとした。その後、ALをP+とはオ−ミック接触、
N--とはショットキ接触するように蒸着して主たるアノ
−ド電根Aを、また、N+面にはオ−ミック金属Bを配
設してダイオ−ドを完成した。
The structure of the present invention has an N type of 10 Ω · cm (NB =
The thickness of about 2.5 μm of the second epitaxial layer 7 of 4.5 × 10 14 Atows / cm 3) is set to the first epitaxial layer 2, 5Ω.
・ Double epitaxial silicon wafer pre-deposited on cm (NB = 1 × 10 15 Atows / cm 3) 12 μm thick
Was used. The P + region 3 was formed by ion implantation or trench etching followed by P + diffusion to form a shape substantially as shown in FIG. The Schottky width W is 2.
It was 5 μm. After that, ohmic contact with AL and P +,
N-- was vapor-deposited so as to be in Schottky contact with the main anodic electron A, and the ohmic metal B was provided on the N + surface to complete the diode.

【0014】本発明の実施例特性は、図3、図4、図5
の(b)に示すように逆方向特性は従来構造よりもPN
接合に似た特性となり改善されるが、順方向特性は本発
明構造では従来構造と較べ若干悪い。しかし、スイッチ
ング時のノイズは本発明構造は従来構造におけるノイズ
値よりも小さくVsurge=160V優れた値が得られ
た。 (5)
The characteristics of the embodiment of the present invention are shown in FIGS.
As shown in (b) of FIG.
The characteristics are similar to those of the junction and are improved, but the forward characteristics are slightly worse in the structure of the present invention than in the conventional structure. However, the noise during switching was smaller in the structure of the present invention than that in the conventional structure, and a value excellent in Vsurge = 160V was obtained. (5)

【0015】[0015]

【発明の効果】本発明によれば高速、低ノイズダイオ−
ドを提供出来る。又、容易な加工プロセスで従来例の構
造と同様のものを作ることが出来る。なお、エピタキシ
アル層7はP+層下端より上でもよく若干下まであって
も特性に大差はない。
According to the present invention, a high speed, low noise diode
Can be provided. Also, a structure similar to that of the conventional example can be manufactured by an easy processing process. It should be noted that there is no great difference in the characteristics of the epitaxial layer 7 even if it is above or slightly below the lower end of the P + layer.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来構造図FIG. 1 Conventional structure diagram

【図2】図1の説明用部分的拡大図FIG. 2 is a partially enlarged view for explaining FIG.

【図3】ダイオ−ドのVR−JR(逆方向電圧−逆漏れ電
流)特性図
[Fig.3] VR-JR (reverse voltage-reverse leakage current) characteristic diagram of diode

【図4】ダイオ−ドのVF−JF(順電圧降下−順電流)
特性図
[Figure 4] Diode VF-JF (forward voltage drop-forward current)
Characteristic diagram

【図5】nSec−Vsuge(時間−サ−ジ電圧)特性図FIG. 5: nSec-Vsuge (time-surge voltage) characteristic diagram

【図6】本発明の一実施例構造図FIG. 6 is a structural diagram of an embodiment of the present invention.

【図7】図6の説明用部分的拡大図FIG. 7 is a partially enlarged view for explaining FIG. 6;

【符号の説明】[Explanation of symbols]

1 N型半導体基体 2 N-型半導体層(第1エピタキシアル層) 3 P+領域 4 ショットキバリア金属 5 電極金属 6 電極金属 7 N--型半導体層(第2エピタキシアル層) (6) W ショットキ巾 1 N-type semiconductor substrate 2 N- type semiconductor layer (first epitaxial layer) 3 P + region 4 Schottky barrier metal 5 Electrode metal 6 Electrode metal 7 N-- type semiconductor layer (second epitaxial layer) (6) W Schottky Width

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 N型半導体基体にN型の第1エピタキシ
アル層及び第2エピタキシアル層を積層し、又、前記第
2エピタキシアル層の一面にPN接合とショットキ接合
を交互に配置し、且つショットキ接合直下でゼロバイア
ス時隣接するPN接合が空乏層により重なるように構成
すると共に、前記ショットキ接合を形成する前記第2エ
ピタキシアル層の不純物濃度を前記第1エピタキシアル
層の不純物濃度より低くしたことを特徴とするショット
キバリアダイオ−ド。
1. An N-type first epitaxial layer and a second epitaxial layer are laminated on an N-type semiconductor substrate, and a PN junction and a Schottky junction are alternately arranged on one surface of the second epitaxial layer, In addition, the PN junction adjacent to the Schottky junction immediately under zero bias is configured to overlap the depletion layer, and the impurity concentration of the second epitaxial layer forming the Schottky junction is lower than the impurity concentration of the first epitaxial layer. A Schottky barrier diode characterized in that
JP34558392A 1992-12-01 1992-12-01 Schottky barrier diode Pending JPH06177365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34558392A JPH06177365A (en) 1992-12-01 1992-12-01 Schottky barrier diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34558392A JPH06177365A (en) 1992-12-01 1992-12-01 Schottky barrier diode

Publications (1)

Publication Number Publication Date
JPH06177365A true JPH06177365A (en) 1994-06-24

Family

ID=18377584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34558392A Pending JPH06177365A (en) 1992-12-01 1992-12-01 Schottky barrier diode

Country Status (1)

Country Link
JP (1) JPH06177365A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175143B1 (en) * 1997-06-02 2001-01-16 Fuji Electric Co., Ltd. Schottky barrier
KR100701140B1 (en) * 2004-02-24 2007-03-29 산요덴키가부시키가이샤 Schottky Diodes and Manufacturing Method Thereof
JP2009535849A (en) * 2006-04-29 2009-10-01 アルファ アンド オメガ セミコンダクター,リミテッド Integrated MOSFET-Increases the Schottky breakdown voltage (BV) without affecting the layout of the Schottky device
KR101463078B1 (en) * 2013-11-08 2014-12-04 주식회사 케이이씨 Schottky barrier diode and fabricating method thereof
CN112310227A (en) * 2019-07-30 2021-02-02 株洲中车时代半导体有限公司 High-potential-barrier SiC JBS device and preparation method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175143B1 (en) * 1997-06-02 2001-01-16 Fuji Electric Co., Ltd. Schottky barrier
US6221688B1 (en) * 1997-06-02 2001-04-24 Fuji Electric Co. Ltd. Diode and method for manufacturing the same
US7112865B2 (en) 1997-06-02 2006-09-26 Fuji Electric Holdings Co., Ltd. Diode and method for manufacturing the same
US7187054B2 (en) 1997-06-02 2007-03-06 Fuji Electric Holdings Co., Ltd. Diode and method for manufacturing the same
US7276771B2 (en) 1997-06-02 2007-10-02 Fuji Electric Co., Ltd. Diode and method for manufacturing the same
KR100701140B1 (en) * 2004-02-24 2007-03-29 산요덴키가부시키가이샤 Schottky Diodes and Manufacturing Method Thereof
JP2009535849A (en) * 2006-04-29 2009-10-01 アルファ アンド オメガ セミコンダクター,リミテッド Integrated MOSFET-Increases the Schottky breakdown voltage (BV) without affecting the layout of the Schottky device
KR101463078B1 (en) * 2013-11-08 2014-12-04 주식회사 케이이씨 Schottky barrier diode and fabricating method thereof
CN112310227A (en) * 2019-07-30 2021-02-02 株洲中车时代半导体有限公司 High-potential-barrier SiC JBS device and preparation method thereof

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