JPH06163764A - Structure for mounting semiconductor chip - Google Patents
Structure for mounting semiconductor chipInfo
- Publication number
- JPH06163764A JPH06163764A JP43A JP33108992A JPH06163764A JP H06163764 A JPH06163764 A JP H06163764A JP 43 A JP43 A JP 43A JP 33108992 A JP33108992 A JP 33108992A JP H06163764 A JPH06163764 A JP H06163764A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- heat sink
- solder
- silicon chip
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000017525 heat dissipation Effects 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 229910000679 solder Inorganic materials 0.000 abstract description 14
- 230000008646 thermal stress Effects 0.000 abstract description 9
- 239000004020 conductor Substances 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 229910001080 W alloy Inorganic materials 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000005482 strain hardening Methods 0.000 description 2
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- 229910020174 Pb-In Inorganic materials 0.000 description 1
- 239000006096 absorbing agent Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体チップの実装構
造、詳しくはシリコンチップの熱膨張による歪、応力を
容易に吸収し得る半導体チップの実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting structure, and more particularly to a semiconductor chip mounting structure capable of easily absorbing strain and stress due to thermal expansion of a silicon chip.
【0002】[0002]
【従来の技術】半導体素子、特にパワートランジスタや
半導体整流素子等では、動作面積当りの消費電力が大き
い。このため、半導体素子のケースやリードからの熱量
の放出だけでは、発生熱量を放出しきれず、半導体素子
の内部温度が上昇して、熱破壊を起こしてしまう。その
ために、半導体素子の発熱を吸収する熱溜めが必要であ
り、従来、絶縁基板とシリコンチップ(半導体素子)と
の間に放熱板を介在させて熱を吸収、放散させていた。2. Description of the Related Art Semiconductor devices, particularly power transistors and semiconductor rectifying devices, consume a large amount of power per operating area. Therefore, the generated heat amount cannot be completely discharged only by discharging the heat amount from the case or the lead of the semiconductor element, and the internal temperature of the semiconductor element rises, causing thermal destruction. Therefore, a heat sink for absorbing the heat generated by the semiconductor element is required, and conventionally, a heat sink is interposed between the insulating substrate and the silicon chip (semiconductor element) to absorb and dissipate the heat.
【0003】この放熱板の材質としては、熱伝導性が良
いことからCuが使われていた。特に、発熱量が多い場
合には、放熱板としては、該シリコンチップの熱膨張係
数に近似している熱膨張係数を有するCu−W合金、あ
るいは、Cu/Mo/Cuクラッド材が使われる。Cu has been used as the material for the heat sink because of its good thermal conductivity. In particular, when a large amount of heat is generated, a Cu-W alloy or a Cu / Mo / Cu clad material having a thermal expansion coefficient close to that of the silicon chip is used as the heat dissipation plate.
【0004】[0004]
【発明が解決しようとする課題】このようにCuは、熱
伝導率は高いものの、その固有の特性として剛性が高い
ため、熱変形が起こりにくく、シリコンチップに発生し
た熱応力を吸収しにくい。例えば、0.2%耐力(4.
9MPa)が大きいので、外力を印加した場合の弾性変
形範囲が広く、加工硬化も大きい。すなわち、熱応力が
塑性変形により吸収される割合が少ない。また、Cu−
W合金またはCu/Mo/Cuクラッド材は、ともに熱
伝導率が極端に小さいだけでなく、コスト的に高価であ
るという難点を有している。さらに、Cu系材料を用い
た放熱板は、基板全体として重量が過大になるという課
題があった。As described above, although Cu has a high thermal conductivity, it has a high rigidity as an inherent property thereof, so that it is hard to undergo thermal deformation and absorb the thermal stress generated in the silicon chip. For example, 0.2% proof stress (4.
9 MPa), the elastic deformation range is wide when an external force is applied, and the work hardening is also large. That is, the rate at which thermal stress is absorbed by plastic deformation is small. Also, Cu-
Both the W alloy and the Cu / Mo / Cu clad material have the drawbacks of not only extremely low thermal conductivity but also high cost. Further, the heat dissipation plate using the Cu-based material has a problem that the weight of the whole substrate becomes excessive.
【0005】本発明の目的は、半導体素子の熱サイク
ル、断続通電等により、シリコンチップと放熱板との間
に介在する接合層界面の熱疲労による割れやその剥離が
起こりにくい半導体チップの実装構造を提供することに
ある。An object of the present invention is to mount a semiconductor chip on which a crack or peeling thereof due to thermal fatigue at the interface of a bonding layer interposed between a silicon chip and a heat sink is less likely to occur due to a thermal cycle or intermittent energization of the semiconductor element. To provide.
【0006】[0006]
【課題を解決するための手段】本発明は、放熱材を純度
99.9%以上のアルミニウムを用いて作製し、この放
熱材の積層方向の厚みを0.2mm以上とする。このよ
うに柔性の高い金属であるアルミニウムを使用すること
により、上記の目的は達成される。According to the present invention, a heat dissipation material is made of aluminum having a purity of 99.9% or more, and the thickness of the heat dissipation material in the stacking direction is 0.2 mm or more. By using aluminum, which is a metal having high flexibility, the above object can be achieved.
【0007】[0007]
【作用】本発明にあっては、半導体チップ実装用の放熱
材に使用される純アルミニウムは、熱膨張率はCuと比
較してほぼ同等である。また、その熱伝導率もCu−W
合金、Cu/Mo/Cuクラッド材と比較して遜色がな
く、Cu単体と比較した場合は、やや劣るものの、それ
以上に変形抵抗が少ないため、熱応力の吸収材として非
常に有効である。例えば、0.2%耐力(2.9MP
a)が小さいため、容易に塑性変形を起こす。すなわ
ち、熱応力に対して抵抗せずに、順応し易いので、熱応
力の吸収が効果的に行われる。また、Cuに比べて加工
硬化が少ないため、外力に対して柔軟に対応することが
できる。すなわち、金属に外力を印加して塑性変形を起
こさせ、一旦外力を取り除き、再度外力を印加した場
合、Cuをはじめ、大部分の金属は、初めの外力よりか
なり大きな外力でないと、再び塑性変形を起こさない
が、アルミニウムはより小さな外力で塑性変形を起こ
す。In the present invention, the coefficient of thermal expansion of pure aluminum used as a heat dissipation material for mounting semiconductor chips is almost equal to that of Cu. Also, its thermal conductivity is Cu-W.
It is comparable to alloys and Cu / Mo / Cu clad materials, and is slightly inferior when compared to Cu alone, but it has less deformation resistance and is very effective as a thermal stress absorber. For example, 0.2% proof stress (2.9MP
Since a) is small, plastic deformation easily occurs. That is, since it is easy to adapt without resisting the thermal stress, the thermal stress is effectively absorbed. Further, since work hardening is less than that of Cu, it is possible to flexibly cope with external force. That is, when an external force is applied to a metal to cause plastic deformation, the external force is removed once, and then the external force is applied again, most of the metal including Cu does not undergo plastic deformation again unless the external force is considerably larger than the initial external force. However, aluminum causes plastic deformation with a smaller external force.
【0008】本発明においては、このアルミニウムの純
度を99.9%以上とする。この範囲未満では、本発明
の実効が発現しない。さらに本発明においては、アルミ
ニウム製放熱材の積層方向の厚さを0.2mm以上とす
る。この値より薄いと熱応力の緩和効果が少なくなるだ
けでなく、熱溜めとして有効に機能しなくなる。そし
て、このアルミニウム製放熱材は、Cu系放熱材と比較
して軽量であり、Cu−W合金、Cu/Mo/Cuクラ
ッド材よりもコストが安い。In the present invention, the purity of this aluminum is set to 99.9% or more. Below this range, the effect of the present invention is not exhibited. Further, in the present invention, the thickness of the aluminum heat sink in the stacking direction is set to 0.2 mm or more. When the thickness is less than this value, not only the effect of relaxing the thermal stress decreases, but also the thermal storage does not function effectively. The aluminum heat dissipation material is lighter in weight than the Cu-based heat dissipation material and has a lower cost than the Cu-W alloy and the Cu / Mo / Cu clad material.
【0009】[0009]
【実施例】以下、本発明の一実施例について図1を参照
して説明する。この図に示すように、セラミックス、樹
脂、アルミニウム絶縁基板等を用いて作製された絶縁基
板11の上面には、例えばアルミニウム製の回路形成用
導体基板12がろう材等により接合されている。この導
体基板12の上面には、アルミニウム放熱板13がはん
だ14により固着されている。このアルミニウム放熱板
13の表面にははんだ14との濡れ性を良くするためめ
っき層15が被着されている。そして、このアルミニウ
ム放熱板13の上面にはシリコンチップ16が例えばは
んだ17により固着されて搭載されている。ここで、放
熱板13は純度99.9%以上のアルミニウムを用いて
いる。図2はアルミニウムの引張性質に及ぼす不純物の
影響を示すグラフである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. As shown in this figure, a circuit-forming conductor substrate 12 made of, for example, aluminum is joined to the upper surface of an insulating substrate 11 made of ceramics, resin, an aluminum insulating substrate, or the like by a brazing material or the like. An aluminum heat dissipation plate 13 is fixed to the upper surface of the conductor substrate 12 with solder 14. A plating layer 15 is deposited on the surface of the aluminum heat dissipation plate 13 to improve wettability with the solder 14. Then, a silicon chip 16 is mounted on the upper surface of the aluminum heat dissipation plate 13 while being fixed thereto by, for example, solder 17. Here, the heat dissipation plate 13 uses aluminum having a purity of 99.9% or more. FIG. 2 is a graph showing the influence of impurities on the tensile properties of aluminum.
【0010】また、放熱板13の厚さは、0.2mm以
上、好ましくは0.2〜2.0mmとする。厚さがこの
範囲を超えると実用的でない。はんだ層14、17との
濡れ性を高めるために放熱板13の表裏面に被着された
めっき層15に用いられるめっき材としては、ニッケル
またはAu/Niを用いる。このめっき層15を挟んで
設層されるはんだ層14、17としては、通常のPb−
Sn系、Su−Sb系、Pb−In系、Au−Si系、
あるいは、Au−Sn系はんだを用いる。殊に、Pb−
Sn系はんだを用いれば、ニッケルめっき層15は、搭
載されるシリコンチップ16が小型の場合、シリコンチ
ップ16のはんだ付けが必要な部分のみに設層すれば、
シリコンチップ16の位置ずれが防止でき好適である。
このような構成に係る実装構造にあっては、シリコンチ
ップ16にパワートランジスタ等を形成した場合でも放
熱板13が発熱を伝達、放散することとなる。そして、
トランジスタ等の繰り返しての使用にあってもはんだ1
4、17の割れ、剥がれ、シリコンチップ16の割れが
生じにくい。これはアルミニウム放熱板13が容易に塑
性変形することにより熱応力を緩和、吸収するからであ
る。The thickness of the heat dissipation plate 13 is 0.2 mm or more, preferably 0.2 to 2.0 mm. If the thickness exceeds this range, it is not practical. Nickel or Au / Ni is used as the plating material used for the plating layer 15 attached to the front and back surfaces of the heat dissipation plate 13 in order to improve the wettability with the solder layers 14 and 17. As the solder layers 14 and 17 which are provided with the plating layer 15 sandwiched between them, ordinary Pb-
Sn system, Su-Sb system, Pb-In system, Au-Si system,
Alternatively, Au—Sn solder is used. In particular, Pb-
If Sn-based solder is used, the nickel plating layer 15 may be formed only on the portion of the silicon chip 16 that needs to be soldered when the silicon chip 16 to be mounted is small.
This is preferable because the displacement of the silicon chip 16 can be prevented.
In the mounting structure having such a configuration, the heat dissipation plate 13 transmits and dissipates heat even when the power transistor or the like is formed on the silicon chip 16. And
Solder 1 even for repeated use of transistors, etc.
The cracks and peeling of Nos. 4 and 17 and the crack of the silicon chip 16 are unlikely to occur. This is because the aluminum heat sink 13 is easily plastically deformed to absorb and absorb thermal stress.
【0011】表1は耐熱サイクル試験の結果を示すもの
である。この表にあって、本発明品としては純度99.
9%のアルミニウムを放熱板として用い、比較品として
はCuを放熱板として用いたものである。試験条件は以
下の通りである。すなわち、1サイクルは、上記絶縁基
板を、−40℃で60分保持した後、室温で10分間保
持し、さらに125℃にて60分間保持し、室温で10
分間保持するものである。Table 1 shows the results of the heat resistance cycle test. In this table, the product of the present invention has a purity of 99.
9% of aluminum was used as a heat sink, and Cu was used as a heat sink as a comparative product. The test conditions are as follows. That is, for one cycle, after holding the insulating substrate at −40 ° C. for 60 minutes, holding it at room temperature for 10 minutes, further holding it at 125 ° C. for 60 minutes, and then holding it at room temperature for 10 minutes.
Hold for a minute.
【0012】[0012]
【表1】 [Table 1]
【0013】図3は上記熱サイクル試験後の比較品のは
んだ部分の割れを100倍に拡大して示す顕微鏡写真で
ある。FIG. 3 is a micrograph showing a crack of the solder portion of the comparative product after the thermal cycle test, magnified 100 times.
【0014】[0014]
【発明の効果】本発明の半導体チップの実装構造にあっ
ては、放熱材の変形抵抗が小さく、塑性変形し易いので
シリコンチップを接合するはんだ層内で発生する熱応力
の緩和効果が高く、シリコンチップに対する熱サイクル
や断続通電に際して、シリコンチップの破壊などを効果
的に抑えることができる。According to the semiconductor chip mounting structure of the present invention, since the heat-dissipating material has a small deformation resistance and is easily plastically deformed, the effect of alleviating the thermal stress generated in the solder layer for joining the silicon chips is high, It is possible to effectively prevent damage to the silicon chip during the thermal cycle or intermittent energization of the silicon chip.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の一実施例に係る半導体チップの実装構
造を示す断面図である。FIG. 1 is a sectional view showing a semiconductor chip mounting structure according to an embodiment of the present invention.
【図2】本発明に係る高純度アルミニウムの降伏応力と
耐力とを示すグラフである。FIG. 2 is a graph showing yield stress and proof stress of high-purity aluminum according to the present invention.
【図3】本発明を説明するための比較品の顕微鏡写真で
ある。FIG. 3 is a micrograph of a comparative product for explaining the present invention.
11 絶縁基板 13 放熱板 16 シリコンチップ 11 Insulating substrate 13 Heat sink 16 Silicon chip
Claims (2)
介して搭載された半導体チップと、これらの絶縁基板と
接合層との間に介装された放熱材と、を備えた半導体チ
ップの実装構造において、 上記放熱材を、純度99.9%以上のアルミニウムによ
り形成したことを特徴とする半導体チップの実装構造。1. A semiconductor chip including an insulating substrate, a semiconductor chip mounted on the insulating substrate via a bonding layer, and a heat dissipation material interposed between the insulating substrate and the bonding layer. 2. The mounting structure for a semiconductor chip, wherein the heat dissipation material is formed of aluminum having a purity of 99.9% or more.
m以上とした請求項1に記載の半導体チップの実装構
造。2. The thickness of the heat dissipation material in the stacking direction is 0.2 m.
The mounting structure for a semiconductor chip according to claim 1, wherein the mounting structure is at least m.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4331089A JP3044952B2 (en) | 1992-11-17 | 1992-11-17 | Semiconductor chip mounting structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4331089A JP3044952B2 (en) | 1992-11-17 | 1992-11-17 | Semiconductor chip mounting structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06163764A true JPH06163764A (en) | 1994-06-10 |
JP3044952B2 JP3044952B2 (en) | 2000-05-22 |
Family
ID=18239736
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4331089A Expired - Fee Related JP3044952B2 (en) | 1992-11-17 | 1992-11-17 | Semiconductor chip mounting structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3044952B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5729052A (en) * | 1996-06-20 | 1998-03-17 | International Business Machines Corporation | Integrated ULSI heatsink |
US7239016B2 (en) | 2003-10-09 | 2007-07-03 | Denso Corporation | Semiconductor device having heat radiation plate and bonding member |
US8198540B2 (en) | 2006-06-06 | 2012-06-12 | Mitsubishi Materials Corporation | Power element mounting substrate, method of manufacturing the same, power element mounting unit, method of manufacturing the same, and power module |
-
1992
- 1992-11-17 JP JP4331089A patent/JP3044952B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5729052A (en) * | 1996-06-20 | 1998-03-17 | International Business Machines Corporation | Integrated ULSI heatsink |
US5773362A (en) * | 1996-06-20 | 1998-06-30 | International Business Machines Corporation | Method of manufacturing an integrated ULSI heatsink |
US7239016B2 (en) | 2003-10-09 | 2007-07-03 | Denso Corporation | Semiconductor device having heat radiation plate and bonding member |
US8198540B2 (en) | 2006-06-06 | 2012-06-12 | Mitsubishi Materials Corporation | Power element mounting substrate, method of manufacturing the same, power element mounting unit, method of manufacturing the same, and power module |
Also Published As
Publication number | Publication date |
---|---|
JP3044952B2 (en) | 2000-05-22 |
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