JPH0616310B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and in particular, like a firing part of a data driven data processing device, one new data packet is generated from two data packets. The present invention relates to a data processing device.

(Prior Art) The applicant of the present invention has previously described, for example, Japanese Patent Application No. 60-19165.
In the issue, we proposed a new configuration of the ignition part.

Referring to FIG. 10, the system 10 includes an asynchronous delay line ring 12 as a data transmission line, and the asynchronous delay line ring 12 is provided with a data packet to be processed through the merging unit 14 and is processed. The output data is output through the branch unit 16. The data packet provided from the merging unit 14 passes through the asynchronous delay line ring 12, is branched by the branching unit 18, and is stored in the function storage unit 20.
Given to. The data read from the function storage unit 20 is given to the asynchronous delay line ring 12 again via the merging unit 22.

The data packet provided from the function storage unit 20 includes, for example, as shown in FIG. 2, a header HD and a plurality of data words DW _{1 to} DWn following the header HD. Header HD
Is identification data or processing code PC and control code C
This processing code PC includes a code indicating a packet structure and a code indicating the processing content. As the code indicating the packet structure, for example, an order code indicating that it is a header or the last data word is given by the 17th and 16th 2 bits. The code indicating the processing content is particularly called an F code, and is used to specify the type of processing such as "+", "-", ... Or data replacement or insertion. The control code CC includes logical information such as physical destination information, node information due to the program structure, and color information.

The above-mentioned data packet transmitted by the asynchronous delay line ring 12 is given to the first loop-shaped data transmission line 28 forming the ignition unit 27 through the branching unit 24 and the merging unit 26, for example. Different data packets are taken into the second loop-shaped data transmission path 34 that constitutes the ignition unit 27 through different branching units 30 and merging units 32. The data packets provided to the first and second loop-shaped data transmission paths 28 and 34 are transmitted through the respective loops in opposite directions, and are provided to the ignition detection section 36 that constitutes the ignition section 24 together with these transmission paths. To be

The ignition detection unit 36, which is the background of the present invention, exists on the first loop-shaped data transmission line 28 by comparing the control codes included in the respective data packets between the two data packets. It is determined whether or not the data packet and the data packet existing on the second loop-shaped data transmission path 34 form a pair, and 1 is determined based on the specific data packet detected as the data packet pair.
Generates two new data packets. The new data packet generated in this way is placed on the first loop-shaped data transmission line 28, for example, and is introduced again onto the asynchronous delay line ring 12 through the branching unit 38 and the merging unit 39.

As described above, the firing detection unit 36 performs firing detection by comparing the left and right operand packets (identification data in the data packets while circulating the data packet) on each of the two data rings. The two data packets that were detected to be
One operand is converted into a new data packet so that it merges with the other operand. The new data packet generated in this way is transmitted, for example, on the first data transmission line 28 and output through the branching unit 38.

(Problems to be Solved by the Invention) In the background art described above, since the branch output section is provided only on one data transmission path 28, there are various problems as described below. That is, the time taken from the generation of a new data packet to the output becomes long on average. this is,
This is particularly noticeable when a large number of ignition detection units 36 are provided in parallel. Also, since a new data packet is transmitted only on one of the data transmission paths, when the output side of the branching section becomes congested, different data packets are mixed in the data only on the transmission path and circulated. Therefore, an imbalance occurs in which it is difficult to input only the operand packet that should be input to this data transmission path. Furthermore, since there is only one branching unit, even if a large number of firing units generate new data packets in parallel at a high processing rate, the output rate of new data packets is limited by the capability of the branching unit. However, it is difficult to further speed up data processing.

Therefore, a main object of the present invention is to provide a data processing device capable of higher speed processing.

(Means for Solving the Problems) Briefly, the present invention relates to first data for transmitting a data packet including identification data including at least destination information and configured using a shift register. A transmission path, a second data transmission path for transmitting a data packet including identification data including at least destination information, and a second data transmission path, which is configured by using a shift register, respectively serving as the first and second data transmission paths. Formed by a plurality of data packet forming means for detecting data packets which are concatenated, each transmitting and are to be paired and form a new data packet from the two data packets At least 2 to extract new data packets
It is a data processing device provided with one data packet extraction means.

(Operation) Data packets are individually transmitted on the first data transmission line and the second data transmission line. Each of the data packet forming means determines, for example, whether or not the identification data of the data packets transmitted on the first and second data transmission paths match or not,
Detect data packet to be paired. Then, the data packet forming means forms a new data packet from the detected two data packets by, for example, recombining the data packets. The new data packet formed by the data packet forming means is extracted from any of at least two data packet extracting means.

(Effect of the Invention) According to the present invention, since two or more means for extracting a new data packet are provided, the output rate of the new data packet is limited by the processing state at the output portion as in the conventional one. As a whole, a high processing rate can be expected.

By extracting a new data packet from each of the two data transmission paths, there is no imbalance that the input of the data packet to one data transmission path is restricted. Can be realized.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

(Embodiment) FIG. 1 is a schematic block diagram for explaining the principle of the present invention. The present invention is suitable as the ignition part 27 of the system 10 shown in FIG. However, the present invention is generally applicable to all data processing devices that need to find the other party's data to be paired and generate one new data from the paired data. I will point out that in advance.

First and second loop-shaped data transmission lines 28 and 3
Reference numeral 4 denotes a shift register, preferably a self-propelled shift register. The self-propelled shift register will be described in detail later, but data can be pushed in and popped out independently and simultaneously, and the pushed-in data is in a state where the register in the next stage is empty. However, in this and later-described embodiments, these first and second data transmission lines 28 and 34 are not synchronized with the asynchronous data. It is configured as a transmission line.

The two data transmission lines 28 and 34 have been described as constituting a loop in the system of FIG. 1, but they do not necessarily have to be looped. However, as will be explained in detail later, it is desirable that at least one of them, and more preferably both of them, be configured as a loop.

Different data packets are input to the first loop-shaped data transmission line 28 and the second loop-shaped data transmission line 34 through the merging units 26 and 32, as in FIG. Then, the data packets having the configurations as shown in FIG. 2 are transmitted to the first and second data transmission paths 28 and 34, respectively, in opposite directions.

These first and second data transmission lines 28 and 34
Coupled to a plurality of firing detectors 36a, 36b, 36c, 36d, 36e and 3 (as shown in FIG. 10).
6f is provided. Each firing unit 36a-36f
Is the first and second data transmission lines 28 as described above.
It finds a pair of data packets that wrap around and 34 to be paired, and creates a new data packet from the two data packets.

More specifically, in the three firing detection units 36a to 36c in the range shown by the section A in FIG. 1, the data packet and the first data transmission path 28, which are rotated from left to right in FIG. The data packets circulating from right to left on the second data transmission path 34 are compared with each other to generate new data packets. Then, the new data packets generated by these firing detection units 36a to 36c are sent to the branching unit 4 provided in the second data transmission path 34.
It circulates toward 0 and is extracted from this branching section 40.
On the other hand, the three ignition detection units 36d to 3 provided in the section B
In 6f, one new data packet is generated from each of the data packets looped around the two data transmission paths 28 and 34. These ignition detection units 36d-3
The new data packet generated in 6f is diverted from left to right on the first data transmission line 28, and reaches the branching unit 38. Then, such a new data packet is extracted from this branch unit 38.

In this way, two correct data packet extraction units are provided for each of the data transmission lines 28 and 34, a total of two, and the firing detection units 36a to 36f are divided into sections A and B at the intermediate points. Then, if the new data packet generated in the section A joins the second data transmission path 34 and the new data packet generated in the section B joins the first data transmission path 28, two data packets are merged. Branch unit 38 or 4 of the transmission line
A new data packet can be generated on the data transmission line closer to 0 by merging one of the operands, thus eliminating all the problems caused by the background art shown in FIG.

FIG. 3 is an example of embodying the system of FIG. In this embodiment, a plurality of basic modules M ₁₁ , M ₁₂ and M ₂₁ , M ₂₂ each constituting the ignition detection unit 36 are connected in cascade.

One basic module M is shown in FIG. This 4th
In the figure, the ignition detection unit 36d provided in the section B (FIG. 1)
Modules M ₂₁ or M ₂₂ configured as ~ 36f are shown. An identification data detection circuit 42 is provided in association with one data transmission line 28, and the other data transmission line 3 is provided.
4, an identification data detection circuit 44 is provided. That is, the identification data detection circuit 42 extracts the identification data from the input data to the _four parallel data buffers B _{1 to} B ₄ forming the data transmission path 28. The identification data detection circuit 44 extracts the identification data from the input data to the parallel data buffers B _{11 to} B ₁₄ forming the data transmission path 34.

The identification data detected by the identification data detection circuit 42 is commonly provided as one input of the _two comparison circuits 46 ₁ and 46 ₂ . The identification data detected by the identification data detection circuit included in the adjacent module and the identification data detected by the identification data detection circuit 54 included in the same module M are respectively input to the other inputs of the corresponding comparison circuits 46 ₁ and 46 ₂ . As given individually. These two comparison circuits 46 ₁ and 46 ₂ are compared whether identification data both given match, the match signal is provided to each stop circuit 48.

The stop circuit 48 is for synchronizing the data packets to be paired transmitted on the two data transmission lines 28 and 34. Then, a control signal is given from the stop circuit 48 to the merging circuit 50, and the merging circuit 50 cooperates with the packet reassembling circuit 52 to merge a new data packet on the data transmission path 28.

The ignition detection unit 36 provided in the section A shown in FIG.
a module M ₁₁ or M ₁₂ configured as a-36c
Also, it is basically the same as the basic module M shown in FIG. However, both of these modules M ₁₁ and M ₁₂ send the generated data packet to the second
Are merged on the data transmission path 34 of The conversion board 36a is inserted between the section A and the section B in the depth. In the conversion board 36a, given the identification data detected by the module M ₁₂ to one of the comparison circuits of the module M _22, also adjusts the direction of such signals TR and AK for C elements of each module. The identification data may be given to the modules M ₂₂ to M ₁₂ . However, it is not good to send the identification data from both to both at the same time. Because, when the same identification data is input to the two modules M ₁₂ and M ₂₂ , both the input M ₁₂ and M ₂₂ are in a state of waiting for the arrival of a data packet to be paired with the other party, and in that state. The data transmission path 28 or 34 is stopped. Therefore, in this embodiment, in the conversion board 36a, the same identification data is given only to the modules belonging to the section A to the modules belonging to the section B.

Here, prior to the detailed description of this embodiment, the data transmission path included in the module M, the C element used for the data transmission path, the identification data detection circuit, the stop circuit, the merging circuit, the packet reassembling circuit, and the like will be described. .

As shown in FIG. 4, the first and second data transmission lines 2
Both 8 and 34 are configured as self-propelled shift registers. The self-propelled shift register that constitutes the first data transmission line 28 includes cascaded parallel data buffers B _{1 to} B ₅ and respective parallel data buffers B _1.
~ C element corresponding to B ₅ (Coincident Element) C ₁ ~
Including C ₅ . Similarly, the self-propelled shift register that constitutes the second data transmission path 34 includes cascaded parallel data buffers B _{11 to} B ₁₅ and their corresponding C elements C _{11 to} C ₁₅ . .

Here, with reference to FIG. 5 and FIG. 6, the C element constituting the asynchronous self-propelled shift register will be described. C
The element C includes six terminals T _{1 to} T ₆ , a signal TRI (Transfer In) from the C element in the subsequent stage is given to the terminal T _1, and a signal AKO is supplied from the terminal ₂ to the C element in the subsequent stage.
(Acknowledge Out) is output. From the terminal ₃ signal TRO (Transfer Out) is output to the preceding C-element, the signal from the preceding C-element from the terminal ₄ AKI (Ackn
owledge In) is given. Signal TRO is further provided as a transfer command signal to its corresponding parallel data buffer. Then, the signal AKI is given as an empty signal of the preceding parallel data buffer.

The terminal T ₅ is supplied with the reset signal RESET, and the terminal ₆ is supplied with the stop signal STOP.

In the circuit of FIG. ₅ , the reset signal RE is applied from the terminal T _5.
When SET is given, it is inverted by the inverter, and four NAND gates G ₁ and G to which this signal is given are given.
The outputs of ₄ , G ₁₁ and G _{14 all} become high level. The outputs of the NAND gates G ₁ , G ₄ , G ₁₁ and G ₁₄ are at the high level, and therefore the outputs of the NAND gates G ₃ and G ₁₃ receiving it are at the low level. The high level output of the NAND gate G ₄ becomes the signal AKO, and the terminal T ₂
Is given as a signal AKI to the C element in the subsequent stage. This is a signal representing the empty state of the preceding parallel data buffer. At this time, if the data has not arrived yet, the signal TRI to the terminal ₁ is at the low level. When the reset signal RESET to the terminal T ₅ is released, the output of the inverter becomes high level, while the NAND gate G
The signal AK 'from ₁₄ is also at high level, and this state is the initial state.

In the initial state, therefore, the two inputs of each of the NAND gates G ₁ and G ₁₁ are high level,
One input of the OR gates G ₂ and G ₁₂ is at high level. Therefore, the two inputs of the NAND gates G ₃ and G ₁₃ are both at the high level, and therefore the outputs of the NAND gates G ₃ and G ₁₃ are both at the low level. That is, the signal TRO from the signal TR 'and the terminal _{T 3} is at a low level. The inputs of the NAND gates G ₄ and G ₁₄ are low level, high level and high level, respectively, and the outputs of the NAND gates G ₄ and G ₁₄ are high level, respectively.

When the data is transferred and the signal TRI from the C element in the subsequent stage to the terminal T ₁ changes to high level as shown in FIG. 6, all three inputs of the NAND gate G ₁ become high level and their outputs. Becomes low level. Then, in a high level as shown in output or signal TR 'is Figure 6 of the NAND gate G _3, the NAND gate G
The output of ₄ becomes low level. 'When a high level, the output of the NAND gate G ₁₁ goes low, the output TRO is high level of the NAND gate G _13, the output AK of the NAND gate G _14' signal TR becomes a low level. The outputs of the NAND gates G ₄ and G ₁₄ are respectively the NAND gate G.
Back to the input of the ₃ and G _13, the output of NAND gate G _3, and G ₁₃ is locked in the high level state. In this way, as shown in FIG. 6, the signal AKO from the terminal T ₂ becomes low level, and the data has been transferred to the corresponding parallel data buffer of this C element C, that is, the data transfer is no longer in that state. Is notified to the C element in the latter stage. Further, the output of the NAND gate G ₁₃ is at a high level, and a high level signal TRO is given from the terminal T ₃ to the C element at the previous stage. This high level signal TRO is given as a transfer command to the corresponding parallel data buffer, and the data in the parallel data buffer is sent to the preceding stage.

When the signal AKO becomes a low level, the signal TRI, as shown in Figure 6 goes low, therefore, output TR of the NAND gate G ₁ 'is returned to the high level. Further, as described above, the output AK 'of the NAND gate G ₁₄ is changed to the low level, the output AKO of the NAND gate G ₄ returns to the high level, and the output T of the NAND gate G ₃ is output.
R'returns to low level.

When the signal AKO from the C element in the previous stage, that is, the signal AKI given from the terminal T ₄ changes from the high level to the low level, that is, when the empty space of the parallel data buffer in the previous stage is extracted. , The input of the OR gate G ₁₂ becomes low level, and the signal TR ′ is also at low level, the output of the OR gate G ₁₂ also becomes low level. At this time, since the output of the NAND gate G ₁₃ is at high level, the output of the NAND gate G ₁₄ changes to high level. Therefore, the input of the NAND gate G ₁₃ becomes high level, and the output of the NAND gate G ₁₃ changes to low level. In this way, the same state as the initial state is restored.

If the signal AKO from the C element in the previous stage, that is, the signal AKI from the terminal T ₄ remains at the low level, that is, if the parallel data buffer corresponding to the C element in the previous stage is not yet empty, the NAND gate NAND gate Since one input of G ₁₁ remains at low level, even if the signal TRI from the terminal T ₁ is given as high level and the signal TR ′ changes to high level, the NAND gate G ₁₁
Does not work and the signal TRO does not go high,
As a result, the acceptance of data from the subsequent stage is rejected, so that data cannot be transferred to the parallel data buffer corresponding to this C element in that state.

In addition, the stop signal STOP is supplied to the C element C from the terminal T _6.
Is given, the high level signal is
₅ to the NAND gate G ₁₃ . Therefore, the output of the NAND gate G ₁₃ becomes low level,
In this state, the signal TRO from the terminal T ₃ becomes low level, is transmitted to the C element in the previous stage, and the data transfer is stopped.

In this way, as shown in FIG. 4, the parallel data buffers B _{1 to} B ₅ and the C elements C _{1 to} C ₅ and the parallel data buffers B _{11 to} B ₁₅ and the C elements C _{11 to} C ₁₅ respectively receive data. An asynchronous self-propelled shift register for the transmission lines 28 and 34 is configured.

FIG. 7 is a block diagram showing an example of an identification data detection circuit applicable to the embodiment shown in FIG. 3 or FIG. In FIG. 7, only the first identification data detection circuit 42 for extracting the identification data from the first data transmission line 28 is shown and described.

In FIG. 7, the identification data detection circuit 42 includes parallel data buffers B ₂ , B ₃ ,
From B ₄ and _{B 5,} a multiplexer 5 which receives the data
Including 4. That is, when data packets are transferred from the parallel data buffer in the subsequent stage to the parallel data buffer in the previous stage, the multiplexer 54 receives the outputs of the four parallel data buffers B _{2 to} B ₅ .

The header signal line HSL is connected to the 17th bit of each of the parallel data buffers B _{1 to} B ₅ , that is, one bit of the order code. The header signal line HSL ₁ between the parallel data buffers B ₁ and B ₂ is supplied to the multiplexer 54, inverted by an inverter, and supplied to one input of the AND gate G ₁ . Header signal line HSL ₂ connected between parallel data buffers B ₂ and B ₃ is applied to the other input of AND gate G ₁ . The output of the AND gate G ₁ is given to the multiplexer 54, inverted by an inverter and given to one input of the AND gate G ₂ . Header signal line HSL ₃ connected between parallel data buffers B ₃ and B ₄ is applied to the other input of AND gate G ₂ . The output of the AND gate G ₂ is given to the multiplexer 54, inverted by an inverter, and given to one input of the 2-input AND gate G ₃ .
To the other input of the AND gate G ₃ of the header signal line HSL connected between the parallel data buffers B ₄ and B _5.
4 outputs, which are provided to the multiplexer 54.

These header signal line HSL ₁ and AND gate G ₁ to
The output of G ₃ is applied as an enable signal to a corresponding latch circuit (not shown) included in multiplexer 54.

From the multiplexer 54, the identification data extracted from the first data transmission line 28 is given to the comparison circuits 46 ₁ and 46 ₂ (FIG. 4) through the identification data line.

In the initial state, all header signal lines HSL ₁ to
HSL ₄ is at low level. When the header of the data packet is transferred from the parallel data buffer in the subsequent stage to the parallel data buffer B ₅ , the header signal HSL ₄ becomes high level. On the other hand, the header signal line HSL ₃ between the parallel data buffers B ₄ and B ₃ is at the low level, and therefore the output of the AND gate G ₂ is at the low level. Since this low level is inverted and given to the AND gate G ₃ , at this time, a high level is output from this AND gate G ₃ .

When the output of the AND gate G ₃ becomes high level, the corresponding latch circuit included in the multiplexed selector 54 is enabled and the latch to the identification data that the latch circuit from the identification data lines between the parallel data buffer B ₅ and B ₄ To be done.

After that, when the empty space of the parallel data buffer B ₄ is detected by the C element C ₅ , the header of the data packet is transferred from the parallel data buffer B ₅ to this parallel data buffer B ₄ . Accordingly, the header signal line HSL ₃ becomes high level, and the output of the AND gate G ₂ becomes high level in the same manner as the AND gate G ₃ . The high level output of the AND gate G ₂ is inverted and the AND gate G ₃
Therefore, the output of the AND gate G ₃ changes to the low level. On the other hand, the AND gate G ₂ functions as an enable signal for the corresponding latch circuit stepped on by the multiplexer 54, and the identification data included in the header transferred from the parallel data buffer B ₄ to the parallel data buffer B ₃ is fetched at that timing.

By repeating this, the parallel data buffer B ₂
When the header of the data packet from the parallel data buffer B ₃ is transferred to, the header signal HSL ₁ goes high. Therefore, the output of the AND gate G ₁ becomes low level, like the AND gates G ₂ and G ₃ . When the header signal HSL ₁ goes high, the corresponding latch circuit included in the multiplexer 54 is enabled and the identification data included in the data packet from the parallel data buffer B _{2 of the} latch circuit is written. That is, the same identification data is sequentially written in the four latch circuits (not shown) of the multiplexer 54 while the data packet is transferred in the four registers. Therefore, in that period, the same identification data is continuously output from the multiplexer 54. In this way, the multiplexer 54 can be used to hold the identification data for a certain period of time. Thus, in this embodiment, when one of the header signal line HSL ₁ ~HSL ₄ is in the high level, the identification data that exists in which the most preceding stage is selected.

Parallel data from the buffer B ₂ of data packet header is transferred to the parallel data buffer B ₁ at the first stage, the data word other than subsequent headers in parallel data buffer B ₂ is transferred, the header signal line HSL ₁ is low again Therefore, if any of the header signals HSL _{1 to} HSL ₄ is at a high level due to the header of the subsequent data packet, the circuit configuration described above causes the header signal lines HSL _{1 to} HSL ₄ to change. Among them, the identification data existing in the first stage is selected.

In the example of FIG. 7, the number of stages of the parallel data buffer that the multiplexer 54 receives the data can be set arbitrarily according to the required time.

The stop circuit 48 includes a header signal line H between the parallel data buffers B ₃ and B ₄ forming the first data transmission line 28.
Header signal from SL ₁ and second data transmission line 3
The header signal from the header signal line HSL ₂ between the parallel data buffers B ₁₃ and B ₁₄ forming the buffer No. 4 is supplied. In addition, signals TRO ₁ and TRO ₂ from C elements C ₃ and C ₁₃ corresponding to parallel data buffers B ₃ and B ₁₃ , respectively are provided.

From the stop circuit 48, stop signals STOP ₁ and STOP ₂ are applied to the C elements C ₄ and C ₂₄ in the preceding stage, respectively, and a merging control signal is supplied to the merging circuit 50.

The stop circuit 48, as shown in FIG.
Hints, the two inputs are coincident signal 1 and the coincidence signal 2 from the comparison circuits 46 ₁ and 46 ₂ provided in the OR gate 86, whose output is supplied to one input of the AND gate 58. The other input of the AND gate 58 is supplied with the header signal from the header signal line HSL ₁ . The match signal 1 and the header signal from the header signal line HSL _{2 are applied} to the _two inputs of the AND gate 60.
The outputs of these AND gates 58 and 60 are provided as D inputs of D flip-flops 66 and 68 through OR gates 62 and 64, respectively. The clock input of the D flip-flop 66 is supplied with the signal TRO ₁ from the C element C ₃ associated with the first data transmission line 28, and similarly, the clock input of the D flip-flop 68 is supplied with the second signal. The signal TRO ₂ from the C element C ₂₃ of the data transmission line 34 of is supplied. D flip-flop 6
The respective outputs Q of 6 and 68 are provided as their own D inputs through OR gates 62 and 64.

The output Q of the D flip-flop 66 is given as it is to one input of each of the AND gates 70 and 72, and also inverted by an inverter and given to one input of the AND gate 74. Further, the output Q of the D flip-flop 68 is directly applied to the AND gates 70 and 7.
4 and the other input of AND gate 72 after being inverted by an inverter. The output of the AND gate 72 is given to the C element C ₄ of the first data transmission line 28 as the stop signal STOP ₁ , and the output of the AND gate 74 is given as the stop signal STOP ₂ of the C element C of the second data transmission line 34. Given to ₁₄ . Further, the output of the AND gate 70 is given to the merging circuit 82 as a merging control signal.

A stop release signal is applied to the reset inputs of the D flip-flops 66 and 68.

In operation, when the header of the data packet is transferred to the parallel data buffer B ₃ of the first data transmission line 28,
Header signal line HSL ₁ becomes high level, a match signal at this time a high level from the comparator circuit 46 ₁ or 46 ₂ is obtained, a two-input AND gate 58 of the stop circuit 48 are both at a high level, D flip-flop 66 D input of becomes high level. At this time, the signal TRO ₁ from the C element C ₃ becomes high level, the D flip-flop 66 is set, and its output Q becomes high level.
When the header is transferred to the parallel data buffer B ₁₃ included in the second data transmission line 34, the header signal line HS
L ₂ becomes high level, a match signal from the comparison circuit 46 ₂ at this time is obtained, the signal TRO from C-element C _{23 2}
The D flip-flop 68 is set accordingly. That is, the D flip-flops 66 and 68 are connected to the parallel data buffer B ₃ and the second data buffer B _{3 of} the first data transmission line 28.
The parallel data buffer B ₂₃ of the data transmission line 34, the header of the data packets to be paired are set from either faster as it arrives. Then, the D flip-flop that has not been set is set whenever the header arrives. That is, the D flip-flops 66 and 68 hold the coincidence signals from the comparison circuits 46 ₁ and 46 ₂ .

If one D flip-flop 66 is set and the other D flip-flop 68 is not yet set, that is, the corresponding header has not arrived at the parallel data buffer B ₁₃ of the second data transmission path 34. , The two inputs of the AND gate 102 of the stop circuit 48 are both at the high level, and therefore the terminal T of the C element C ₄ is
The stop signal STOP ₁ to ₆ (FIG. 5) becomes high level. Then, the C element C ₂ is stopped.

Conversely, when the D flip-flop 68 is set and the D flip-flop 66 is not set, that is, when the corresponding header has not arrived at the first data transmission line 28, the stop signal STOP ₂ is output from the AND gate 104. Therefore, the data transmission on the second data transmission path 34 is stopped.

In this way, the stop circuit 48 establishes the synchronization of the data packets circulating on the two data transmission paths.

The merging circuit 50 receives the merging control signal from the stop circuit 48. As shown in FIG. 9, the merge control signal is inverted and applied to one input of AND gates 76, 78 and 86, and is applied to one input of AND gate 84 as it is. The other input of the AND gate 76 receives the signal TR from the C element C ₁ included in the first data transmission line 28.
O is given. Further, the other input of the AND gate 78 is supplied with the signal TRO from the C element C ₁₂ included in the second data transmission path 34. And AND gate 76
Is applied to one input of the OR gate 82, and the other input of the OR gate 82 is connected to the C element C ₂ and the C element C _2.
The signal TRO from ₁₂ and the output of the AND gate 80 to which the merge control signal is given are given. OR gate 82
Is provided to the C element further upstream of the first data transmission line 28. Similarly, the output of the AND gate 78 is also given to the C element in the previous stage included in the second data transmission path 34. The signal AKO from the C element included in the first data transmission path 28 is applied to the other input of the AND gate 84, and the signal AKO from the C element in the preceding stage of the second data transmission path 34 is applied. The outputs of these two AND gates 84 and 86 are both passed through an OR gate 88 and are included in the second data transmission line 34 as C.
Given to element C ₁₂ .

Two D flip-flops 66 included in the stop circuit 48
When both 68 and 68 are set, that is, when the corresponding headers arrive at the parallel data buffers B ₃ and B ₁₃ , one of the inputs of the AND gates 72 and 74 becomes low level, and the stop signals STOP ₁ and STOP. Both ₂ are low level. Accordingly, the two inputs of the AND gate 100 both become high level, and the high level merge control signal is output to the merge circuit 50.

Therefore, the AND gate 84 included in the merging circuit 50.
One input of the AND gate 86 becomes high level, and conversely, one input of the AND gate 86 becomes low level. Therefore, the OR gate 88 outputs the signal AKO from the C element included in the first data transmission line 28, not from the C element of the second data transmission line 34, and the signal AKO is output from the C element included in the second data transmission line 28.
Is given as the signal AKI of the C element C ₁₄ of the data transmission path 34. At the same time, one of the inputs of the AND gate 78 becomes low level, and the signal TRO from the C element C ₁₄ to the C element at the previous stage becomes low level. Also,
Since the merging control signal is at the high level, the output of the AND gate 80 is validated as the input of the OR gate 82 of the merging circuit 50. Therefore, the first data transmission line 2
8 of the C element C ₄ and the C element C ₁₄ of the second data transmission line 34 are both high level signals TRO ₁ and TRO ₂ from the OR gate 82 to the preceding stage of the first data transmission line 28. High level signal TRO to C element
Is given. Therefore, after that, the data packet of the second data transmission path 34 is given to the packet reassembling circuit 52 provided in the first data transmission path 28, and disappears from the second data transmission path 34.

In the data packet regrouping circuit 52, the repacking of packets is performed and a new data packet is first
Of the stop circuit 48 after it is brought to the data transmission line 28 of
A high-level stop release signal is applied to, and both D flip-flops 66 and 68 are reset. In this way, a match of the data packets to be paired is detected and one new data packet is generated.

Returning to Figure 3, when attention is paid to a certain one basic module M _22, the match can be taken by the comparator circuit 46 2 _(FIG. 4), the two data packets to be paired together in the module M ₂₂ It was when they were transferred. On the other hand, the comparison circuit 46 ₁ can match the data packet on the first data transmission line (upper data transmission line in the figure) of the two data packets to be paired with the module M.
₂ , but the data packet on the second data transmission path (lower data transmission path in the figure) is in the module M ₁₂ next to (on the left side in the figure) the conversion board 54 in between. Is. That is, the data packets existing in the four parallel data buffers forming the upper data transmission path are the parallel data buffers in the eight stages including the adjacent modules of the data packet on the lower data transmission path. If the data packet of the other party is transmitted to the module M ₂₂ , it is kept waiting until it reaches the module M ₂₂ . On the contrary, the data packet existing on the lower data transmission path is kept waiting until the partner's data packet arrives at the module M ₂₂ only when the partner's data packet is transferred into the same module M ₂₂ . It will be.

Then, the new data packets generated by the modules M ₁₁ and M _{12 in the} section A merge on the second data transmission path 34 and are output via the branching unit 40. On the other hand, the new data packet generated by the modules M ₂₁ and M ₂₂ in the section B is sent to the first data transmission line 28 and output through the branch unit 38.

[Brief description of drawings]

FIG. 1 is a schematic block diagram for explaining the principle of the present invention. FIG. 2 is a diagram showing an example of a data packet to which this embodiment can be applied. FIG. 3 is a block diagram showing a preferred embodiment of the present invention. FIG. 4 is a block diagram showing an example of modules used in the embodiment of FIG. FIG. 5 is a circuit diagram showing an example of the C element. FIG. 6 is a timing chart for explaining the circuit of FIG. FIG. 7 is a block diagram showing an example of the identification data detection circuit of the embodiment shown in FIG. FIG. 8 is a circuit diagram showing an example of the stop circuit of the FIG. 4 embodiment. FIG. 9 is a circuit diagram showing an example of the merging circuit of the embodiment of FIG. FIG. 10 is a block diagram showing an example of a data driven type processing system which is the background of the present invention. In the figure, the first data transmission line 28, the second data transmission line 34, 36 is firing detector, the identification data detection circuit 42, _44, 46 1, 46 ₂ comparison circuit, 48 stop circuit, Reference numeral 50 is a merging circuit, and 52 is a reassembling circuit.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Kosuke Terada, 52-3 Yamada Nishi, Suita City, Osaka Prefecture B-803 Senri Ichijo Pond B-803 (72) Katsuhiko Asada 4--11, Higashinadanami, Amagasaki City, Hyogo Prefecture No. 4 (72) Hiroaki Nishikawa 1-1255-1002, Esaka-cho, Suita City, Osaka Prefecture (72) Inventor Soichi Miyata 17-88 folding screen, Miyake-cho, Isojo-gun, Nara (72) Inventor Satoshi Matsumoto 3-30 30 Tenmadai Nishi, Hara-cho, Uda-gun, Nara Prefecture 5 (72) Inventor Hajime Asano 1-5 28 Shonanishicho, Toyonaka City, Osaka Prefecture (72) Inventor Masahisa Shimizu 271 Shimobashi, Kadoma City, Osaka Prefecture (72) Inventor Hiroki Miura 10-49 Asahioka-cho, Hirakata-shi, Osaka Sanyo Denki Co., Ltd. No. 2 Tamiya Dormitory (72) Inventor Kenji Shima 3-16-411 Koshien-cho, Nishinomiya-shi, Hyogo (72) Nobufumi Komori Tree in Kunyo, Itami City, Hyogo Prefecture This 14-7

Claims (7)

[Claims] 1. A first data transmission path for transmitting a data packet including identification data including at least destination information, the first data transmission path including a shift register, and data including identification data including at least destination information. A second data transmission line for transmitting a packet and configured by using a shift register, each being connected to the first and second data transmission lines, transmitting each, and forming a pair A plurality of data packet forming means for detecting a data packet to be formed and forming a new data packet from the two data packets, and at least two for extracting the new data packet formed by the data packet forming means A data processing device, comprising data packet extracting means. 2. A new data packet formed by the data packet forming means is merged into the first or second data transmission path, and the data packet extracting means is provided in the first or second data transmission path. The data processing apparatus according to claim 1, further comprising: a branching unit. 3. The plurality of data packet forming means are arranged in cascade on the first or second data transmission path, and the branching means is arranged on both sides of the plurality of data packet forming means. 2. A data processing apparatus according to claim 2. 4. The third data packet forming means generates a new data packet toward the closest one of the branching means arranged on the both sides.
The data processing device according to the item. 5. The identification data detection means for detecting identification data contained in the data packets transmitted on the first and second data transmission paths, and the identification data detection means. 3. A pair discriminating means for discriminating a data packet which is transmitted on the first and second data transmission paths and is to be paired by comparing the identification data detected by the means. The data processing device according to any one of item 4. 6. The method according to claim 1, wherein at least one of the first and second data transmission paths is formed in a loop shape, and a data packet is circulated around the loop data transmission path. The data processing device according to item 5. 7. Data packets are transmitted in opposite directions on the first and second data transmission paths, respectively.
The data processing device according to any one of claims 1 to 6.