JPH0424737B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a data transmission device that primarily transmits data between systems that operate asynchronously, and particularly to the configuration of a merging section thereof. [Prior Art] Conventionally, a common method for transmitting data between asynchronous systems has been to use a FIFO (first-in, first-out) memory as a buffer between systems. However, this
FIFO memory simply has a data buffer function, so if such FIFO memory is used for data transmission between asynchronous systems, multiple asynchronous systems can only be connected in series, and therefore FIFO The overall system connected to the memory merely constructs a pipeline processing mechanism using a simple cascade connection, and the problem is that the degree of freedom is extremely low. In response, the applicant has developed and filed an application for a data transmission device that can provide a large degree of freedom when constructing an entire system by connecting asynchronous systems (Japanese Patent Application No. 60-33035, Special request 1986
-Refer to No. 33036). This data transmission device will be explained below. FIG. 3 is a diagram showing the system of the data transmission device, in which 5 is a data transmission path, 2a
~2c is the branching part, 3a~3c is the confluence part, 1a~1
c is a processing element, and 4 is an interface. In such a device, packet data flowing from an external system via the interface 4 reaches any one of the processing elements 1a to 1c while circulating between the network elements 3a and 2a to 2c. After the distributed processing is performed by the network elements 1c, the processing results are collected by the network elements 3b and 3c, and sent again to the external system via the interface 4. Here, FIG. 4 shows an example of an asynchronous self-running shift register used in the data transmission line. This asynchronous self-running shift register is a register in which input data is automatically shifted in the output direction without using a shift clock, provided that the next register is empty. It has a buffer function. Each stage of this asynchronous self-running shift register consists of a parallel data latch L and a transfer control circuit C (hereinafter referred to as C) that provides a rising edge trigger for this parallel data latch.
(referred to as elements). Also, the above C
For example, the element has three inputs as shown in Figure 5.
NAND circuit C11 and 2-input NAND circuit C1
2, C13. Note that the INIT signal for initialization is omitted in the figure. Here, the above C element receives two inputs, P0 and P3, and outputs two outputs to P1 and P2,
The internal state of the C element is determined by the states of these four signals, and takes nine states, _S0 to _S8 , as shown in Table 1 below. In the following explanation, the logical values "0" and "1" represent the low level and signal value, respectively.
Equivalent to high level.

[Problem that the invention seeks to solve]

By the way, the present applicant measured the propagation performance when the above-mentioned asynchronous self-propelled shift register was configured in a loop shape. The configuration and measurement results will be explained below. FIG. 9 shows an outline of the loop configuration, which has a circuit configuration in which 16 dynamic C elements as shown in FIG. 10 are connected in stages. Figures 11 a to i each contain 1 word, 2 words,
This figure shows how data passes through a stage of a C element when 4 words, 5 words, 6 words, 9 words, 12 words, 13 words, and 15 words of data are circulated. indicates a state in which data is being transmitted (held) at the stage of the C element, and a "GND" part indicates a state in which no transmission is being performed. Further, a period T in FIG. 2A indicates a cycle. As can be seen from these figures, when 5 words are transmitted within the loop (see d in the same figure), there is a state in which there is equivalently no empty space within the loop,
If more words are added, the circulation period becomes slower (see Table 1 below). Then, as we enter more words, we reach the 9th word (see f in the same figure).
A phenomenon occurs where it is more reasonable to think that holes are propagating, rather than words propagating. From the 12th word onwards, as shown in figure g, there is a period in which the data is held for a fairly long time, and the data throughput becomes extremely poor. Table 1 below summarizes the above experimental results.

[Table] Propagation area

4( 〃 12) 〃 182.5 〃
38 11.4(38) 15

area

Claims (1)

[Scope of Claims] 1. A main data transmission line, a branch data transmission line, and a combined data transmission line configured in a loop form automatically according to control signals from a plurality of data storage means and transfer control circuits in adjacent stages. A data transmission device configured using a shift register consisting of a transfer control circuit in each stage that controls data storage means in each stage, and which transmits an arrival signal when a merged packet arrives at the main line side end of the merged data transmission path. an arrival detection means for outputting an output; a free buffer monitoring means for monitoring the free state on the main line data transmission path; When the empty buffer monitoring means detects that there are at least N/16×3 stages of empty buffers (N is the number of stages of the loop transmission line) ahead of the merging point on the main line, the merging packet is merged onto the main line. A data transmission device characterized in that it is equipped with a merging control means for controlling.