JPH06161778A - Multiflow instruction control method and instruction processing device - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a control method of a multi-flow instruction in an instruction processing apparatus using a hard-wired control method, in the case of performing a complicated processing such as a system control instruction in an instruction processing apparatus of a hard-wired control system. , The simulation (simulation) by the combination of simple instructions is required, and the purpose is to solve the problem that the overhead has occurred. [Structure] Count up every execution of one instruction flow,
Multi-flow counter (M
FC) 11 and decoders (DC2, DC3) that determine the processing contents of the flow to be executed by the count value and the decode signal of the operation code of the instruction are provided.
2, DC3), the processing is executed one by one according to the decoding result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to RISC (Reduc).
ed Instruction Set Comput
The present invention relates to an instruction processing device using an er (reduced instruction set computer) architecture, and more particularly to a method of controlling a multiflow instruction in an instruction processing device using a hardwired control system and an instruction processing device using the method.

[0002]

2. Description of the Related Art In recent years, a hard-wired control type instruction processing apparatus represented by the RISC architecture has been remarkably risen, which attempts to improve performance by deleting complicated instructions and executing all the instructions in a single flow. .

However, on the contrary, for a complicated instruction, for example, a system control instruction in the case of a multiprocessor configuration in which a plurality of processors are connected to one bus (for example, an instruction to access a shared memory), the RISC architecture is used. The adopted instruction processor cannot support it as it is.

Therefore, in order to support such a complicated instruction, it is necessary to simulate those instructions in software by combining them with a simple instruction as if the instruction is supported. Occurs.

On the other hand, the conventional CISC (Complex)
In the instruction processing device of the Instruction Set Computer) architecture, the complicated instructions as described above are realized by microprogram control by a combination of microinstructions, and are configured so that various complicated instructions can be easily accommodated depending on the contents of the microprogram. Has been done.

[0006]

As described above,
In the RISC architecture instruction processing device, when performing complicated processing such as system control instructions, a method of simulating by combining simple instructions is used. However, in this method, overhead may occur due to simulation. Also, CISI
It is difficult to separately provide the microprogram control mechanism used in the architecture, because it increases the hardware and the design complexity.

The present invention has been made in view of the above problems, and in a hard-wired control type instruction processing device, it is possible to effectively execute a multi-flow instruction without using software simulation or microprogram control. It is an object of the present invention to provide a method for controlling a multi-flow instruction that can be processed in an arbitrary manner and an instruction processing device using the method.

[0008]

According to the invention, the above mentioned objects are achieved by means of the patent claims.

That is, according to the first aspect of the present invention, in the instruction processing device of the hardwired control system, when executing a multiflow instruction, the count is incremented every execution of one instruction, and the initial state is obtained by executing the final flow. Flow control means, the control means for determining the processing contents of the instruction by the count value of the flow counting means and the decode signal of the instruction, and the PC control means for updating the program counter only when the final flow is executed. Is a multiflow instruction control method for processing a multiflow instruction by using.

According to the invention of claim 2, claim 1
An instruction processing device using the described multi-flow instruction control method.

[0011]

According to the multiflow instruction control method of the present invention, in order to execute a multiflow instruction such as a CS instruction in an instruction processing device using a hard-wired control method, counting is performed for each execution of one instruction flow. A multi-flow counter (MFC) 11 as a flow counting means that is up-loaded and returned to the initial state when the final flow is executed, and a control that determines the processing content of the instruction based on the count value of the multi-flow counter (MFC) 11 and the operation code of the instruction. Decoders (DC2, DC3) as means are provided, and (1) a decoder (D
C2, DC3) sequentially determine the processing contents of the flow to be executed, generate a processing signal necessary for the processing, and proceed the processing one by one.

(2) When the processing of the final flow is executed, the contents of the multi-flow counter (MFC) 11 are returned to "0" and the program counter (PC) 4
Is updated and the process is completed.

As described above, according to the present invention, it is possible to process a complex instruction such as a CS instruction in a multi-flow without the need for simulation by software or microprogram control.

According to another aspect of the instruction processor of the present invention, the multiflow instruction control method according to the first aspect is used in an instruction processor of a hard-wired control system.

[0015]

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention. This is an embodiment commonly corresponding to the inventions described in claims 1 and 2. FIG. 2 is a diagram showing the execution state of the CS instruction according to the embodiment of the present invention.

In FIG. 1, 1 is an instruction buffer (IB).
Decoder (DC1) that analyzes the operation code of the instruction in
2 is a decoder (DC2) that generates a decoded signal from the signal from DC1 and the signal from MFC 11; 3 is DC1
Decoder (DC3) that generates a decode signal from the signal from MFC11 and the signal from MFC11, 4 is a program counter (PC), 5 is a final flow flag (LF-EX) in the EX stage, and 6 is a final flow flag () in the WB stage. LF-WB) and 7 carry out a logical product operation of the signal (WB-REL) and the signal from the final flow flag (LF-WB) to output the signal (UP-DATE) to the enable terminal (E) of the program counter (PC). Give and circuit,
10 is an instruction buffer (IB) in which instruction data is stored,
11 is a multi-flow counter (MFC), 12 is an AND circuit which performs a logical product operation of a signal (DC-REL) and a signal (LAST-FLOW) and gives a signal to an enable terminal (E) of an instruction buffer (IB). There is. In addition,
Reference symbol E in the circuit block in the figure represents an enable signal terminal, and reference symbol C represents a source input terminal.

An embodiment of the present invention will be described by taking the following instructions used in a multiprocessor configuration as an example.・ Compare and Swap
d Swap) The above instruction (hereinafter, also simply referred to as “CS” instruction) is an instruction to access a certain data area on a shared memory shared by a plurality of processors for inter-processor communication, and to inspect the data area. And the data is updated by bus lock.

In this example, the CS instruction is executed in three flows of data fetch, data comparison, and data store. The bus lock control is omitted because it is not directly related to the present invention.

The instruction processing apparatus of this embodiment is pipeline-controlled, and has the following three stages (see FIG. 2). -DC stage: instruction decode stage-EX stage: operation execution stage-WB stage: operation write stage Furthermore, the program counter (PC) 4 is updated at the end of execution of the instruction. That is, it is assumed that the program counter (PC) 4 is updated when the WB stage is executed without a biline interlock or cancellation of instruction execution.

The operation of the embodiment shown in FIG. 1 will be described below. (1) The decoder (DC1) analyzes the data of the operation code of the executable instruction existing in the instruction buffer (IB) 10 and recognizes that it is a CS instruction. Also at this time,
Since the DC stage of the previous instruction has ended, the flow count value of the multiflow counter (MFC) 11 is "0".
Is.

(2) The decoder (DC2) generates various decode signals for executing the data fetch under the CS instruction and under the condition of the flow count value = 0. (3) The decoder (DC3) does not meet the condition and the signal (L
AST-FLOW) is off. Because the decoder (DC3) is a CS instruction and the flow count value = 2
The final flow is detected under the condition of, and when the flow count value = 0, this condition is not satisfied, and the signal (L
AST-FLOW) is off.

(4) If there is no pipeline interlock condition, the decoding of the flow count value = 0 is released (execution is completed and the process is advanced to the next stage). In this case, the signal (DC-REL) is turned on (control of the release signal of each stage belongs to the technical scope of pipeline control itself and is not directly related to the present invention, and therefore omitted). At this time, the signal (LAST-FLOW)
Is off, the instruction buffer (IB) 10 is not updated. The multiflow counter (MFC) 11 counts up by 1.

(5) The flow count value of the multi-flow counter (MFC) 11 is 1 by the processing of the above (4).
Becomes The decoder (DC2) generates various decode signals for fetch data comparison under the condition of CS instruction and flow count value = 1.

(6) In the decoder (DC3), the condition is not satisfied, and the signal (LAST-FLOW) is off. (7) If there is no pipeline interlock condition, the decoding of the flow count value = 1 is released. At this time, since the signal (LAST-FLOW) is off, the instruction buffer (IB) 10 is not updated. The multiflow counter (MFC) 11 counts up by 1.

(8) The flow count value of the multi-flow counter (MFC) 11 is 2 by the processing of the above item (7).
Becomes The decoder (DC3) generates various decode signals for data store under the condition of CS instruction and flow count value = 2.

(9) The decoder (DC3) detects the final flow with the CS instruction and the flow count value = 2. Since the flow count value = 2, the signal (LAST-FLOW) is turned on.

(10) If there is no pipeline interlock condition, the decoding of the flow count value = 2 is released. At this time, since the signal (LAST-FLOW) is on, the instruction buffer (IB) 10 is updated with the instruction to be executed next. Also, multi-flow counter (MFC)
11 is cleared to "0" because the signal (LAST-FLOW) is on.

(11) When the DC stage of the final flow is released, the final flow flag (LF) of the EX stage is released.
-EX) 5 is set. (12) The EX stage of the final flow is released (EX-
When REL is turned on), the final flow flag (LF-WB) 6 of the WB stage is set.

(13) Final flow flag (LF-WB)
6 is set and the WB stage is released (WB-
When REL is turned on), the program counter (PC) 4
The signal (PC-UPDATE), which is the update permission signal of, is turned on, and the content of the program counter (PC) 4 is updated to the address of the instruction to be executed next.

The execution state of the processing described above is shown in the time chart of FIG. That is, in FIG.
It is shown that the CS instruction is executed in the three processing flows as described above, and the flow 0 is the processing flow of the data fetch and includes DC (0), EX (0), WB.
(0), each stage is started from time t1, flow 1 is a process flow of data comparison, and DC
(1), EX (1), WB (1) stages, starting from time t2, the final flow 2 is the processing flow of the data store, DC (2), EX (2), W
It is shown that each stage is composed of B (2) and starts from time t3.

Further, the progress status of the processing of the flows 0, 1 and 2, the count status of the multi-flow counter (MFC) 11 and the update timing of the program counter (PC) 4 are shown respectively.

Although the embodiment of the present invention has been described above, the method of the present invention is not limited to the case of executing a CS instruction,
It can be widely used for special control of pipeline processing.

For example, when configuring the birdware of the processor used for the instruction processing device, it can be easily used when it is necessary to specially control the pipeline processing due to implementation restrictions such as chip division.

[0034]

As described above, according to the present invention,
In a hard-wired control type instruction processing device, a complicated instruction such as a CS instruction can be realized without changing the pipeline control by adding a small amount of hardware such as a flow counter and some decoders. . Therefore, there is no need to use software simulation or microprogram control.

Further, the method used in the present invention can be effectively used even when special control of the pipeline is required due to hardware restrictions or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an execution state of a CS instruction according to an embodiment of the present invention.

[Explanation of symbols]

 1 Decoder (DC1) 2 Decoder (DC2) 3 Decoder 8DC3) 4 Program Counter (PC) 5 Final Flow Flag (LF-EX) 6 Final Flow Flag (LF-WB) 7 AND Circuit 10 Instruction Buffer (IB) 11 Multiflow Counter (MFC) 12 AND circuit

Claims (2)

[Claims] 1. In a hard-wired control type instruction processing device, when executing a multi-flow instruction, a flow counting means that counts up every execution of one instruction flow and returns to an initial state when the final flow is executed, A multi-flow instruction using a control means for determining and executing the processing content of the instruction by the count value of the flow counting means and a decode signal of the instruction and a PC control means for updating the program counter only when the final flow is executed. A multi-flow instruction control method, characterized by performing the following processing. 2. An instruction processing apparatus using the multiflow instruction control method according to claim 1.