JPH06152622A - Broken loop detection circuit in double loop data communication system - Google Patents

Abstract

PURPOSE:To prevent erroneous detection of a broken line caused by the quantity of a signal propagation delay difference and a minimum packet length by providing 1st and 2nd latches so as to store a reception state till the reception is started in lines in pairs. CONSTITUTION:Upon the receipt of a transmission signal from a line A, a packet recognition circuit 11 clears a latch circuit 12 and sets a latch circuit 22 when the reception is consecutive for a prescribed time or over. Upon the receipt of a transmission signal from a line B, a packet recognition circuit 21 clears the latch circuit 22 and sets the latch circuit 12 when the reception is consecutive for a prescribed time or over. When the circuit 12 or 22 is set, an ON delay timer 13 or 23 starts counting time and sends a signal to a broken line decision circuit 24, and when the circuit 24 does not receive the signal from the timers 13, 23 within a prescribed time, the circuit 24 decides that line discontinuity takes place. Thus, erroneous detection of a broken line caused by the quantity of a signal propagation delay difference and a minimum packet length is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double loop type transmission system in which a plurality of nodes are connected to a transmission line of a double loop via transmission devices, and the same signal is simultaneously transmitted in the opposite direction in the double loop. The present invention relates to a data communication system.

[0002]

2. Description of the Related Art FIG. 2 shows a network (optical double loop) configuration of a token path type communication system of this type. 10 is an optical transmission line (A line) and 20 is an optical transmission line (B line). , N1 to N5 are nodes, MAU1 to MAU
Reference numeral 5 is a transmission device.

In this configuration, a control token serving as a transmission permit is sent from a specific node, for example, the node N1 to the optical transmission line, and the node receiving the control token is allowed to transmit the control packet of its own node.

[0004]

In this double-loop network, when transmission is performed at some station, the corresponding reception is always performed within a fixed time on both lines. Based on the above, the line down (disconnection) of one transmission line is detected.

However, A line 10 and B line 2
Since there is usually a signal propagation delay difference between 0, if this signal propagation delay difference is longer than the minimum packet length, a signal disconnection state may occur before reception is performed on both lines. Yes, there was a risk of false detection.

The present invention has been made to solve this problem, and it is an object of the present invention to provide a disconnection detection circuit in a double loop type data communication system which can detect a disconnection with higher reliability than in the prior art. To aim.

[0007]

In order to achieve the above object, the present invention provides a dual loop data communication system in which a plurality of nodes are connected to a transmission line consisting of an inner loop and an outer loop via respective transmission devices. A first packet recognition circuit connected to the inner loop, a second latch circuit set when the first packet recognition circuit recognizes a packet, and a second latch circuit connected to the second latch circuit. ON
A delay timer, a second packet recognition circuit connected to the outer loop, and a first latch circuit that is set when the second packet recognition circuit recognizes a packet,
The first and second latch circuits include a first ON-delay timer connected to the first latch circuit, and a disconnection determination circuit that inputs both outputs of the first and second ON-delay timers. Are cleared when the packet is received by the first packet recognition circuit and when the packet is received by the first packet recognition circuit.

[0008]

In the present invention, the first and second latch circuits are provided, and the reception state is stored until the reception on the pair of lines is started, which is caused by the difference between the signal propagation delay difference and the minimum packet length. False disconnection detection is prevented.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a disconnection detection circuit. In this figure, 11 is an A-line packet recognition circuit, which takes in a transmission signal A from an A-line 10 and, when receiving this signal, clears a latch circuit (D latch) 12 and this reception is performed for a predetermined time T1 (for example, , 25.6 to 32.0 μs) or more, the latch circuit (D latch) 22 is set.

Reference numeral 21 is a B-line packet recognition circuit, which takes in the transmission signal B from the B-line 20, and when this signal is received, the latch circuit (D latch) 22 is cleared, and this reception takes a predetermined time T1 (for example, 25.6-3
If it continues for more than 2.0 μs, the latch circuit (D latch)
Set 12.

When the latch circuit (D latch) 12 or 22 is set, the ON delay timer 13 or 23
Starts timing and sends a signal to the disconnection determination circuit (exclusive OR circuit) 30, and the exclusive OR circuit 30 outputs both signals for a predetermined time T2 (for example, 44.6 to 51.2 μs). O
When no signal is received from the N delay timers 13 and 23, it is determined that line down has occurred.

The values of the ON delay timers 13 and 23 may be set to be equal to or larger than the maximum signal propagation delay difference. In this embodiment, the ON delay timer value = the maximum value of the signal propagation delay difference−the packet is recognized. Until time.

As described above, in this embodiment, since the reception state of the A line is stored until the reception is started on the B line, even if the signal propagation delay difference is larger than the minimum packet length,
No false positives occur.

In order to avoid a malfunction of the circuit when receiving a signal that is not a packet, it is sufficient to lengthen the time from the start of reception until the packet is recognized.

[0016]

As described above, according to the present invention, the first and second latch circuits are provided, and the reception state is stored until the reception is started on the paired line. False detection of disconnection due to length and size is prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a dual loop data communication system.

[Explanation of symbols]

 10, 20 Optical transmission path 11, 21 Packet recognition circuit 12, 22 Latch circuit 13, 23 ON delay timer 30 Disconnection determination circuit (exclusive OR circuit) N1 to N5 nodes MAU1 to MAU4 transmission device

Claims (1)

[Claims] 1. A double-loop data communication system in which a plurality of nodes are connected to a transmission line composed of an inner loop and an outer loop via transmission devices, respectively, and a first packet recognition circuit connected to the inner loop. When,
A second latch circuit set when the first packet recognition circuit recognizes a packet, a second ON delay timer connected to the second latch circuit, and a second ON delay timer connected to the outer loop. Packet recognition circuit,
A first latch circuit that is set when the second packet recognition circuit recognizes a packet; a first ON delay timer connected to the first latch circuit;
And a disconnection determination circuit for inputting the output of the second ON delay timer together, the first and second latch circuits respectively receiving the packet of the first packet recognition circuit and the first packet recognition circuit. Loop disconnection detection circuit in a double-loop data communication system, which is cleared when the packet is received.