JPH06139068A - Bit offset quantity calculating device - Google Patents

Abstract

PURPOSE:To lighten a burden to be charged upon software at the time of calculating an offset by providing an M-bit adding means. CONSTITUTION:This bit offset quantity calculating device is constituted of an address bus 10 to supply the initial address of 32 bits, an offset bus 11 to supply the initial offset of 32 bits, a 2-bit adder 12 and a 3-bit by-pass 13. Here, since a processing unit is made 32 bits, an access address fundamental unit is 8 bits, and an adding means required for offset quantity calculation is the (M=2)-bit adding means. Then, the least significant M bits of the initial address are M-bit-added to the leading M bits among the least significant N bits of the initial offset, and an offset value is calculated, and the offset or the complement of the offset is outputted in conformity with an offset complement output signal. Then, the initial address and the initial offset shifted down by 3 bits are added, and a base address is calculated by bit-masking in conformity with designated size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit offset amount calculation device.

[0002]

2. Description of the Related Art A conventional selecting means changes the bit taken in by a decoder according to the size information of an operand to be bit-operated, and a difference between the number of bits of an operand and the maximum number of bits of an operand is determined by its offset data. An indirect offset amount control system for performing bit manipulation is disclosed in, for example, Japanese Unexamined Patent Publication No. 1-134621. FIG. 8 is a block diagram of this conventional offset amount indirect designation control system.
Bit input bus, 81 is input section, 82 is selector, and 83
Is a decoder, 84 is an output circuit section, and 85 is an output bus. The offset data based on the bit command is fetched into the input unit 10 of the 5-bit decoder circuit unit 1 via the internal bus, and the lower 5 bits of the fetched data are output as valid data. The lower 3 bits of this data are supplied to the decoder 83, and the upper 2 bits are supplied to the decoder 83 via the selector 82. The decoder 83 converts the bit code into a numerical value. Then, the converted bit at the corresponding position is set to 1 and the other bits are set to 0, and 32-bit data is output to the internal bus 7 via the output circuit unit 5 to reduce the load on the software and process at high speed. To do.

The base address of the operation target bit and its offset amount can be obtained by controlling an adder, shift and mask means such as a barrel shifter, and a temporary register capable of saving data by a microprogram.

For example, in the case of obtaining an offset, if controlled by a microprogram, the initial offset is first inputted to a shift means such as a barrel shifter, arithmetic shift down is performed by 3 bits, and overflowing 3 bits are shifted to a temporary register. It is found by inputting the initial address and the shifted-down offset to the adder, adding them, and masking all the bits other than the lower 2 bits of the result.

Further, when the base address is obtained, if controlled by a microprogram, the initial address and the 3-bit arithmetic down-shifted initial offset are input to a 32-bit adder and added, and then through a bit mask means such as a barrel shifter. , It is necessary to perform a bit mask according to the bit size specification. When performing bit masking with the barrel shifter, for example, when masking the lower 2 bits, first shift down by 2 bits,
The lower 2 bits are replaced with 0 by shifting up by 2 bits. However, such processing requires at least 2 clocks.

[0006]

However, in the above configuration, the base address cannot be obtained,
There is a problem that a 32-bit decoder is required, hardware is increased, and several clocks are required when controlled by a microprogram.

[0007]

An address bus for inputting an initial address, an offset bus for inputting an initial offset, and M-bit adding means for adding M bits are provided, and the least significant M of outputs of the address bus is provided. The bit is connected to one input of the M-bit adding means, and the head M of the least significant N (N> M) bits of the output of the offset bus
An offset amount calculation device in which a bit is connected to another input of the M-bit addition means.

An address bus for inputting an initial address,
An offset bus for inputting a 3-bit arithmetically shifted down initial offset, an addition means for performing addition, and a bit mask means for performing a bit mask by a mask signal are provided, and the output of the address bus is one input of the addition means. A base address calculating device connected to the input of the offset bus, the output of the offset bus being connected to another input of the adding means, and the output of the adding means being connected to the input of the bit mask means.

An address bus for inputting an initial address,
An offset bus for inputting an initial offset, M-bit addition means for adding M bits, and complement output means for complement output of data by a complement output signal are provided, and the least significant M bits of the output of the address bus are The first M bits of the least significant N bits of the output of the offset bus are connected to one input of the M-bit adding means, and the output of the M-bit adding means is connected to the other input of the M-bit adding means. An offset amount complement calculation device connected to the input of the complement output means.

[0010]

According to the present invention, with the above-described structure, the least significant M bits of the initial address are added with the first M bits and M bits of the least significant N bits of the initial offset to obtain the offset value.
The offset or the complement of the offset is output according to the offset complement output signal. The base address is obtained by adding the initial address and the initial offset that has been shifted down by 3 bits and performing bit masking according to the designated size.

[0011]

1 is a block diagram of an offset amount calculating apparatus according to a first embodiment of the present invention. In the figure, 10 is an address bus that supplies a 32-bit initial address, 11 is an offset bus that supplies a 32-bit initial offset, 12 is a 2-bit adder, and 1
3 is a 3-bit bypass.

FIG. 2 is a block diagram of a base address calculation device according to the first embodiment of the present invention. In the figure, 20 is an address bus for supplying a 32-bit initial address, and 21 is a 3-bit downshifted 3
An offset bus that supplies a 2-bit initial offset,
22 is a 32-bit adder, and 23 is a bit mask device.

Using the device shown above, a bit manipulation instruction,
When an arbitrary base address and offset are given as an initial address and an initial offset in a bit field instruction and an arbitrary length bit operation instruction, respectively, the offset (access offset) within the 32-bit word to be actually accessed and the base at that time Calculate the address (access base address). In this embodiment, the processing unit is 32 bits and the access address basic unit is 2.
It is 8 bits in ** N (N = 3). The addition means required for the offset amount calculation is M (log2 (32 /
8)) = 2-bit addition means. The processing unit is 6
In the case of 4 bits, M = 3 bit addition means is required. The operation of each device shown in FIGS. 1 and 2 will be described below.

FIG. 3 is a diagram for explaining the operation of the adding means in the calculation of the access offset, and the operation of FIG. 1 will be described below with reference to FIG. The lowest 2 bits of the initial address 10 and the first 2 bits of the lowest 5 bits of the initial offset 11, that is, the 27th bit and the 28th bit are input to the 2-bit adder 12 to perform a 5-bit offset. 2 leading bits of The lower 3 bits of the 5-bit offset are the same as the least significant 3 bits of the initial offset, and are output from the initial offset bus 11 via the bypass 13. The access offset is obtained by the above.

Actually, as an increase in hardware, the addition of three logical XOR gates and logical NOR gates makes it possible to quickly calculate the access offset and the access base address for microprogram control, which has the effect of accelerating the operation speed. .

FIG. 4 is an operation explanatory diagram of the addition means and the bit mask means in the calculation of the access base address, and the operation of FIG. 2 will be described below with reference to FIG. 32-bit initial address 20 and 3-bit shifted down 3
The 2-bit initial offset 21 is added to the 32-bit adder 22.
Input to and add to obtain the access base address.
By designating the bit size, the bit mask device masks the lower 2 bits of the access base address. For example,
If the bit size designation is halfword (16 bits), the halfword boundary access base address is obtained by masking the lower bits of the base address on the byte boundary. When the bit size designation is word, the word boundary access base address is obtained by masking the lower 2 bits.

Actually, by inputting the word mask signal or the half word mask signal to the bit mask device, the byte boundary access base address which is the output of the adder is passed through the 2-input logical AND gate, respectively, and the lower 2 bits respectively. Alternatively, it can be easily realized by masking the lower 1 bit.

The operation of the above apparatus will be specifically described with reference to FIG. FIG. 7 is an explanatory diagram showing an access method of an operation target bit in a bit operation instruction and a bit field instruction, and referring to it, when an initial offset and an initial address are given, an access base address and an access of the operation target bit The method of obtaining the offset will be described. The initial address is 20h (h: hexadecimal number), and the initial offset is 1BCh. Since this initial offset is a bit offset, it is shifted down by 3 bits to obtain a byte offset.
32 bits are added to h and the initial address 20h to obtain the access base address, 57h. Next, the least significant 2 bits of the initial address, in this case 00b (b: binary number) and the 27th and 28th bits of the initial offset, in this case, 11
2 bits of b are added to obtain the upper 2 bits of the access offset. The least significant 3 bits of the initial offset, in this case 100b, are used as the least significant 3 bits of the access offset, and the access offset is 11100b (1C
h). FIG. 9 shows the access base address and access offset in the case of byte, half word, and word, respectively, by specifying the bit size.

FIG. 5 is a block diagram of a complement output device according to the second embodiment of the present invention. In FIG. 5, 10 is an address bus for supplying a 32-bit initial address, 11 is an offset bus for supplying a 32-bit initial offset, 12 is a 2-bit adder, 13 is a 3-bit bypass, and 14 is a complement output. It is a complement output device. As shown in FIG. 1, the calculation of the offset includes the least significant 2 bits of the initial address 10 and the initial offset 11
The leading 2 bits of the least significant 5 bits, that is, the 27th bit and the 28th bit are input to the 2-bit adder 12, and the leading 2 bits of the 5 bit offset are obtained by performing an operation. The low-order 3 bits of the 5-bit offset are the same as the low-order 3 bits of the initial offset.
It is output as an input to the complement output device 14 via the bypass. The complement of the offset is output through the complement output device according to the complement output signal.

FIG. 6 is an explanatory diagram of a bit mask forming method using the offset complement, and the necessity of calculating the complement of the offset by the complement output device will be described with reference to FIG.
For example, the 20th bit of the 32-bit word is the operation target bit in the bit operation instruction. Then, 20
A mask in which 1 is set at the bit is created and bit operation is performed. The method of making such a mask is to set the most significant bit to 1 and shift down by the offset, or to set the least significant bit to 1 and shift up by the complement of the 5 bit offset, offset (31-offset). It is easier to set the least significant bit to 1 than to set the most significant bit to 1. After the offset value is obtained, the 5-bit offset can be realized faster through the logical NOT gate than in the microprogram control in order to obtain the offset complement.

[0021]

As described above, according to the present invention,
The following effects can be obtained.

By providing the M-bit adding means when obtaining the offset, it is possible to reduce the load on the software and increase the processing speed.

By providing the bit mask means when obtaining the base address, the load on the software can be reduced and the processing speed can be increased.

The bit operation instruction can be processed at high speed by reducing the load on the software by providing the complement output means for outputting the complement of the offset.

By attaching such a small piece of hardware, it is possible to realize a high-speed operation, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an offset amount calculation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a base address calculation device of the same embodiment.

FIG. 3 is an explanatory diagram of the operation of an adding unit in offset calculation.

FIG. 4 is an operation explanatory diagram of an addition unit and a bit mask unit in calculating a base address.

FIG. 5 is a block diagram of an offset complement output device according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a bit mask creation method using offset complement.

FIG. 7 is an explanatory diagram showing an access method of an operation target bit in a bit operation instruction and a bit field instruction.

FIG. 8 is a block diagram of a conventional offset amount indirect designation control system.

FIG. 9 is an explanatory diagram of the difference due to the bit size specification.

[Explanation of symbols]

 10 initial address bus 11 initial offset bus 12 2-bit adding means 13 3-bit bypass 14 complement output means 22 32-bit adding means 23-bit masking means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyohara ▲ Taku ▼ 3 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. An address bus for inputting an address, an offset bus for inputting a bit offset value, and an address from a logarithmic value (M) whose base is the bit length 2 of the basic unit of data processing. The number of bits obtained by subtracting the logarithmic value (N) from the base of the bit length of the smallest possible unit of data is subtracted, and the least significant M bits of the address input from the address bus and the offset bus are input. The least significant M bits of the least significant bit offset, the first (MN) bits are input, and the least significant N bits of the output are the least significant bit offset value input from the offset bus. A bit offset amount calculation device which outputs N bits and outputs the output of the addition means to the higher (MN) bits. 2. An address bus for inputting an address and an offset bus for inputting a bit offset which is a logarithmic value (N) bit arithmetic shift down whose base is 2 of the bit length of the minimum unit data which can be designated by the address. And an addition means for performing addition and a bit mask means for performing a bit mask with a mask signal, the output of the address bus being connected to one input of the addition means,
An access base address calculating device in which an output of the offset bus is connected to another input of the adding means, and an output of the adding means is connected to an input of the bit mask means. 3. An address bus for inputting an address, an offset bus for inputting a bit offset value, and an address from a logarithmic value (M) whose base is 2 of the bit length of a basic unit of data processing. The number of bits obtained by subtracting the logarithmic value (N) from the base of the bit length of the smallest possible unit of data is subtracted, and the least significant M bits of the address input from the address bus and the offset bus are input. The least significant N bits of the least significant bit offset are provided with addition means for inputting the first (M−N) bits and complement output means for performing complement output of data by the complement output signal. Outputs the least significant N bits of the bit offset value input from the offset bus, and outputs the output of the adding means to the higher (M−N) bits. Bit offset complement computing device, characterized in that it is connected to the output of said input of said complement output means.