JPH0613376A - Integrated circuit device of semiconductor - Google Patents
Integrated circuit device of semiconductorInfo
- Publication number
- JPH0613376A JPH0613376A JP17096792A JP17096792A JPH0613376A JP H0613376 A JPH0613376 A JP H0613376A JP 17096792 A JP17096792 A JP 17096792A JP 17096792 A JP17096792 A JP 17096792A JP H0613376 A JPH0613376 A JP H0613376A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- wiring layer
- insulating film
- integrated circuit
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000002184 metal Substances 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008602 contraction Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、金属配線層が多層で構
成される半導体集積回路装置に関し、特に金属配線層の
構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having multiple metal wiring layers, and more particularly to the structure of metal wiring layers.
【0002】[0002]
【従来の技術】一般に半導体集積回路装置は、シリコン
基板上に、ウェル(基板のP・N分離の形成),拡散層
(トランジスタのソース・ドレインの形成),ゲートポ
リ(トランジスタのゲートの形成),コンタクト(各層
間を接続するために絶縁膜に明ける穴),金属配線層
(配線パターン)等が形成されている。さらに相対的に
上下の層間には、絶縁膜を構成して各層が接触しないよ
うにしている。2. Description of the Related Art Generally, a semiconductor integrated circuit device has a well (formation of P / N isolation of a substrate), a diffusion layer (formation of source / drain of a transistor), a gate poly (formation of gate of a transistor), and a silicon substrate. A contact (a hole formed in an insulating film for connecting each layer), a metal wiring layer (wiring pattern), and the like are formed. Further, an insulating film is formed between the upper and lower layers so that the layers do not come into contact with each other.
【0003】また、近年の半導体集積回路装置は、金属
配線層が多層構造になってきており、この金属配線層が
特性的に優れているために、図3に示すように金属配線
層11,12を上下に重なり交差させることができるよ
うになった。さらに半導体集積回路装置は大容量化・多
様化が進んでおり、数十μmから数百μmの金属配線層
が必要になってきている。Further, in recent semiconductor integrated circuit devices, the metal wiring layer has become a multi-layered structure, and since the metal wiring layer is excellent in characteristics, as shown in FIG. 12 can now be overlapped vertically and crossed. Further, semiconductor integrated circuit devices have been increasing in capacity and diversifying, and metal wiring layers of several tens μm to several hundreds μm are required.
【0004】この半導体集積回路装置を構成する各層
は、温度変化により膨張・収縮を引き起こす。特に金属
配線層は、金属配線層以外の各層に比べると、膨張・収
縮の変化の起こる温度が低い。さらに太い金属配線層を
用いている部分では、変化する量が大きくなる。Each layer constituting this semiconductor integrated circuit device causes expansion and contraction due to temperature change. In particular, the metal wiring layer has a lower temperature at which expansion / contraction changes occur, as compared with the layers other than the metal wiring layer. In a portion where a thicker metal wiring layer is used, the amount of change is large.
【0005】一方、半導体集積回路装置を拡散・選別等
している工程で温度変化を少なくすることは、難しくな
っている。On the other hand, it is difficult to reduce the temperature change in the process of diffusing and selecting the semiconductor integrated circuit device.
【0006】[0006]
【発明が解決しようとする課題】前記半導体集積回路装
置では、多層構造の金属配線層が数十μmから数百μm
の太さで構成される場合、金属配線層の温度変化による
変化量が大きいために、この配線層の形状が変形してし
まうという問題があった。In the semiconductor integrated circuit device described above, the metal wiring layer having a multi-layer structure has a thickness of several tens to several hundreds of μm.
When the metal wiring layer is formed to have a large thickness, there is a problem that the shape of the wiring layer is deformed because the amount of change due to temperature change of the metal wiring layer is large.
【0007】また、太い金属配線層が交差している場合
は、金属配線層が変形するだけでなく、上下をこの金属
配線層に挾まれた絶縁膜の温度変化量が小さいために、
上下の金属配線層の変化に伴って絶縁膜に加えられる力
により、絶縁膜に亀裂を生じてしまう。さらに、この亀
裂に金属配線層が入り込んでしまうために上下の金属配
線層が接触(ショート)してしまうという問題があっ
た。Further, when the thick metal wiring layers intersect, not only the metal wiring layers are deformed, but also the temperature change amount of the insulating film sandwiched between the metal wiring layers above and below is small,
A crack is generated in the insulating film due to the force applied to the insulating film as the upper and lower metal wiring layers change. Further, there is a problem in that the metal wiring layers enter into the cracks, so that the upper and lower metal wiring layers come into contact (short).
【0008】本発明の目的は、金属配線層の熱変化を小
さく抑えた半導体集積回路装置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device in which the thermal change of the metal wiring layer is suppressed to a small level.
【0009】[0009]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体集積回路装置は、金属配線層を
有する半導体集積回路装置であって、金属配線層は、絶
縁膜を介して相対的に上下に積層して形成された多層構
造のものであり、上下に重なり交差した部分の金属配線
層は、長さ方向に沿い複数に分割されて、その配線巾が
縮小し、熱変化による変形量が小さく抑えられたもので
ある。In order to achieve the above-mentioned object, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a metal wiring layer, and the metal wiring layer is relatively disposed with an insulating film interposed therebetween. It has a multi-layer structure formed by vertically stacking, and the metal wiring layer at the portion where it overlaps and intersects vertically is divided into a plurality along the length direction, the wiring width is reduced, The amount of deformation is kept small.
【0010】[0010]
【作用】上下に重なり交差した部分の金属配線層の配線
幅を縮小することにより、熱変化による変形量を小さく
抑える。これにより、金属配線層間の絶縁膜に無理な力
が加わらず、亀裂の発生を防止できる。By reducing the wiring width of the metal wiring layer at the portions which are vertically overlapped and intersect with each other, the amount of deformation due to thermal change is suppressed to a small amount. As a result, an unreasonable force is not applied to the insulating film between the metal wiring layers, and the occurrence of cracks can be prevented.
【0011】[0011]
【実施例】以下、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【0012】(実施例1)図1(a)は、本発明の実施
例1を示す平面図、図1(b)は、図1(a)のA−
A′線断面図である。(Embodiment 1) FIG. 1A is a plan view showing Embodiment 1 of the present invention, and FIG. 1B is an A- line in FIG. 1A.
It is an A'line sectional view.
【0013】図において、金属配線層11と12は、基
板14上に絶縁膜13を介して相対的に上下に積層して
形成された多層構造のものである。In the figure, metal wiring layers 11 and 12 have a multi-layered structure formed on a substrate 14 with an insulating film 13 interposed therebetween so as to be laminated one above the other.
【0014】相対的に上下に設けられた金属配線層1
1,12のうち、上下に重なり交差した部分の金属配線
層11,12は、長さ方向に沿いスリ割り11a,12
aが設けられて複数に分割されている。Metal wiring layers 1 provided relatively above and below
Of the metal wiring layers 1 and 12, the metal wiring layers 11 and 12 at the portions that vertically overlap each other intersect with each other.
a is provided and divided into a plurality.
【0015】スリ割り11a,12aは、配線幅Lをも
つ1本の金属配線層11,12を、縮小した配線幅L1
をもつ複数の配線部11b,12bに分割したものであ
り、上下に重なり交差した部分の金属配線層11,12
は、このスリ割り11a,12aが設けられることによ
り熱変化による変形量が小さく抑えられている。尚、実
施例では、分割された配線幅L1は、15μm以下であ
る。The slits 11a and 12a are formed by reducing the wiring width L 1 of one metal wiring layer 11 and 12 having the wiring width L.
Is divided into a plurality of wiring portions 11b and 12b having
By providing the slits 11a and 12a, the deformation amount due to thermal change is suppressed to be small. In the embodiment, the divided wiring width L 1 is 15 μm or less.
【0016】したがって、本発明によれば、上下の金属
配線層11,12が重なり交差している場合に、その交
差箇所での金属配線層11,12の変形量が小さくなる
ため、上下を金属配線層11,12に挾まれた絶縁膜1
3に加えられる力が小さく抑えられ、金属配線層11,
12の熱変形による絶縁膜13の亀裂発生をなくすこと
ができる。これにより、絶縁膜13の亀裂箇所を通して
上下の金属配線層同士がショートするという事故を防止
できる。Therefore, according to the present invention, when the upper and lower metal wiring layers 11 and 12 intersect with each other, the amount of deformation of the metal wiring layers 11 and 12 at the intersecting points becomes small, so that the upper and lower metal wiring layers 11 and 12 are metalized. Insulating film 1 sandwiched between wiring layers 11 and 12
The force applied to the metal wiring layer 3 is suppressed to a small level, and the metal wiring layer 11,
The generation of cracks in the insulating film 13 due to thermal deformation of 12 can be eliminated. As a result, it is possible to prevent an accident that the upper and lower metal wiring layers are short-circuited through the cracked portion of the insulating film 13.
【0017】(実施例2)図2は、本発明の実施例2を
示す平面図である。(Second Embodiment) FIG. 2 is a plan view showing a second embodiment of the present invention.
【0018】本実施例は、重なり交差した下層の金属配
線層11のみにスリ割り11aを設けたものである。こ
の構成により、実施例1と同様に、上下を金属配線層1
1,12で挾まれた絶縁層13の亀裂発生を防止するこ
とができる。In this embodiment, the slit 11a is provided only in the lower metal wiring layer 11 which overlaps and intersects. With this configuration, similarly to the first embodiment, the upper and lower metal wiring layers 1 are formed.
It is possible to prevent the occurrence of cracks in the insulating layer 13 sandwiched between 1 and 12.
【0019】[0019]
【発明の効果】以上説明したように本発明は、上下に重
なり交差する部分の金属配線層の熱変形量を小さくした
ため、上下を金属配線層で挾まれた絶縁膜に亀裂を発生
させる大きさの力が金属配線層より加わることがなく、
絶縁膜の亀裂発生を防止できる。これにより、絶縁膜の
亀裂箇所を通した上下の金属配線層同士のショートを防
止することができる。As described above, according to the present invention, since the amount of thermal deformation of the metal wiring layers in the vertically overlapping and intersecting portions is reduced, the size of cracks in the insulating film sandwiched between the metal wiring layers at the top and bottom is generated. Force is not applied from the metal wiring layer,
It is possible to prevent cracking of the insulating film. Thereby, it is possible to prevent a short circuit between the upper and lower metal wiring layers through the cracked portion of the insulating film.
【図1】(a)は、本発明の実施例1を示す平面図、
(b)は(a)のA−A′線断面図である。FIG. 1A is a plan view showing a first embodiment of the present invention,
(B) is a sectional view taken along the line AA ′ of (a).
【図2】本発明の実施例2を示す平面図である。FIG. 2 is a plan view showing a second embodiment of the present invention.
【図3】従来例を示す平面図である。FIG. 3 is a plan view showing a conventional example.
11,12 金属配線層 13 絶縁膜 14 基板 11, 12 Metal wiring layer 13 Insulating film 14 Substrate
Claims (1)
であって、 金属配線層は、絶縁膜を介して相対的に上下に積層して
形成された多層構造のものであり、 上下に重なり交差した部分の金属配線層は、長さ方向に
沿い複数に分割されて、その配線巾が縮小し、熱変化に
よる変形量が小さく抑えられたものであることを特徴と
する半導体集積回路装置。1. A semiconductor integrated circuit device having a metal wiring layer, wherein the metal wiring layer has a multi-layered structure which is formed by relatively stacking the metal wiring layer vertically with an insulating film interposed therebetween. A semiconductor integrated circuit device characterized in that the metal wiring layer in the above portion is divided into a plurality along the length direction, the wiring width is reduced, and the amount of deformation due to thermal change is suppressed small.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17096792A JPH0613376A (en) | 1992-06-29 | 1992-06-29 | Integrated circuit device of semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17096792A JPH0613376A (en) | 1992-06-29 | 1992-06-29 | Integrated circuit device of semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0613376A true JPH0613376A (en) | 1994-01-21 |
Family
ID=15914689
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17096792A Pending JPH0613376A (en) | 1992-06-29 | 1992-06-29 | Integrated circuit device of semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0613376A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015195383A (en) * | 2009-01-16 | 2015-11-05 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
1992
- 1992-06-29 JP JP17096792A patent/JPH0613376A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015195383A (en) * | 2009-01-16 | 2015-11-05 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP2017083881A (en) * | 2009-01-16 | 2017-05-18 | 株式会社半導体エネルギー研究所 | Display device |
US10332610B2 (en) | 2009-01-16 | 2019-06-25 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device including the same |
US10741138B2 (en) | 2009-01-16 | 2020-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device including the same |
US11151953B2 (en) | 2009-01-16 | 2021-10-19 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device including the same |
US11468857B2 (en) | 2009-01-16 | 2022-10-11 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device including the same |
US11735133B2 (en) | 2009-01-16 | 2023-08-22 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device including the same |
US12027133B2 (en) | 2009-01-16 | 2024-07-02 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device including the same |
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