JPS62254446A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a multilayer wiring structure suitable for a highly integrated semiconductor device.

(Conventional technology) Conventionally, regarding multilayer wiring structures using interlayer films made by laminating organic and inorganic films, a preliminary report of the Second International VLSI Multilevel Interconnection Conference (held in June 1985) Collection, pages 163 to 169 (Second Intern
ational VLSI Multilevl
Interconnection Conf.
e (1985, June) p p163-169)
It is discussed in As LSIs become more highly integrated and performant, the amount of wiring on an LSI chip increases, and the level difference on the chip surface becomes more severe, necessitating a multilayer wiring structure with excellent flatness. In response to this request, 1
There is a multilayer wiring structure using a glabellar film in which an organic film and an inorganic film are laminated according to this document. In this structure, the top surface of the organic film is all at a higher level than the surface of the underlying wiring metal, and the organic film is thicker than the upper inorganic film.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into consideration wiring in fine patterns for items with through holes at various levels or steps at various levels, and although flatness can be ensured, conversely It was difficult to ensure continuity through the through holes. That is, since the organic film is thick, there is a problem that side etching of the organic film occurs during processing of the organic film after processing of the inorganic film, resulting in an overhang of the inorganic film. Further, the organic film is thicker in the case where the lower wiring metal is at the lowest level than in the case where the lower layer metal is at the higher level, causing the above-mentioned problem and the aspect ratio of the through hole being very large.

The object of the present invention is to solve the above-mentioned drawbacks of the prior art.

An object of the present invention is to provide a semiconductor device having a multilayer wiring structure that can ensure flatness and conduction through fine through holes.

[Means for solving problems]

The above purpose is to create an interlayer film in which the organic film is formed so that the top surface of the organic film is lower than the top surface of the lower layer wiring at the highest level and higher than the top surface of the lower layer wiring at the lowest level, and an inorganic film is placed on top of the organic film. This is achieved by creating a multilayer wiring structure having the following characteristics.

[Effect]

In the present invention, by changing the thickness of the organic film according to the level of the lower wiring metal dust, flatness is ensured, and the organic film in the through-hole forming area is made as thin as possible, so that the through hole can be easily established. It has a structure that allows for a hole shape.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1 and FIG. 2 showing the manufacturing process thereof.

Oxidation, 1112. First gate electrode 3. Second gate electrode 4
A thick organic film 6 is formed on the surface of the semiconductor substrate 1 having the first layer interconnection metal 5 at various levels.
Flatten it as shown in 1). The organic film is preferably made of polyimide. Then, as shown in FIG. It is scraped off from the surface so that it comes between it and the upper surface of the layer wiring metal 5b.

Next, an inorganic film 7 is formed on the surface as shown in FIG. 2 (3). The inorganic film is preferably a plasma oxide film or a nitride oxide film in terms of adhesion with the organic film, crack resistance, and formation temperature.
The thickness of the inorganic film 7 is small and is set to the thickness necessary to ensure the common glabellar withstand pressure.In the case of this example, it is set to 0.6 μm.
Next, a pattern of through holes is formed by a known phosphorography technique, and the inorganic film 7 is etched using a photoresist as a mask. Subsequently, using the inorganic film 7 as a mask, the organic film 6 is etched to form a through hole 8 of 1.4 μm square to obtain the structure shown in FIG. 2(4). Finally, a second layer wiring metal 9 is formed to obtain the multilayer wiring structure of the present invention shown in FIG. set to a low level.

At this time, the organic film thickness on the low level first layer wiring metal 5b is 0.4 μm. This thickness is thinner than an inorganic film. In this state, there is no inorganic membrane eaves.

In addition, since the aspect ratio of the through hole is 1.0 or less, sufficient conduction through the through hole can be ensured.

FIG. 3 shows another example, in which there is no through hole on the highest level first layer wiring metal 5a.

FIG. 4 shows an embodiment applied to three-layer wiring. An organic film 6 and an inorganic film 7 between the first M wiring metal 5 and the second layer wiring metal 9 and an organic film 6 between the second layer wiring metal 9 and the third layer wiring metal 10. It is applied to the inorganic film 7, and can ensure flatness and through-hole conduction even in multilayers of three or more layers.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a semiconductor device including a high-density multilayer wiring in which flatness and conduction through fine through holes are ensured.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device having a multilayer wiring structure according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of each step showing the manufacturing process of the embodiment shown in FIG. 1. Figure 4 shows a cross-sectional view of a semiconductor device having a multilayer wiring structure according to another embodiment of the present invention. 1... Silicon substrate, 2... Oxide film, 3... First
Gate electrode, 4... second gate electrode, 5... first layer wiring metal. 6...Organic film, 7...Inorganic film, 8...Through hole, 9 Satoru 1 Mouth 9...1mu4 詑 bar 3rd Kokuryo 40

Claims (1)

[Claims] 1. In a semiconductor device in which an insulating film and wiring metal are stacked in multiple layers on a semiconductor substrate, the upper surface of the organic film is lower than the upper surface of the lower wiring metal at the highest level, and the lowest level 1. A semiconductor device characterized by having an interlayer film which is higher than the upper surface of a lower layer wiring metal and has an inorganic film formed thereon. 2. A semiconductor device according to claim 1, characterized in that the thickness of the organic film at the location where the through hole is to be formed is thinner than the co-inorganic film. 3. A semiconductor device according to claim 2, characterized in that the organic film is made of polyimide. 4. A semiconductor device according to claim 2, wherein the inorganic film is formed by plasma vapor deposition.