JPH06105780B2 - Method of manufacturing integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing an optoelectronic integrated circuit in which an optical element and an electronic element are integrated and used for optical fiber communication and the like.

[Conventional technology]

As a reception front end for optical fiber communication, there is known a structure in which a pin photodiode (PIN-PD) which is a light receiving element and a field effect transistor (FET) or a bipolar transistor which are electronic elements are integrated on a hybrid substrate. .

Also, a structure in which PIN-PD and FET are monolithically integrated on an InP substrate has already been manufactured.

[Problems to be Solved by the Invention]

An integrated light receiving element and electronic element on a hybrid substrate has each element mounted by soldering, which is less reliable than a monolithic type.
Not suitable for mass production.

On the other hand, the conventional monolithic device described above does not include a bipolar transistor. The receiving front end of optical fiber communication is preferably a FET with high input impedance and low shot noise in the first stage, and a bipolar transistor with high mutual conductance in the subsequent stages. Therefore, there is a demand for a PIN-PD, an FET, and a bipolar transistor in which all three types of elements are monolithically integrated on the same semiconductor substrate, but such an integrated circuit has not been developed yet.

Especially when integrating a PIN-PD and a high electron mobility transistor (HEMT), which is a type of FET, and a heterojunction bipolar transistor (HBT) on an InP semiconductor substrate, they all have different epitaxial layer structures. However, if it is attempted to fabricate an integrated circuit by simply gathering together conventional techniques for forming each element, it is expected that the process will become very complicated.

[Means for Solving the Problems]

In order to solve the above problems, the method for manufacturing an integrated circuit according to the present invention is such that an n-type layer for a PIN-PD is made of In on an InP semiconductor substrate.
An epitaxial crystal in which the P and i-type layers are GaInAs and the p-type layers are InP or GaInAs, and the electron supply layer is AlInA for HEMT.
s, an epitaxial crystal in which the active layer is GaInAs, an epitaxial crystal in which the subcollector layer is InP, the collector layer is GaInAs, the base layer is GaInAs, and the emitter layer is InP for HBT are formed. so,
It is characterized in that the n-type layer of the PIN-PD crystal is partially exposed, the sub-collector layer of the HBT crystal is partially exposed, and the unnecessary region of the HEMT crystal is removed at the same time.

[Action]

Since GaInAs and AlInAs can be selectively etched with respect to InP, the i-type layer (P-type layer is GaI
In the case of nAs, the p-type layer and i-type layer), the base layer and collector layer of the HBT crystal, and the HEMT crystal in the unnecessary region are simultaneously etched, and the n-type layer of the PIN-PD crystal is exposed. Etching is automatically stopped at the HBT crystal when the sub-collector layer is exposed, and the HEMT crystal at the unnecessary region is automatically stopped when the substrate is exposed.

〔Example〕

FIG. 1 is a process sectional view showing an embodiment of the present invention.
On the prepared indium phosphide (InP) semiconductor substrate 1, the normal epitaxial growth technique and the epitaxial selective growth technique using the selective growth mask are used,
The HEMT epitaxial crystal 3 for the HEMT in the HEMT region 2 is PIN-P
Epitaxial crystal 5 for PIN-PD in D region 4,
Epitaxial crystals 7 for HBT are respectively formed in the HBT regions 6 (see FIG. 1 (A)).

The HEMT crystal 3 is composed of a GaInAs layer 8 serving as an active layer and an n-type AlInAs layer 9 serving as an electron supply layer. PIN-PD
The crystal for use 5 is composed of an n-type InP layer 10 serving as an n-type layer, an i-type GaInAs layer 11 serving as an i-type layer, and a p-type InP layer 12 serving as a p-type layer. The HBT crystal 7 serves as a sub-collector layer n
The InP layer 13 includes a p-type GaInAs layer 15 serving as a collector layer and an n-type InP layer 16 serving as an emitter layer. Note that H
When the crystal 3 for EMT is formed, HEMT is also applied to the HEMT unnecessary region 17.
A GaInAs layer and an n-type AlInAs layer which are crystal for use are formed.

In this example, as the epitaxial growth method, a metal organic chemical vapor deposition method (OMVPE) at a reduced pressure of 100 Torr or less, which exhibits excellent selective growth properties, is used. The metal temperature is about 600 ° C. to 700 ° C., and the reaction gas is appropriately selected for each formation or semiconductor layer. Trimethylindium (TMI) and phosphine (PH ₃ ) are used as reaction gases for the epitaxial growth of the InP layer. For the epitaxial growth of GaInAs, trimethylgallium (TM
G), trimethylindium (TMI) and arsine (As
H ₃ ) is used. For the epitaxial growth of the AlInAs layer, trimethyl aluminum (TMA) as a reaction gas,
Trimethyl indium (TMI) and arsine (AsH ₃₎
Is used.

Also, as a selective growth mask, silicon nitride (SiN _x ) is used.
A film or a silicon oxide (SiO ₂ ) film is used.

Next, after depositing a silicon nitride film on the entire surface, a resist is applied, the resist is patterned by using a photolithography technique, and the silicon nitride film is further patterned using the patterned resist as a mask, Patterned etching masks 18 and 19 made of a silicon nitride film and a resist film are formed. A silicon oxide film may be used for the masks 18 and 19 instead of the silicon nitride film. Then, the p-type layer 12 of the PIN-PD crystal 5 and the emitter layer 16 of the HBT crystal 7 are
Etching is performed while masking a part of the masks 18 and 19 (see FIG. 1B).

At this time, as an etchant, GaInAs and AlInAs are not etched, but when InP is etched, an etchant, for example, HCl: H ₃ PO ₄ is used. Therefore, so-called selective etching is performed, and the p-type layer 12 and the emitter layer are etched. 16 etching stops automatically.

Next, in a predetermined area of the HEMT area 2 and the HBT area 6,
Patterned masks 20 and 21 made of the above-mentioned silicon nitride film (or silicon oxide film) and resist film are formed. Then, etching is performed while masking a predetermined area with the masks 18, 20 and 21, and i of the PIN-PD crystal 5 is
Mold layer 11, base layer 15 of HBT crystal 7, and collector layer 1
4, electron supply layer 9 and active layer 8 of HEMT crystal 3 (HEMT
(Including the unnecessary area) is removed (see FIG. 1 (C)).

At this time, without etching InP as an etchant,
Since an etchant for etching aInAs and AlInAs, for example, H ₂ SO ₄ : H ₂ O ₂ is used, so-called selective etching is performed, and i-type layer 11, base layer 15, collector layer 14, electron supply layer The etching of 9 and the active layer 8 stops automatically. If the sub-collection layer 13 of the HBT crystal 7 and the n-type layer 10 of the PIN-PD crystal 5 are not InP but Ga
If it was composed of InAs, the etching here would be layer 13
Or it must be stopped when any of the 10 layers are exposed. However, the thickness of the i-type layer of PIN-PD is generally 2 μm or more, and the total thickness of the base layer and collector layer of HBT is generally 1 μm or less. And the time until the HBT subcollector layer is exposed is different. Therefore, the n-type layer of PIN-PD and the subcollector layer of HBT cannot be exposed at the same time. That is, in this embodiment, the n-type layer of the PIN-PD and the HBT
The sub-collector layer of is composed of InP, and the electron supply layer and the active layer of HEMT are composed of n-type AlInAs and GaInAs, respectively, so that so-called selective etching is possible, and the PIN-PD crystal 5 I-type layer 11, HBT base layer 15,
The HEMT crystals in the collector layer 14 and the unnecessary region 17 can be simultaneously etched.

After the above etching process, the PIN electrodes of the PIN-PD 22 and n
The electrode 23, the source electrode 24 of the HEMT, the drain electrode 25, the gate electrode 26, the emitter electrode 27 of the HBT, the base electrode 28, and the collector electrode 29 are formed (see FIG. 1 (D)), and the necessary wiring is provided. As a result, a desired integrated circuit is completed.

FIG. 2 is a process sectional view showing another embodiment of the present invention. In this example, the p-type layer of the PIN-PD crystal is not InP
It is different from the embodiment of FIG. 1 in that it is GaInAs. In addition,
The same or corresponding portions as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

PIN-PD crystal 105, HEMT crystal 3 and H on InP substrate 1
After the BT crystal 7 is formed (see FIG. 2 (A)), HBT
A mask 19 made of a resist film and a silicon nitride film is formed on the emitter layer 16 of the crystal for use 7. Then, selective etching is performed while masking a predetermined region with the mask 19 to expose the base layer 15 of the HBT crystal 7 (see FIG. 2 (B)).

Further, masks 18, 20, and 21 made of a resist film and a silicon nitride film are formed, and selective etching is performed while shielding desired regions by these, i-type layer 11 of PIN-PD crystal 105, base layer of HBT. 15, collector layer 14 and unused area 1
The HEMT crystal of No. 7 is simultaneously removed by etching (see FIG. 2 (C)). Then, the required electrodes 22 to 29 are formed,
(See FIG. 2D) Finally, wiring is applied to complete the desired integrated circuit.

〔The invention's effect〕

As described above, according to the method for manufacturing an integrated circuit of the present invention, the i-type layer of the PIN-PD crystal (P-type layer and i-type layer when the p-type layer is GaInAs) and the base of the HBT crystal are used. Layer and collector layer, and HEMT crystal in the unnecessary area at the same time,
Moreover, etching can be performed without strictly controlling the etching time. Therefore, an integrated circuit including PIN-PD, HEMT and HBT can be obtained in a short time.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing an integrated circuit according to an embodiment of the present invention, and FIG. 2 is a process sectional view showing another embodiment of the present invention. 1 ... InP substrate, 3 ... HEMT crystal, 5,105 ... PIN-PD crystal, 7 ... HBT crystal, 8 ... Active layer, 9 ... Electron supply layer, 10
... n-type layer, 11 ... i-type layer, 12,112 ... p-type layer, 13 ... subcollector layer, 14 ... collector layer, 15 ... base layer, 16 ... emitter layer, 18-21 ... mask.

Claims (2)

[Claims] 1. An epitaxial crystal for a pin photodiode having an n-type layer of InP, an i-type layer of GaInAs, and a p-type layer of InP on an InP semiconductor substrate, an electron supply layer of AlInAs, and an active layer of GaIn.
Epitaxial crystal for high electron mobility transistor, which is As, and epitaxial crystal for heterojunction bipolar transistor, in which the subcollector layer is InP, the collector layer is GaInAs, the base layer is GaInAs, and the emitter layer is InP, are formed in different regions. A step of exposing the i-type layer and a part of the base layer by etching away the p-type layer of the pin photodiode and the emitter layer of the heterojunction bipolar transistor, respectively. -Type layer of epitaxial crystal for semiconductor, base layer and collector layer of epitaxial crystal for heterojunction bipolar transistor, and electron supply layer and active layer of epitaxial crystal for high-electron-mobility transistor are partially removed at the same time by etching to form an n-type layer And And exposing a part of the subcollector layer and leaving only the necessary region of the epitaxial crystal for the high electron mobility transistor, on the p-type layer and the n-type layer of the pin photodiode epitaxial crystal, and the epitaxial crystal for the heterojunction bipolar transistor. And a step of forming necessary electrodes on the emitter layer, the base layer and the subcollector layer, and on the electron supply layer of the epitaxial crystal for the high electron mobility transistor, respectively. 2. A pin photodiode epitaxial crystal having an n-type layer of InP, an i-type layer of GaInAs and a p-type layer of GaInAs on an InP semiconductor substrate, an electron supply layer of AlInAs and an active layer of
GaInAs epitaxial crystal for high electron mobility transistors, InP for the subcollector layer and GaInA for the collector layer
s, the base layer is GaInAs, and the emitter layer is InP, the step of forming a heterojunction bipolar transistor epitaxial crystal in regions different from each other, and the heterojunction bipolar transistor epitaxial crystal emitter layer is partially removed by etching. To expose a part of the base layer, and the p-type and i-type layers of the pin photodiode epitaxial crystal and the base layer and collector layer of the heterojunction bipolar transistor epitaxial crystal and the electron of the high electron mobility transistor epitaxial crystal. A step of exposing the n-type layer and a part of the subcollector layer by etching away the supply layer and the active layer at the same time, and leaving only the necessary region of the epitaxial crystal for the high electron mobility transistor, and the epitaxial layer for the pin photodiode. P-type layer of crystal And the n-type layer, the emitter layer of the epitaxial crystal for the heterojunction bipolar transistor, the base layer and the subcollector layer, and the electron supply layer of the epitaxial crystal for the high electron mobility transistor. A method of manufacturing an integrated circuit having the same.