JPS6334994A - Photoelectric integrated circuit device and manufacture thereof - Google Patents
Photoelectric integrated circuit device and manufacture thereofInfo
- Publication number
- JPS6334994A JPS6334994A JP17953386A JP17953386A JPS6334994A JP S6334994 A JPS6334994 A JP S6334994A JP 17953386 A JP17953386 A JP 17953386A JP 17953386 A JP17953386 A JP 17953386A JP S6334994 A JPS6334994 A JP S6334994A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- layer
- optoelectronic integrated
- strain relaxation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 24
- 230000003287 optical effect Effects 0.000 claims abstract description 19
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 5
- 230000005693 optoelectronics Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 5
- 239000007791 liquid phase Substances 0.000 claims description 3
- 229910008310 Si—Ge Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 2
- 238000005979 thermal decomposition reaction Methods 0.000 claims 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 238000005253 cladding Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、光電子集積回路装置く以下０ＥＩＣという
）およびその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optoelectronic integrated circuit device (hereinafter referred to as 0EIC) and a manufacturing method thereof.
第３図は、例えば日経エレクトロニクス１９８６年２月
１０日号ＰＰ２１８に示されたＹａｒｉｖ氏らの試作し
た０ＥＩＣを示す斜視図である。この図において、２ｏ
は半絶縁性ＧａＡｓ基板、２１は前記ＧａＡｓ基板２Ｑ
上に形成された半導体レーザ部、２２ば前記ＧａＡｓ基
板２０上に形成されたＦＥＴ部、２３は前記ＧａＡｓ基
板２０上に形成されたＰＤ（フォトダイオード）部であ
る。FIG. 3 is a perspective view showing an 0EIC prototyped by Mr. Yariv et al., which was shown in Nikkei Electronics February 10, 1986 issue PP218, for example. In this figure, 2o
21 is the semi-insulating GaAs substrate, and 21 is the GaAs substrate 2Q.
22 is a FET section formed on the GaAs substrate 20, and 23 is a PD (photodiode) section formed on the GaAs substrate 20.
次に動作について説明する。Next, the operation will be explained.
入力光はＰＤ部２３で電気信号に変換されたのち、ＦＥ
Ｔ部２２により増幅され、そして、増幅された信号電流
は半導体レーザ部２１を駆動し、し・−ザ光が出力され
ろ。The input light is converted into an electrical signal by the PD section 23, and then sent to the FE.
The T section 22 amplifies the signal current, and the amplified signal current drives the semiconductor laser section 21 to output laser light.
上記のような従来の０ＥＩＣは、電子回路をＧａＡｓ基
板２０上に構成しなければならず、従来のＩＣ製造技術
をそのまま用いることができない。また、基板としてＳ
ｉを用いろ０ＥＩＣも提案されているが、このタイプの
０ＥＩＣにおいては、Ｓｉ基板上にエピタキシャル成長
したＧａＡｓ等■−■族化合物の結晶性が悪く、形成さ
れるし・−ザ等の光素子の信頼性が悪いという問題点が
あった。In the conventional 0EIC as described above, the electronic circuit must be constructed on the GaAs substrate 20, and conventional IC manufacturing technology cannot be used as is. Also, as a substrate, S
0EIC using i has also been proposed, but in this type of 0EIC, the crystallinity of ■-■ group compounds such as GaAs epitaxially grown on a Si substrate is poor, and the formation of optical devices such as There was a problem with poor reliability.
この発明は、かかる問題点を解決するためになされたも
ので、製造が容易で、かつ光素子を構成するエピタキシ
ャル層の結晶性を損なうことのない０ＥＩＣおよびその
製造方法を得ることを目的とする。The present invention was made to solve these problems, and aims to provide an 0EIC that is easy to manufacture and does not impair the crystallinity of the epitaxial layer constituting an optical element, and a method for manufacturing the same. .
この発明に係る０ＥＩＣは、■−■族化合物半導体基板
上に順次形成された光素子を構成するのに必要な複数の
半導体層と、これらの半導体層の最上部に形成された歪
緩和層と、この歪緩和層上に形成された電子回路部が形
成されるＳｉエピタキシャル層とから構成したものであ
る。The 0EIC according to the present invention includes a plurality of semiconductor layers necessary for constructing an optical device that are sequentially formed on a ■-■ group compound semiconductor substrate, and a strain relaxation layer formed on the top of these semiconductor layers. , and a Si epitaxial layer in which an electronic circuit section is formed on the strain relaxation layer.
また、この発明の別の発明に係る０ＥｒＣの製造方法は
、ＩＮ−Ｖ族化合物半導体基板上に光素子を構成するの
に必要な複数の半導体層、歪緩和層。Further, a method for manufacturing 0ErC according to another aspect of the present invention includes a plurality of semiconductor layers and strain relaxation layers necessary for constructing an optical element on an IN-V group compound semiconductor substrate.
Ｓｉエピタキシャル層を順次エピタキシャル成長させろ
工程と、半導体基板から歪緩和層までをエツチングして
Ｓｉエピタキシャル層を露出させて電子回路部を形成す
る工程とを含むものである。This method includes a step of sequentially epitaxially growing Si epitaxial layers, and a step of etching from the semiconductor substrate to the strain relaxation layer to expose the Si epitaxial layer to form an electronic circuit section.
この発明においては、電子回路部が８１工ピタキシヤル
層上に形成され、信頼性が向上する。In this invention, the electronic circuit portion is formed on the 81-layer pitaxial layer, improving reliability.
また、この発明の製造方法においては、歪緩和層を介し
てＳｉエビタキンヤル層が光素子を構成するのに必要な
複数の半導体層上に成長される。Further, in the manufacturing method of the present invention, a Si vitreous layer is grown on a plurality of semiconductor layers necessary for constructing an optical device via a strain relaxation layer.
第１図はこの発明の０ＥＩＣの一実施例を示す断面図で
ある。この図において、１はＧａＡｓ基板、２．・３，
４はそれぞれ光素子を構成するのに必要な半導体層とし
てのＡｊ’ＧａＡｓ下クラッド層。FIG. 1 is a sectional view showing an embodiment of the 0EIC of the present invention. In this figure, 1 is a GaAs substrate, 2.・３、
Reference numeral 4 denotes an Aj'GaAs lower cladding layer as a semiconductor layer necessary for constructing each optical element.
ＡＩ！ＧａＡｓ活性層、ＡＪＧａＡＳ上クラッド層、５
はＡｌＡｓ−ＧａＡｓ超格子からなる歪緩和層、６はＳ
ｉエピタキシャル層、７はレーザ電極、８は光素子とし
ての半導体レーザ部、１５は電子回路部で、ソース領域
９．ドし・イン領域１０．ゲート酸化膜１１．ソース電
極１２．ゲート電極１３゜ドし・イン電極１４とから構
成され、ここでばＦＥＴが構成されている。AI! GaAs active layer, AJGaAS upper cladding layer, 5
is a strain relaxation layer made of AlAs-GaAs superlattice, 6 is S
i epitaxial layer, 7 a laser electrode, 8 a semiconductor laser section as an optical element, 15 an electronic circuit section, and a source region 9. Do/in area 10. Gate oxide film 11. Source electrode 12. It is composed of a gate electrode 13 and an in-electrode 14, and here an FET is constructed.
すなわち、この発明の０ＥＩＣでは、光の入出力がＡｊ
’ＧａＡｓ系材料で構成された半導体レーザｍ８．ＬＥ
Ｄ、ＰＤ（図示せず）などで行われ、増幅などの信号の
処理および光素子の駆動は、Ｓｉエピタキシャル層６上
に形成された電子回路部］５で行われる。また電子回路
部１５をＳｉエピタキシャル層６上に形成しているので
、従来のＩＣ技術で形成することができる。That is, in the 0EIC of this invention, the input and output of light is Aj
'Semiconductor laser m8 made of GaAs-based material. L.E.
Processing of signals such as amplification and driving of optical elements are performed in an electronic circuit section 5 formed on the Si epitaxial layer 6. Furthermore, since the electronic circuit section 15 is formed on the Si epitaxial layer 6, it can be formed using conventional IC technology.
次に、第２図（ａｌ、（ｂ）を用いてこの発明の０ＥＩ
Ｃの製造方法について説明する。これらの図において、
第１図と同一符号は同一部分を示し、１６はフォトレレ
ス）・である。Next, using FIG. 2 (al, (b)), the 0EI of this invention is
The manufacturing method of C will be explained. In these figures,
The same reference numerals as in FIG. 1 indicate the same parts, and 16 is a photores.
まず、第２図（ａ）に示すように、ＧａＡｓ基板１上に
半導体レーザ部８を構成するのに必要なＡｔ’ＧａＡｓ
下クラッド層２．ＡＪＧａＡｓ活性層３．ＡｌＧａＡｓ
上クラッド層４を順次エピタキシャル成長させた後、歪
緩和層５およびＳｉエピタキシャルＨ６を成長させる。First, as shown in FIG. 2(a), At'GaAs is
Lower cladding layer 2. AJGaAs active layer 3. AlGaAs
After the upper cladding layer 4 is epitaxially grown in sequence, the strain relaxation layer 5 and the Si epitaxial layer H6 are grown.
次に第２図（ｂ）に示すように、電子回路部１５を形成
する場所以外のところをフォトレジスト
スクし、電子回路部１５を形成する場所のみを選択エツ
チングによりＧａＡｓ基板１側から歪緩和層５まで除去
し、Ｓｉエピタキシャル層６のｉ面を露出させる。次い
で、通常のＩＣ技術によりＳ１工ピタキシヤル層６の裏
面上に電子回路部１５を形成ずろとともに、レーザ電極
７の形成を行う。Next, as shown in FIG. 2(b), photoresist is applied to areas other than the area where the electronic circuit part 15 is to be formed, and the strain is relaxed from the GaAs substrate 1 side by selective etching only at the area where the electronic circuit area 15 is to be formed. The layer 5 is removed to expose the i-plane of the Si epitaxial layer 6. Next, an electronic circuit section 15 is formed on the back surface of the S1 pitaxial layer 6, and a laser electrode 7 is formed using a normal IC technique.
すなわち、この発明のＯＥＩＣの製造方法は、半導体レ
ーザ部８を構成するのに必要なＡｔ’ＧａＡｓ下クラッ
ド層２，Ａｊ’ＧａＡｓ活性層３，Ａ／ＧａＡｓ上クラ
ッ，ドり４を順次エピタキシャル成長させた後、歪緩和
層５を介してＳｉエピタキシャル層６を成長させるので
、半導体レーザ部８を構成するＡｌＧａＡｓ上クラッド
層２，ＡｔｌＧａＡｓ活性層３，ＡｔｌＧａＡｓ上クラ
ッド層４内の結晶性を損なうことがない。That is, the method for manufacturing an OEIC of the present invention involves sequentially epitaxially growing the At'GaAs lower cladding layer 2, the Aj'GaAs active layer 3, the A/GaAs upper cladding layer 4, and the Aj'GaAs upper cladding layer 4 necessary for forming the semiconductor laser section 8. After that, the Si epitaxial layer 6 is grown through the strain relaxation layer 5, so that the crystallinity in the AlGaAs upper cladding layer 2, AtlGaAs active layer 3, and AtlGaAs upper cladding layer 4 that constitute the semiconductor laser section 8 is not impaired. do not have.
なお、上記実施例では電子回路部１５をＳｉエピタキシ
ャル層６の裏面に設けたものを示したが、表面に設けて
もよいことはいうまでもない。In the above embodiment, the electronic circuit section 15 is provided on the back surface of the Si epitaxial layer 6, but it goes without saying that it may be provided on the front surface.
また、上記実施例では基板にＧａＡｓを用い、半導体レ
ーザ等の光素子を構成するのに必要な半導体層にＡｉＧ
ａＡｓ系材料を用いたものを示したが、基板にＩｎＰを
用い、半導体レーザ等の光素子を構成するのに必要な半
導体層にＩｎＧａＡＳＰ系材料を用いてもよいことはい
うまでもない。In addition, in the above embodiment, GaAs is used for the substrate, and AiG is used for the semiconductor layer necessary for constructing an optical device such as a semiconductor laser.
Although a case using an aAs-based material is shown, it goes without saying that InP may be used for the substrate and an InGaASP-based material may be used for the semiconductor layer necessary to construct an optical element such as a semiconductor laser.
さらに、上記実施例では歪緩和層５にＡＩＡｓ−ＧａＡ
ｓ超格子を用いたが、Ｓｉ−Ｇｅ超格子を用いても，よ
いことはいうまでもない。Furthermore, in the above embodiment, the strain relaxation layer 5 is made of AIAs-GaA.
Although the s superlattice was used, it goes without saying that a Si-Ge superlattice may also be used.
またさらに、エピタキシャル層の成長方法としては、分
子線法，有機金属法，＃１分解法，液相法のいずれを用
いてもよい。Furthermore, as a method for growing the epitaxial layer, any of the molecular beam method, organometallic method, #1 decomposition method, and liquid phase method may be used.
この発明に係るＯＥＩＣは以上説明したとおり、■−■
族化合物半導体基板上に順次形成された光素子を構成す
るのに必要な複数の半導体層と、これらの半導体層の最
上部に形成された歪緩和層と、この歪緩和層上に形成さ
れた電子回路部が形成されるＳｉエピタキシャル層とか
ら構成したので、電子回路部を容易に形成でき、信頼性
も高いという効果がある。As explained above, the OEIC according to this invention is as follows:
A plurality of semiconductor layers necessary to construct an optical device are sequentially formed on a group compound semiconductor substrate, a strain relaxation layer formed on the top of these semiconductor layers, and a strain relaxation layer formed on the strain relaxation layer. Since it is composed of the Si epitaxial layer on which the electronic circuit section is formed, the electronic circuit section can be easily formed and the reliability is also high.
また、この発明に係るＯＥｆＣの製造方法は、［−Ｖ族
化合惚半導体基板上に光素子を構成するのに必要な複数
の半導体層，歪緩和層，Ｓｉエピタキシャル層を順次エ
ピタキシャル成長させる工程と、半導体基板から歪緩和
層までをエツチングしてＳｉエピタキシャル層を露出さ
せて電子回路部を形成する工程とを含むので、容易な製
造技術で結晶性を損なうことなく、高い信頼性のＯＥＩ
Ｃの製造方法が得られるという効果がある。Further, the method for manufacturing an OEfC according to the present invention includes a step of sequentially epitaxially growing a plurality of semiconductor layers, a strain relaxation layer, and a Si epitaxial layer necessary for constructing an optical device on a -V group composite semiconductor substrate; This process includes the process of etching the semiconductor substrate up to the strain relaxation layer to expose the Si epitaxial layer to form the electronic circuit section, so it is possible to achieve highly reliable OEI without impairing crystallinity using easy manufacturing technology.
This has the effect that a method for manufacturing C can be obtained.
第１図はこの発明の０ＥＩＣの一実施例を示す断面図、
第２図はこの発明の０ＥＩＣの製造方法の一実施例を示
す断面図、第３図は従来の０ＥＩＣを示す断面図である
。
図において、１はＧａＡｓ基板、２はＡｌＧａＡｓ下ク
ラッド層、３はＡｊ’ＧａＡｓ活性層、４はＡＩ！Ｇａ
Ａｓ上クラッド層、５は歪緩和層、６はＳｉエピクキン
ヤル層、７はし・−ザ電極、８は半導体しｆ部、９１；
ｔソース領域、１ｏはドレイン領域、１１はゲート酸化
膜、１２はソース電極、１３はゲー）・電極、１４はド
レイン電極、１５は電子回路部である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
Ｔ り ： ’Ｍｌｊ−凹λト節
第１１
節第２FIG. 1 is a sectional view showing an embodiment of the 0EIC of the present invention;
FIG. 2 is a sectional view showing an embodiment of the method for manufacturing an 0EIC according to the present invention, and FIG. 3 is a sectional view showing a conventional 0EIC. In the figure, 1 is a GaAs substrate, 2 is an AlGaAs lower cladding layer, 3 is an Aj'GaAs active layer, and 4 is an AI! Ga
As upper cladding layer; 5, strain relaxation layer; 6, Si epitaxial layer; 7, the electrode; 8, semiconductor f section; 91;
t source region, 1o a drain region, 11 a gate oxide film, 12 a source electrode, 13 a gate electrode, 14 a drain electrode, and 15 an electronic circuit section. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 T: 'Mlj-Concave λT clause 11 Clause 2
Claims (16)
光素子を構成するのに必要な複数の半導体層と、これら
の半導体層の最上部に形成された歪緩和層と、この歪緩
和層上に形成された電子回路部が形成されるＳｉエピタ
キシャル層とで構成したことを特徴とする光電子集積回
路装置。(1) A plurality of semiconductor layers necessary for constructing an optical device that are sequentially formed on a III-V compound semiconductor substrate, a strain relaxation layer formed on the top of these semiconductor layers, and a strain relaxation layer formed on the top of these semiconductor layers. 1. An optoelectronic integrated circuit device comprising a Si epitaxial layer on which an electronic circuit section is formed.
とを特徴とする特許請求の範囲第（１）項記載の光電子
集積回路装置。(2) The optoelectronic integrated circuit device according to claim (1), wherein the III-V compound semiconductor substrate is GaAs.
を特徴とする特許請求の範囲第（１）項記載の光電子集
積回路装置。(3) The optoelectronic integrated circuit device according to claim (1), wherein the III-V group compound semiconductor substrate is InP.
ｌＧａＡｓ系材料で構成されたことを特徴とする特許請
求の範囲第（１）項記載の光電子集積回路装置。(4) A plurality of semiconductor layers necessary to constitute an optical element
The optoelectronic integrated circuit device according to claim (1), characterized in that it is made of lGaAs-based material.
ｎＧａＡｓＰ系材料で構成されたことを特徴とする特許
請求の範囲第（１）項記載の光電子集積回路装置。(5) The multiple semiconductor layers necessary to configure the optical device are
The optoelectronic integrated circuit device according to claim 1, wherein the optoelectronic integrated circuit device is made of an nGaAsP-based material.
たことを特徴とする特許請求の範囲第（１）項記載の光
電子集積回路装置。(6) The optoelectronic integrated circuit device according to claim (1), wherein the strain relaxation layer is composed of an AlAs-GaAs superlattice.
特徴とする特許請求の範囲第（１）項記載の光電子集積
回路装置。(7) The optoelectronic integrated circuit device according to claim (1), wherein the strain relaxation layer is composed of a Si-Ge superlattice.
対側の面に構成したものであることを特徴とする特許請
求の範囲第（１）項記載の光電子集積回路装置。(8) The optoelectronic integrated circuit device according to claim (1), wherein the Si epitaxial layer has an electronic circuit formed on a surface opposite to the strain relaxation layer.
じ側の面に構成したものであることを特徴とする特許請
求の範囲第（１）項記載の光電子集積回路装置。(9) The optoelectronic integrated circuit device according to claim (1), wherein the Si epitaxial layer has an electronic circuit formed on the same side as the strain relaxation layer.
するのに必要な複数の半導体層、歪緩和層、Ｓｉエピタ
キシャル層を順次エピタキシャル成長させる工程と、前
記半導体基板から前記歪緩和層までをエッチングして前
記Ｓｉエピタキシャル層を露出させて電子回路部を形成
する工程とを含むことを特徴とする光電子集積回路装置
の製造方法。(10) A step of sequentially epitaxially growing a plurality of semiconductor layers, a strain relaxation layer, and a Si epitaxial layer necessary for constructing an optical device on a III-V compound semiconductor substrate, and a step of growing a plurality of semiconductor layers, a strain relaxation layer, and a Si epitaxial layer in sequence from the semiconductor substrate to the strain relaxation layer. A method for manufacturing an opto-electronic integrated circuit device, comprising the step of etching to expose the Si epitaxial layer to form an electronic circuit section.
ることを特徴とする特許請求の範囲第（１０）項記載の
光電子集積回路装置の製造方法。(11) The method for manufacturing an optoelectronic integrated circuit device according to claim (10), wherein the epitaxial growth is performed by a molecular beam method.
成長法が有機金属法であることを特徴とする特許請求の
範囲第（１０）項記載の光電子集積回路装置の製造方法
。(12) The method for manufacturing an optoelectronic integrated circuit device according to claim (10), wherein the method for growing the plurality of semiconductor layers necessary to construct the optical element is an organic metal method.
徴とする特許請求の範囲第（１０）項記載の光電子集積
回路装置の製造方法。(13) The method for manufacturing an optoelectronic integrated circuit device according to claim (10), wherein the growth method of the strain relaxation layer is an organic metal method.
熱分解法であることを特徴とする特許請求の範囲第（１
０）項記載の光電子集積回路装置の製造方法。(14) Claim (1) characterized in that the growth method of the Si epitaxial layer is a thermal decomposition method of SiH_4.
0) The method for manufacturing an optoelectronic integrated circuit device according to item 0).
成長法が液相法であることを特徴とする特許請求の範囲
第（１０）項記載の光電子集積回路装置の製造方法。(15) The method for manufacturing an opto-electronic integrated circuit device according to claim (10), wherein the method for growing the plurality of semiconductor layers necessary to construct the optical device is a liquid phase method.
する特許請求の範囲第（１０）項記載の光電子集積回路
装置の製造方法。(16) The method for manufacturing an optoelectronic integrated circuit device according to claim (10), wherein the strain relaxation layer is grown by a liquid phase method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17953386A JPS6334994A (en) | 1986-07-29 | 1986-07-29 | Photoelectric integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17953386A JPS6334994A (en) | 1986-07-29 | 1986-07-29 | Photoelectric integrated circuit device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6334994A true JPS6334994A (en) | 1988-02-15 |
Family
ID=16067416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17953386A Pending JPS6334994A (en) | 1986-07-29 | 1986-07-29 | Photoelectric integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6334994A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001059837A1 (en) * | 2000-02-10 | 2001-08-16 | Motorola Inc. | Integrated circuit |
| US6410941B1 (en) | 2000-06-30 | 2002-06-25 | Motorola, Inc. | Reconfigurable systems using hybrid integrated circuits with optical ports |
| US6427066B1 (en) | 2000-06-30 | 2002-07-30 | Motorola, Inc. | Apparatus and method for effecting communications among a plurality of remote stations |
| US6501973B1 (en) | 2000-06-30 | 2002-12-31 | Motorola, Inc. | Apparatus and method for measuring selected physical condition of an animate subject |
| US6563118B2 (en) | 2000-12-08 | 2003-05-13 | Motorola, Inc. | Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same |
| US6583034B2 (en) | 2000-11-22 | 2003-06-24 | Motorola, Inc. | Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61108187A (en) * | 1984-11-01 | 1986-05-26 | Seiko Epson Corp | Semiconductor optoelectronic device |
| JPS61141116A (en) * | 1984-12-13 | 1986-06-28 | Seiko Epson Corp | Semiconductor substrate |
-
1986
- 1986-07-29 JP JP17953386A patent/JPS6334994A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61108187A (en) * | 1984-11-01 | 1986-05-26 | Seiko Epson Corp | Semiconductor optoelectronic device |
| JPS61141116A (en) * | 1984-12-13 | 1986-06-28 | Seiko Epson Corp | Semiconductor substrate |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001059837A1 (en) * | 2000-02-10 | 2001-08-16 | Motorola Inc. | Integrated circuit |
| US6410941B1 (en) | 2000-06-30 | 2002-06-25 | Motorola, Inc. | Reconfigurable systems using hybrid integrated circuits with optical ports |
| US6427066B1 (en) | 2000-06-30 | 2002-07-30 | Motorola, Inc. | Apparatus and method for effecting communications among a plurality of remote stations |
| US6501973B1 (en) | 2000-06-30 | 2002-12-31 | Motorola, Inc. | Apparatus and method for measuring selected physical condition of an animate subject |
| US6583034B2 (en) | 2000-11-22 | 2003-06-24 | Motorola, Inc. | Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure |
| US6563118B2 (en) | 2000-12-08 | 2003-05-13 | Motorola, Inc. | Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4625225A (en) | Integrated light detection or generation means and amplifying means | |
| JPS62194691A (en) | Method for manufacturing a semiconductor optical integrated device having an optical waveguide region | |
| JPH02283067A (en) | Manufacture of integrated circuit | |
| JPS6334994A (en) | Photoelectric integrated circuit device and manufacture thereof | |
| JPH0728051B2 (en) | Semiconductor light emitting element | |
| JP3474917B2 (en) | Method for manufacturing semiconductor device | |
| US5684819A (en) | Monolithically integrated circuits having dielectrically isolated, electrically controlled optical devices | |
| JPH0685458B2 (en) | Method of manufacturing a laser having a mirror facet | |
| JPH02199877A (en) | Optical receiver and photoelectric integrated circuit | |
| JPH0685456B2 (en) | Method of manufacturing semiconductor laser device | |
| JP2682482B2 (en) | Method for manufacturing compound semiconductor integrated circuit | |
| JP2626149B2 (en) | Optoelectronic integrated circuit manufacturing method | |
| JPS62141507A (en) | Optical integrated circuit and its production | |
| JPH0710017B2 (en) | Method of manufacturing semiconductor laser device | |
| JPH02283066A (en) | Manufacture of integrated circuit | |
| JPH07106702A (en) | Manufacturing method of light emitting and receiving device | |
| JP3199414B2 (en) | Optoelectronic integrated circuit device | |
| JPH01120012A (en) | Compound semiconductor device | |
| JPS61187363A (en) | Optical integrated circuit device | |
| JPH0644614B2 (en) | Method for manufacturing optoelectronic integrated circuit | |
| JPS6215874A (en) | Compound semiconductor device | |
| JPH05218379A (en) | Optical / electronic integrated circuit device | |
| JPH08288540A (en) | Parallel light emitting / light receiving array integrated element | |
| JPS60242688A (en) | Optical amplifying light-emitting light-receiving integrated element | |
| Ahadian et al. | Monolithic OEICs using GaAs VLSI technology |