JPH06104443A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] LS made by using epitaxial wafer
The switching speed of the lateral IGBT integrated in I is increased. [Structure] Using a wafer in which a high resistance epitaxial layer of the same conductivity type is grown on a low resistance substrate, a lateral IGBT is formed in and on a diffusion well region selectively formed in the surface layer of the epi layer. . When the back surface electrode of the substrate is short-circuited to the emitter electrode of the lateral IGBT, the minority carriers accumulated in the epitaxial layer when the IGBT is off can be made to flow out from the back surface electrode to the emitter electrode, which enables high-speed switching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IG) having a high speed switching characteristic.
BT) and the control unit can be integrated in the same semiconductor element body.

[0002]

2. Description of the Related Art As a switching power supply, an LSI has been developed in which an IGBT capable of high-speed switching at several 100 kHz is used as a high breakdown voltage output element, and a control unit is integrated in the same semiconductor body to facilitate use. The IGBT has a lateral structure and is formed in the LSI as shown in FIG. That is, an p ⁺ buried region 22 is formed on the p substrate 21 immediately below the p base layer, and then an epitaxial wafer in which an n epitaxial layer 23 is grown is used. Impurities are introduced from the surface of this wafer to p. ⁺ Isolation layer 24 is formed to perform element isolation. A p base layer 4 and a p collector layer 5 are formed in the separated regions, and a gate electrode 7 is provided on the surface with a gate insulating film 6 interposed therebetween. Furthermore, a n ⁺ contact region 11 on the exposed portion of the p base layer 4 to the p ⁺ contact region 8, n ⁺ contact region 9, the p collector layer 5 p ⁺ contact region 10, and n epitaxial layer 23 is formed, p ⁺ contact region 8 and n ⁺ contact region 9
An emitter electrode 12 and a contact electrode 13 are in common contact with the p ⁺ contact region 10 and the n ⁺ contact region 11, respectively.

This lateral IGBT is generated from the emitter electrode 12 to the n ⁺ region 8 and the surface portion 25 of the p base layer 4 by applying a voltage higher than the threshold voltage to the gate electrode 7 with respect to the emitter electrode 12. N through the channel
, And an electron current flows through the n ⁺ region 11 to the collector electrode 13. As a result, the PN junction between the p collector layer 5 and the n layer 23 becomes a forward bias, and the
Holes are injected into the layer 23, and as a result, conductivity modulation is induced in the n layer 23, so that the PNP transistor including the p collector layer 5, the n layer 23, and the p base layer 4 conducts with low on-resistance.

[0004]

In the conventional structure shown in FIG. 2, when the IGBT is turned on, holes are injected into the n layer 23, so that the p collector layer 5, the n epitaxial layer 23, and the p layer are formed.
The PNP transistor made of the substrate 21 becomes saturated,
In addition to the holes being filled in the n layer 23, electrons are also stored in the p substrate 21. Therefore, when the voltage applied to the gate electrode 7 is cut off, the holes in the n-layer 23 become n ⁺ contact region.
It flows out to the collector electrode 13 through 11 in a short time, but it is a p substrate
The electrons accumulated in 21 flow out to the buried region 22 through the p substrate 21 having a high resistance, or recombine with holes and disappear due to the lifetime. Therefore, there is a drawback that the element cutoff time becomes long.

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a semiconductor device including an IGBT capable of high-speed switching, in which minority carriers accumulated on a substrate which is a substrate of an epitaxial layer can be extracted in a short time when turned off. To provide.

[0006]

In order to achieve the above object, a semiconductor device of the present invention has a first conductivity type and a low impurity concentration of one conductivity type laminated on one surface of a substrate of the first conductivity type and a high impurity concentration. A well region of the second conductivity type is selectively provided in the surface layer of the epitaxial layer, and a lateral IGBT having a channel of the first conductivity type is formed in the well region and on the surface thereof, and further contacts the other surface of the substrate. The electrode to be turned on is short-circuited with the emitter electrode of the lateral IGBT. Further, it is effective that the control unit of the lateral IGBT is integrated in the same semiconductor element body. Further, it is effective that the collector electrode of the lateral IGBT also makes ohmic contact with the well region.

[0007]

With the use of the epitaxial layer as the second conductivity type layer in which the lateral IGBT having the first conductivity type channel is formed,
The well region of the second conductivity type is formed in the low impurity concentration epitaxial layer of the first conductivity type, and the substrate of the epitaxial layer has the first conductivity type and the high impurity concentration. As a result, minority carriers accumulated in the epitaxial layer having a low impurity concentration when the IGBT is turned on can be made to flow out to the back surface electrode short-circuited with the emitter electrode through the substrate having a high impurity concentration, so that high speed switching can be performed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a lateral IG of an LSI according to an embodiment of the present invention.
The BT part is shown, and the same parts as those in FIG. 2 are denoted by the same reference numerals. The silicon wafer used for this LSI has a resistivity of 1 to 30 Ω · cm, that is, an impurity concentration of 10 ¹⁵ to
On the p ⁺ substrate 1 of 10 ¹⁶ cm ^-3 , the resistivity is 80 to 120 Ωcm,
That is, a high resistance p epitaxial layer 2 having an impurity concentration of 10 ¹⁴ cm ^-3 grown to a thickness of 50 to 100 μm is used. By the ion implantation and diffusion from the surface of the p epitaxial layer 2, the surface impurity concentration is 1 × 10 ¹⁶ cm ^-3 and the depth is 5-6.
A μm n-well 3 is formed. After that, the n layer in FIG.
23, the same p base layer 4 and p collector layer 5, the gate insulating film 6 and gate electrode 7, p formed on the surface
P ⁺ contact region 8 and n ⁺ contact region 9 in the base layer 4, and p ⁺ contact region 10 in the p collector layer 5
And an n ⁺ contact region 11 in the n layer 2 is formed.
As a result, a lateral IGBT structure is completed. In addition to the emitter electrode 12 and the collector electrode 13 on the front surface, the electrode 14 in contact with the p ⁺ substrate 1 is also formed on the back surface according to the present invention. It is connected.

In such a structure, the n well 3 is replaced by the p layer 2
The element isolation is performed by selectively forming the isolation layer 24 on the surface layer, and it is not necessary to form the isolation region 24. In addition, the electrons accumulated in the p epitaxial layer 2 at the time of turning on are transferred to the n well 3
High-speed switching can be realized by flowing out to the back surface electrode 14 via the p ⁺ substrate 1 existing directly under the entire surface. Therefore, it is not necessary to form the p ⁺ buried region 22 as a path for the electrons to the emitter electrode 12, the number of masks is reduced, and the manufacturing cost is reduced. The collector short circuit structure formed by the contact of the collector electrode 13 with the n ⁺ contact region 11 also contributes to the improvement of the switching speed.

[0010]

According to the present invention, when a lateral IGBT is formed on an epitaxial wafer, it is not formed on a high resistance epitaxial layer on a substrate of a different conductivity type, but an epitaxial layer of the same conductivity type as a low resistance substrate. By configuring the well regions of different conductivity types formed in and on the surface of the well regions, accumulated carriers in the epitaxial layer can flow out through the low resistance substrate when the IGBT is turned off, and thus high speed switching can be performed. Lateral IGB for LSI using epitaxial wafer
It is extremely effective in accumulating T.

[Brief description of drawings]

FIG. 1 is a sectional view of an IGBT portion in an LSI according to an embodiment of the present invention.

FIG. 2 is a sectional view of an IGBT portion in a conventional LSI.

[Explanation of symbols]

1 p ⁺ substrate 2 p epitaxial layer 3 n well 4 p base layer 5 p collector layer 6 gate insulating film 7 gate electrode 8 p ⁺ contact region 9 n ⁺ contact region 10 p ⁺ contact region 11 n ⁺ contact region 12 emitter electrode 13 Collector electrode 14 Back electrode

Claims (3)

[Claims] 1. A well region of a second conductivity type is selectively provided in a surface layer of a first conductivity type and a low impurity concentration laminated on one surface of a substrate of the first conductivity type and a high impurity concentration. A lateral insulated gate bipolar transistor having a channel of the first conductivity type is formed in and on the surface of the region, and an electrode contacting the other surface of the substrate is short-circuited with an emitter electrode of the lateral insulated gate bipolar transistor. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a control unit of a lateral insulated gate bipolar transistor is integrated in the same semiconductor body. 3. The semiconductor device according to claim 1, wherein the collector electrode of the lateral insulated gate bipolar transistor is also in ohmic contact with the well region.