JPH0610410Y2 - Power off detection circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a power-off detection circuit that detects power-off of an electronic device and outputs a control signal to a controlled circuit of the electronic device.

(Prior Art) In general, an electronic device does not instantaneously stop its operation even when its power is turned off, and its operation is continued for a short period until the power supply voltage is attenuated to or close to 0 level. Is to continue.

Then, conventionally, generally, a control signal is output within the above period to control a controlled circuit in an electronic device.

The power-off detection circuit is used for such control. That is, this is to prevent the operation of the controlled circuit from becoming abnormal due to the power being turned off.

FIG. 6 shows a conventional power-off detection circuit of this type. This power-off detection circuit is mechanically driven.

In FIG. 6, 21 is an external power switch, 22 is an electronic device.
23 is a power switch, 24 is a grounded power-off detection switch that is interlocked with the power switch 22, and 25 is a DC power supply that is connected to the power-off detection switch 24 via a resistor 26. 26 and power-off detection switch
24 constitutes a power-off detection circuit 27.

Next, the operation of the power-off detection circuit 27 will be described.

When the power switch 22 is on, the power-off detection switch 24 is also on and grounded, so that no control signal is output from the control signal output terminal 28.

When the power switch 22 is turned off, the power off detection switch 24 is also turned off in synchronization with this. Therefore, the ground is released, and the control signal output terminal 28 outputs the control signal.

However, the conventional example having the mechanically driven power-off detection switch 24 has the following problems.

That is, when the external power switch 21 is turned off while the power switch 22 and the power off detection switch 24 are still turned on, the power off voltage for the electronic device 23 is attenuated to 0 level, but the power off detection is performed. Since the switch 24 is not turned off, the control signal output terminal 28 does not output the control signal. That is, there is a problem that it is not possible to detect that the power supply voltage to the electronic device 23 is off.

(Purpose of the Invention) The present invention has been made in view of such circumstances, and it is possible to turn off the power switch of an electronic device or the external power switch by picking up the attenuation of the power supply voltage itself. Also, the object is to make it possible to output a control signal.

(Structure of the Invention) In order to achieve such an object, the present invention has the following structure.

The present invention has the following configuration in a power-off detection circuit that detects power-off of an electronic device and outputs a control signal to a controlled circuit of the electronic device.

The power-off detection circuit of the present invention comprises a positive voltage power supply circuit for supplying a positive voltage, a negative voltage power supply circuit for supplying a negative voltage, and a switching circuit, and the time constant of the negative voltage power supply circuit is positive. It is set smaller than the time constant of the voltage power supply circuit, and the switching circuit detects this when both output voltages of the positive and negative voltage power supply circuits converge to the ground level when the power is turned off, In addition to outputting, the switching circuit conducts when the deviation between both output voltages of the positive and negative voltage power supply circuits is greater than or equal to a predetermined value,
A first transistor which becomes non-conductive in response to a rapid rise in the negative output voltage of the negative voltage power supply circuit due to power off, and when the first transistor is in the conductive state, the collector voltage of which is lower than the ground level, and , A diode for controlling the collector voltage of the first transistor to be higher than the ground level when the first transistor is in a non-conducting state, and non-conducting when the collector voltage of the first transistor is lower than the ground level, and a collector of the first transistor And a second transistor that conducts when the voltage is equal to or higher than the ground level and sets its own collector voltage to the ground level.

The operation of this configuration is as follows.

When the power supply is turned off, the output voltage of the positive voltage power supply circuit is attenuated toward the ground level, while the output voltage of the negative voltage power supply circuit is increased toward the ground level.
That is, the present invention utilizes the converging action of both the positive and negative output voltages to the ground level.

That is, when the power is off, the collector voltage of the first transistor of the switching circuit rapidly rises to a certain level of the positive voltage, and then attenuates in accordance with the attenuation of the output voltage of the positive voltage power circuit. Further, the collector voltage of the second transistor of the switching circuit is attenuated according to the attenuation of the output voltage of the positive voltage power supply circuit.

When the collector voltage of the first transistor becomes equal to or higher than the ground level, the second transistor becomes conductive and the collector voltage instantly falls to the ground level. Further, when the collector voltage of the first transistor becomes lower than the ground level, the second transistor becomes non-conductive, the collector voltage suddenly rises in a moment, and then the second transistor is attenuated according to the attenuation of the output voltage of the positive voltage power supply circuit.

This operation similarly occurs regardless of whether the power switch of the electronic device is off or the external power switch is off. That is, if the collector voltage of the second transistor described above is used as a control signal to be supplied to the controlled circuit of the electronic device, the power-off can be detected quickly and accurately.

(Embodiment) Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a circuit diagram of a power-off detection circuit according to an embodiment of the present invention.

The power-off detection circuit 1 includes a power-supply voltage attenuation detection circuit 2
And an inverting amplifier circuit 3 and a negative voltage power supply circuit 4.

Reference numeral 5 is a positive voltage power supply circuit, 6 is an external power supply, and 7 is a controlled circuit in an electronic device (not shown).

The power supply voltage attenuation detection circuit 2 includes a transistor Q1 as a switching element, a diode D1, and resistors R1 and R1.
2 and. The collector of the transistor Q1 is connected to the output terminal of the positive voltage power supply circuit 5 via the resistor R1, the base is grounded, and the emitter is the resistor R2.
Is connected to the output terminal of the negative voltage power supply circuit 4 via. The anode of the diode D1 is grounded, and the cathode is connected to the collector of the transistor Q1.

The inverting amplifier circuit 3 is composed of a transistor Q2 as a switching element and resistors R3 and R4. The base of the transistor Q2 is connected to the collector of the transistor Q1 via the resistor R3, the collector is connected to the output terminal of the positive voltage power supply circuit 5 via the resistor R4, and the emitter is grounded.

The collector of the transistor Q2 in the inverting amplifier circuit 3 is connected to the input terminal of the controlled circuit 7.

In the case of this embodiment, the power supply voltage attenuation detection circuit 2 having the transistor Q1 and the inverting amplifier circuit 3 having the transistor Q2 constitute the switching circuit 8 in the configuration of the invention. That is, the switching circuit 8 is configured such that the output voltage of the positive voltage power supply circuit 5 decays to a predetermined level,
Driven on the basis of a predetermined amount or more of attenuation of the output voltage,
It outputs a control signal.

When the time constant of the attenuation characteristic of the positive voltage power supply circuit 5 is τ ₁ and the time constant of the negative voltage attenuation characteristic of the negative voltage power supply circuit 4 is τ ₂ ,
τ ₁ >> τ ₂ .

Next, the operation of this embodiment will be described based on the time chart of FIG.

2A shows the output voltage of the positive voltage power supply circuit 5, and FIG.
Represents the output voltage of the negative voltage power supply circuit 4, (C) represents the collector voltage of the transistor Q1, and (D) represents the collector voltage of the transistor Q2.

Before time t ₀ , the power is on. In this power-on state, the output voltages of the positive voltage power supply circuit 5 and the negative voltage power supply circuit 4 maintain constant voltages.

Since the base voltage of the transistor Q1 is 0 [V], which is higher than the emitter voltage which is a negative voltage, the transistor Q1 is conducting. In this state, the collector voltage of the transistor Q1 is a negative voltage (-0.7 [V]).

Regarding the transistor Q2, since the collector voltage of the transistor Q1 is a negative voltage and the emitter voltage of the transistor Q2 is 0 [V], the transistor Q2 is in the off state.

Therefore, to the controlled circuit 7, the output voltage of the positive voltage power supply circuit 5 is dropped by the resistor R4, that is, the collector voltage of the transistor Q2 is input.

It is assumed that the power is turned off at time t ₀ .

The output voltage of the positive voltage power supply circuit 5 starts to attenuate with a large time constant τ ₁ . The output voltage of the negative voltage power supply circuit 4 starts rising with a small time constant τ ₂ .

At time t _{1 when} the base-emitter voltage of the transistor Q1 becomes lower than the on-voltage of the transistor Q1 due to the rapid increase in the output voltage of the negative voltage power supply circuit 4,
The transistor Q1 turns off.

After the time t ₁ when the transistor Q1 is turned off,
The collector voltage of the transistor Q1 once suddenly rises from a negative voltage to a certain level of the positive voltage, and then decays with a time constant τ _{1 as} the output voltage of the positive voltage power supply circuit 5 decays.

At time _{t 2} when the collector voltage of the transistor Q1 reaches a certain voltage _{V t,} the transistor Q2 is turned on.
In the period from time t _{0 to} t ₂ , the transistor Q2
Is kept off, the collector voltage of the transistor Q2, that is, the input voltage to the controlled circuit 7 decays with a time constant τ ₁ according to the decay state of the positive voltage power supply circuit 5.

In time t _2, the the transistor Q2 is turned on, its collector voltage, i.e., the voltage applied to the input terminal of the control circuit 7, rapidly becomes 0 [V].

The collector voltage of the transistor Q1 sharply rises as described above, and then decays with the time constant τ ₁ of the decay of the output voltage of the positive voltage power supply circuit 5, but this collector voltage becomes equal to or less than the above-mentioned constant voltage V _t. at time _{t 3} the, transistor Q2 is turned off. Therefore, the collector voltage of the transistor Q2, that is, the input voltage to the controlled circuit 7, is switched to the voltage obtained by dropping the output voltage of the positive voltage power supply circuit 5 by the resistor R4.

Time t ₃ after the collector voltage of the transistor Q2 (the input voltage to the control circuit 7), decays with the time constant tau ₁ of attenuation of the output voltage of the positive voltage power supply circuit 5.

It is assumed that the minimum voltage required to control the controlled circuit 7 is V _0, and the time when the collector voltage of the transistor Q2 drops to the voltage V ₀ is t ₄ .

As the control signal for the controlled circuit 7, the collector voltage of the transistor Q2 input to the controlled circuit 7 can be used during the period from time t ₂ to time t ₄ .

That is, it falls at time _{t 2, the} available rise, the low level in the period _t 2 ~t _3, one or more of the signal at a high level in the period _t 3 ~t ₄ at time _{t 3.}

Next, another embodiment will be described with reference to FIG. FIG. 3 is a circuit diagram of the power-off detection circuit.

DC voltage Vcc ₁ positive applied to the power supply terminal of the comparator COM is divided by the resistors R5, R6, a connection point of the voltage dividing resistors R5, R6 is connected to the negative input terminal of the comparator COM. The DC reference voltage Vcc ₂ is applied to the positive input terminal of the comparator COM. The output terminal of the comparator COM is connected to a controlled circuit (not shown).

In the case of this embodiment, the comparator COM and the voltage dividing resistor R
5, R6 and the DC reference voltage Vcc ₂ of the DC power applied to the positive input terminal of the comparator COM (not shown),
The switching circuit 8a referred to in the invention is constructed.

The operation of this embodiment will be described with reference to FIG.

Before time T ₀ , the power is on and the DC voltage Vcc ₁
Is in a steady state. In that state, the input voltage Vcc ₃ applied to the negative input terminal of the comparator COM is
Is lower than the DC reference voltage Vcc ₂ , the comparator C
The output terminal of the OM is at "H" level.

At time T ₀ , when the power is turned off, the DC voltage Vc
c ₁ , the input voltage Vcc ₃ and the output voltage of the comparator COM start to decay with a large time constant τ ₁ . Furthermore, the DC reference voltage Vcc ₂ starts to decay with a small time constant tau ₂ than the time constant tau _2.

At time T ₁ , the input voltage Vcc ₃ is the DC reference voltage Vcc
_When it reaches ₂ , the output voltage of the comparator COM instantly falls to the “L” level, and the output voltage to the controlled circuit disappears. The fall of the output voltage of the comparator COM is used as the control signal of the controlled circuit.

Next, a specific example of the controlled circuit 7 using the power-off detection circuit shown in FIG. 1 or 3 will be described with reference to FIG.

The controlled circuit 7 includes input signal digital processing circuits 9 and 10,
It is composed of a latch circuit 11.

The input digital circuit is the input signal digital processing circuit 9 or 10.
Input to and undergo digital processing. The signal after digital processing is latched by the latch circuit 11 under a certain constant condition and output as a locked output digital signal.

A case where the power is turned on again immediately after the power is turned off will be described.

The power supply voltage of the input signal digital processing circuits 9 and 10 and the latch circuit 11 is attenuated, and any one of the input signal digital processing circuits 9 and 10 and the latch circuit 11 is in the operation stop state or the abnormal operation state first. .

If only the latch circuit 11 stops the operation and the power is turned on again at the stage of releasing the latch, the signal obtained by processing the input digital signal by the input signal digital processing circuits 9 and 10 may have a certain constant condition. And again, it will be latched so there is no problem.

However, if only the input signal digital processing circuit 10 stops operating and the power is turned on again in the random state, the input digital signal will be latched in the random state. Occurs. The conventional power-off detection circuit does not take measures to prevent the occurrence of such an abnormal situation.

However, when the power-off detection circuit of the present invention is used and this power-off detection circuit is used to control the latch circuit 11, when the power is turned off, the latch circuit is forcibly and preferentially
The control signal of the switching circuit 8 (collector voltage of the second transistor Q2) can be used to stop the operation of 11. Therefore, when the power is turned on again, the situation of being latched in the random state as described above does not occur. That is, the signal obtained by processing the input digital signal by the input signal digital processing circuits 9 and 10 is again latched under a certain fixed condition, and no problem occurs.

(Effect of the Invention) As described above, in the present invention, the positive and negative two output voltages converge to 0V regardless of whether the power switch of the electronic device is off or the external power switch is off. At the same time, a ground level control signal is given to the controlled circuit of the electronic device at the initial stage of convergence when the power is off. That is, regardless of whether the power switch of the electronic device is off or the external power switch is off, the power off can be detected quickly and accurately, and the control signal can be output to the controlled circuit of the electronic device. This makes it possible to prevent the controlled circuit of the electronic device from falling into an abnormal state. Moreover, since the power-off detection circuit of the present invention has a simple configuration of two positive and negative voltage power supply circuits and a switching circuit composed of two transistors and diodes, it can be put on the market at low cost. In particular, since the ground level is adopted as the operation reference voltage of the two transistors, it is possible to configure inexpensively without using an expensive reference voltage generator such as a comparator, and there is concern about such a reference voltage generator. It is possible to improve the stability and reliability, such as the variation of parts and the deviation due to defective parts.

[Brief description of drawings]

1 and 2 relate to an embodiment of the present invention. FIG. 1 is a circuit diagram of a power-off detection circuit, FIG. 2 is a time chart,
3 and 4 relate to another embodiment of the present invention.
FIG. 4 is a circuit diagram of a power-off detection circuit, FIG. 4 is a time chart, FIG. 5 is a block diagram of a controlled circuit using the power-off detection circuit, and FIG. 6 is a circuit diagram of a conventional power-off detection circuit. . 1 ... Power supply off detection circuit 2 ... Power supply voltage attenuation detection circuit 3 ... Inversion amplification circuit 8 ... Switching circuit 8a ... Switching circuit Q1 ... Transistor Q2 ... Transistor COM ... Comparator

Claims (1)

[Scope of utility model registration request] 1. A power-off detection circuit for detecting a power-off of an electronic device and outputting a control signal to a controlled circuit (7) of the electronic device, the positive-voltage power supply circuit (5) for supplying a positive voltage. And a negative voltage power supply circuit (4) for supplying negative voltage and a switching circuit (8), the time constant of the negative voltage power supply circuit (4) is set smaller than the time constant of the positive voltage power supply circuit (5). The switching circuit (8) detects the output voltage of both the positive and negative voltage power supply circuits (5, 4) to the ground level when the power is turned off and outputs a control signal. In addition, the switching circuit (8) conducts when the deviation of both output voltages of the positive and negative voltage power supply circuits (5, 4) is more than a predetermined value.
The first transistor (Q which becomes non-conductive in response to a rapid rise in the negative output voltage of the negative voltage power supply circuit (4) due to power-off
1) and the first transistor (Q1) is in a conductive state, the collector voltage of the first transistor (Q1) is lower than the ground level.
When (Q1) is in the non-conducting state, the diode (D1) that controls the collector voltage of the first transistor (Q1) above the ground level and the non-conducting state when the collector voltage of the first transistor (Q1) is less than the ground level Transistor
A second transistor that conducts when the collector voltage of (Q1) is higher than the ground level and sets its own collector voltage to the ground level.
And a transistor (Q2) of 1.