JPH0733462Y2 - Timer circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer circuit, and more particularly, to a second circuit after the first and second input signals are supplied and the first input signal is input.
The timer circuit is started when the input signal is input and the output signal is output after a predetermined time has elapsed.

2. Description of the Related Art A timer circuit has a timer circuit that controls an output signal according to two input signals. In such a circuit, there is a timer circuit in which a timer operates when a second input signal is input while a first input signal is input, and tries to obtain an output signal after a predetermined time has elapsed. .

FIG. 3 shows a circuit diagram of an example of a conventional timer circuit. The terminal 8 receives the first input signal d, the terminal 9 receives the second input signal e, and the output terminal 10 outputs the output signal f. After that, when the terminals 8 and 9 are high level, the first and second
When the terminal 10 is at a high level while the input signal is output, the output signal is output. Fourth
The operation of the circuit will be described with reference to the drawings. First, the first input signal d is input, the terminal 8 is at a high level, and the terminal 9 is at the second level.
At time t _{1 when} the input signal e is low level, the transistor Q ₁ is off and the terminal 8 is high level, so the transistor Q ₈ is on and the capacitor 11 is short-circuited.

On the other hand, the thyristor Q ₉ in the initial state is off, the base voltage of the transistor Q ₁₀ becomes high level by the first input signal d, the transistor Q ₁₀ is also turned off, the collector of the transistor Q ₁₀ and the resistor R ₁₄ The output terminal 7, which is a connection point, remains at the low level in a state where the output signal f is not output.

Next, when the second input signal e is input at time t ₂ and the terminal 9 becomes high level, the transistor Q ₇ is turned on, the transistor Q ₈ is turned off, and the charging of the capacitor 11 is started. When time τ elapses and time T ₃ is reached and the capacitor 11 is charged, the thyristor Q ₉ is turned on, the transistor Q ₁₀ is also turned on, and the current is supplied from the terminal 8 to the transistor Q ₁₀ , so that the transistor Q ₁₀ Collector and resistor R ₁₄
The output signal of the output terminal 10, which is the connection point of, becomes high level. Even if the terminal 9 is set to the low level at time t ₄ and the capacitor 11 is discharged by the transistor Q ₈ , the thyristor Q ₉
Remains on, the output terminal 7 maintains a high level, and when the terminal 8 is set to a low level at time t ₅ , the thyristor Q ₉ is turned off and the output terminal 10 also becomes a low level.

However, in the conventional timer circuit, if the second input signal e is already input before the first input signal d is input as shown in FIG. At time t ₆ , when the first input signal d becomes high level, the second input signal e is already at high level, so that the transistor Q ₇ is turned on and the transistor Q ₈ is turned off. At this point, charging of the capacitor 11 is started. is, over time tau, the thyristor Q ₉ is turned on at time t _7, the transistor Q ₁₀ is turned on, the output terminal 10 becomes a high level.

Therefore, although the timer operates when the second input signal is input after the first input signal is input, and it is necessary to obtain the output signal after a predetermined time τ has elapsed,
There is a problem that the timer operates at the time when the first input signal is input and the circuit malfunctions such that the output signal is output after a predetermined time τ has elapsed.

The present invention has been made in view of the above points, and an object thereof is to provide a timer circuit that does not malfunction.

Means for Solving the Problems The present invention is provided with a first input signal and a second input signal, when the first input signal is valid, and when the second input signal is valid. In a timer circuit in which an output signal becomes valid after a lapse of a predetermined time from a time point when the second input signal becomes valid, the second input signal is supplied to a base, and the second input signal is supplied in response to the first input signal. A first transistor that is supplied with a valid / invalid first control signal and invalidates the first control signal when the second input signal is valid; and a collector of the first transistor Is connected to the base, a second transistor is turned on when the first control signal is valid, and is turned off when the first control signal is invalid, and a collector of the first transistor is connected to the gate, With control signal A first thyristor which is turned on when it becomes effective and holds on until the first input signal is invalid, and an anode of the first thyristor is connected to a base,
A third transistor which is turned on when the first input signal is supplied to the emitter and the first thyristor is turned on, and collectors of the second transistor and the third transistor are connected to one end, A capacitor that is released when the first input signal is valid and the second input signal is valid, and is discharged when the second input signal is invalid; Has a gate connected to one end of the second thyristor, which is turned on according to the charging voltage of the capacitor, and holds the on state until the first input signal becomes invalid, and the anode of the second thyristor serves as a base. Connected,
The third transistor has a collector connected to the emitter, and a fourth transistor which is turned on when the second thyristor is turned on and validates the output signal.

Action In the state where the first input signal is supplied and the second input signal is not supplied, the first transistor is turned off, the first input signal is input to the second transistor and the first thyristor, and the second input signal is input. Since the transistor and the first thyristor are turned on, the capacitor is not charged, so the second thyristor remains off, the fourth transistor also turns off and no output signal is output.

Next, when the second input signal is supplied in the above state, the first transistor is turned on, the first input signal is not supplied to the second transistor and the first thyristor, and the second transistor is Since the capacitor is turned off and the capacitor is in a chargeable state, and the first thyristor is kept on by the holding function of the capacitor, current is supplied to the capacitor through the third transistor and charging of the capacitor is started.

When the capacitor is charged and the charging voltage of the capacitor reaches a predetermined value, the second thyristor is turned on, and accordingly, the fourth transistor is turned on and the output signal is output.

As described above, the output signal can be output after a predetermined time has elapsed since the first input signal was input.

In the case where an input state in which the first input signal is input after the second input signal is input in a different order occurs, the first transistor is in a state where the second input signal is input. Then, the second transistor is turned on, and the second transistor is turned off. Therefore, even if the first input signal is input, the current supplied from the third transistor flows to the second transistor and the capacitor is not charged. Therefore, the second thyristor does not turn on, and therefore the fourth transistor also remains off and no output signal is output.

In this way, when the first and second input signals are input in different orders, the output signals do not have to be output, and the malfunction of the device in the next stage can be prevented.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of the present invention. In the figure, 1 is a switch circuit, 2 is a capacitor, 3 is a current supply circuit, 4
Indicates an output circuit.

The switch circuit 1 includes npn transistors Q ₁ and Q ₂ and resistors R _{1 to} R ₄
Consists of. The connection base of the npn transistor Q ₁ is connected to an input terminal 6 of the second input signal through the resistor R ₁ is supplied, the collector of the npn transistor Q ₁ is the first input signal through a resistor R ₂ Is connected to the input terminal 5, the emitter is grounded, the capacitor 2 is connected between the emitter and collector of the npn transistor Q ₂ , and the base is grounded via the resistor R ₄ and the resistor R ₃ is connected. Through np
It is connected to the connection point between the collector of the n-transistor Q ₁ and the resistor R ₂ .

The current supply circuit 3 includes a pnp transistor Q ₃ , a thyristor Q ₅ ,
It consists of resistors R _{5 to} R ₈ . The gate of the thyristor R ₅ is connected to the connection point between the resistance R ₂ of the switch circuit 1 and the collector of the npn transistor Q ₁ via the resistance R _5, and is also grounded via the resistance R ₆ , and the anode is connected to the resistance R ₇ . pn through a resistor R ₈ together with the first input signal is connected to the terminal 5 supplied via
It is connected to the base of p-transistor Q ₃ and its cathode is grounded. The emitter of the transistor Q ₃ is connected to the terminal 5, and the collector is connected to the capacitor 2 via the resistor R ₉ .

Further, the output circuit 4 is a thyristor Q ₆ , a pnp transistor.
Q _4, made of the resistance R ₉ to R _14, is connected to the gate of the thyristor Q ₆ connecting point between the capacitor 2 and the resistor R ₉ is through a resistor R _10, the anode of the thyristor Q ₆ through the resistor R ₁₁ It is connected to the collector of the pnp transistor Q ₃ of the current supply circuit 3. The emitter of the pnp transistor Q ₄ is p of the current supply circuit 3.
It is connected to the collector of the np transistor Q ₃ , the collector is grounded via a resistor R ₁₄ , the base is connected to the anode of the thyristor Q ₆ via a resistor R ₁₂ , and the collector of the current supply circuit 3 is connected via a resistor R ₁₃ . Connected to the collector of pnp transistor Q ₃ . Further, the terminal 7 is extended from the connection point between the pnp transistor Q ₄ and the resistor R _14, and the output signal is taken out from the terminal 7.

Next, the operation of the circuit will be described. First, the operation in a normal state in which the second input signal is input (the terminal 6 is in the high level state) from the state in which the first input signal is input (the terminal 5 is in the high level state) is shown in FIG. It will be described together with (A). When the terminals 5 and 6 are both at the low level, the transistors Q ₂ and Q ₃ are both turned off, so that no current is supplied to the output stage. Therefore, the output terminal 7 is also at the low level (the output signal C
Is not output).

Then at time t ₈ only terminal 5 is high level, i.e. if only the first input signal a is supplied, because the terminal 6 is at a low level, the transistor Q ₁ is turned off, the transistor Q ₂ is base It goes on because it goes high. Further, since the gate of the dyristor Q ₅ becomes high level, the base of the transistor Q ₃ becomes low level and Q ₃ is turned on. Therefore, current is supplied to the thyristor Q ₆ and the transistor Q ₄ through the emitter and collector of the transistor Q ₃ . However, at this time, since the transistor Q ₂ is on, the current flows only in the transistor Q ₂ and the capacitor 2 is not charged. Therefore, the gate of the thyristor Q ₆ becomes the low level, therefore, the base of the transistor Q ₄ are at the high level, the transistor Q ₄ are terminals 7 off becomes the low level.

Next, assuming that the terminal 6 goes high at time t ₉ from this state, first, the transistor Q ₁ is turned on.
The base of transistor Q ₂ goes low and turns off. Therefore, when the capacitor 2 is charged and the terminal voltage of the capacitor 2 reaches a level that turns on the thyristor Q ₆ at time t ₁₀ , the thyristor Q ₆ turns on. Therefore, the base of the transistor Q ₄ becomes low level and Q ₄ is turned on, so that the collector current of Q ₃ flows to the resistor R ₁₄ via the emitter and collector of Q ₄ and the voltage of the terminal 7 becomes high level. . That is, the output voltage of the terminal 7 is the second voltage of the terminal 6.
Input signal b is input at time t ₉ and becomes high level, and is output after the time τ = t ₁₀ −t _{9 has} elapsed until time t ₁₀ at which capacitor 2 is charged and thyristor Q ₆ turns on. Will be).

Next, an abnormal input state in which the first input signal is input while the second input signal is input will be described with reference to FIG. At this time, since the terminal 5 is at the low level and the terminal 6 is at the high level, the transistor Q ₁ is turned on, but since the terminal 5 is at the low level, the transistors Q ₂ , Q ₃ , and Q ₄ are turned on.
Since no current is supplied to the terminal 7, the terminal 7 becomes low level.

From this state, when the terminal 5 is set to the high level at time t ₁₁ , the transistor Q ₁ is on, the transistor Q ₂ is off, the gate of the thyristor Q ₅ is also low level, and the thyristor Q ₅ is off, the base of the transistor Q ₃ is at the high level, the transistor Q ₃ is turned off. Therefore, even if the transistor Q ₂ is off, no current is supplied to the capacitor 2 and no current is supplied to the thyristor Q ₆ and the transistor Q ₄ , so that the terminal 7 is connected to the terminal 7 in FIG. 2 (B). As shown by C in FIG.

Further, in this state, when the terminal 6 is set to the low level at the time t ₁₂ , the transistor Q ₁ is turned off, so that the transistor Q ₂ is turned on by the high level input signal a and the capacitor 2 is short-circuited, and at the same time, the thyristor Q ₅ turns off and transistor Q ₃ turns on. But at this time,
Since both ends of the capacitor 2 are short-circuited by the transistor Q ₂ , the capacitor 2 is not charged by the collector current of the transistor Q ₃ . Therefore, as indicated by C in FIG. 2 (B), the terminal 7 remains at the low level during the times t _{12 to} t ₁₃ .

Further, as shown in FIG. 2B, from this state, time t ₁₃
When the terminal 6 is brought to a high level, the transistor Q ₁ is turned on, and thus the transistor Q ₂ is turned off to release the short circuit of the capacitor 2. Since the gate of this time the thyristor Q ₅ also becomes a low level which is not blocked current supply to the thyristor Q _5, the thyristor Q ₅ holds the ON state. Therefore, the transistor Q ₃ remains on and the capacitor 2 is charged by the collector current of Q ₃ ,
After the time τ has passed, the voltage across the capacitor 2 becomes thyristor.
At time t ₁₄ when the predetermined value of turning on Q ₆ is reached, the gate of thyristor Q ₆ becomes high level, and thyristor Q ₆ turns on. Therefore, the transistor Q ₄ is turned on and the terminal 7 becomes high level. As shown by C in FIG. 2 (B), the timer operation starts when the terminal 5 goes from the low level to the high level, and the predetermined time τ = t ₁₄ −t ₁₃ (=
t ₁₀ -t ₉₎ an output terminal 7 after a lapse of a high level.

That is, when the terminal 6 is at a high level (a state in which the second input signal is input), the terminal 5 is at a high level (in a state in which the first input signal is input), the timer operates when the input signal is abnormal. There is no such thing.

Therefore, the timer operates only when the second input signal is input in the state where the first input signal is always input, that is, when the input signals are input in the normal order, and the output signal is output after a predetermined time has elapsed. To be done.

Effect of the Invention As described above, according to the present invention, the timer does not operate even if the first input signal is input from the state where the second input signal is input, and the output signal is not output. The timer operates only when the second input signal is input from the state where the input signal is input, and the output signal is output after the elapse of a predetermined time. Therefore, even if the input order of the input signals is incorrect, the output signals are output. Is not output, and it is possible to always operate in a normal state.

[Brief description of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of one embodiment of the present invention, FIG. 3 is a circuit diagram of an example of the conventional art, and FIGS. FIG. 8 is a diagram for explaining an operation of a conventional example. 1 ... Switch circuit, 2 ... Capacitor, 3 ... Current supply circuit.

Claims (1)

[Scope of utility model registration request] 1. A first input signal and a second input signal are supplied, and the second input is provided when the first input signal is valid and when the second input signal is valid. In a timer circuit in which an output signal becomes valid after a lapse of a predetermined time from the time when the signal becomes valid, the second input signal is supplied to a base and becomes valid / invalid according to the first input signal. A first transistor supplied with a collector of the first control signal and disabling the first control signal when the second input signal is valid; and a collector of the first transistor connected to the base , A second transistor which is turned on when the first control signal is valid and is turned off when the first control signal is invalid, and a collector of the first transistor is connected to a gate so that the first control signal is valid. When it turns on Ri, a first thyristor of the first input signal is held on until becomes invalid, the anode of the first thyristor is connected to the base,
A third transistor which is turned on when the first input signal is supplied to the emitter and the first thyristor is turned on, and collectors of the second transistor and the third transistor are connected to one end, A capacitor that is released when the first input signal is valid and the second input signal is valid and that is discharged when the second input signal is invalid; A gate is connected to one end, the second thyristor is turned on according to the charging voltage of the capacitor, and is kept on until the first input signal becomes invalid, and the anode of the second thyristor is connected to the base. Is
A timer circuit comprising: a fourth transistor connected to the emitter of the third transistor, and turned on when the second thyristor is turned on to enable an output signal.