JPH06103333A - How to display logical simulation results - Google Patents

Abstract

(57) [Abstract] [Purpose] The purpose is to efficiently display the signal waveform of the simulation result in a logic circuit simulation system. In a simulation system for simulating a logic circuit and sequentially generating data and time data of each signal waveform at a plurality of terminals of the logic circuit and storing the data in a database, the data is retrieved from the database and the Whether or not there is a change in each of the signal waveforms of the plurality of terminals is sequentially examined, only the changed signal waveform portion is extracted, and the signal name and time are associated and displayed on the display screen in chronological order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for efficiently displaying a signal waveform of a simulation result in a logic circuit simulation system.

In the analysis of the result of the logic simulation, the changed portion of the signal waveform is often important information. On the other hand, in complex large-scale logic circuits, the number of signal terminals increases,
Moreover, the period of the simulation operation becomes long. For this reason, the data amount of the signal waveform of the simulation result becomes large and it becomes difficult to verify it on the display screen. The present invention facilitates verification by displaying the simulation result after compressing the information.

[0003]

2. Description of the Related Art In designing a logic circuit, a verification method by simulation is widely used in order to check a design result quickly and surely. The result of the simulation is output as a signal waveform of each terminal of the logic circuit that is associated in time.

FIG. 3 is a schematic diagram of a conventional simulation system. In the figure, reference numeral 1 denotes a logic design data storage unit, which stores design data such as logic functions of respective elements of a simulation target logic circuit and connection information of signal lines.

A simulation processing unit 2 executes a simulation operation of a logic circuit based on test pattern input data and time data, and generates a signal waveform of each terminal in order of time as a simulation result.

Reference numeral 3 is a simulation result database in which data of simulation results is stored.
A display processing unit 4 edits the simulation result data extracted from the simulation result database 3 on the display screen in the waveform diagram format.

Reference numeral 5 denotes a display, on which the simulation result data is displayed on the screen as image information in a waveform diagram format. In the illustrated example, the signal waveforms of the terminals bus1, in1, in2, ... Of the logic circuit shown in the logic design data storage unit 1 are displayed in parallel on the screen of the display 5 in association with time. Has been done. The designer verifies whether or not there is an error in the logic circuit by checking the validity of the waveform between the fixed signals or the signals separated by a fixed time from the waveform diagram displayed in this way. .

[0008]

Generally, when verifying a simulation result, it is often the case that a signal change of a signal to be verified is focused on and checked. However, in the conventional simulation result display method,
Since the signal waveform is displayed as one signal waveform from the simulation start time to the simulation end time, signals that are not necessary at the verification time, for example, signals that have not changed at that time are also displayed on the screen. On the other hand, in a large-scale logic circuit, since the number of signal terminals is large, it may not be possible to simultaneously display all signals on the screen. In such a case, it is necessary to frequently perform screen movement operations such as scrolling,
There was a problem that the verification work efficiency was reduced.

It is an object of the present invention to select only valid signals for verifying simulation results and perform efficient screen display.

[0010]

According to the present invention, only data of a changing signal waveform portion is extracted from a database in which signal waveform data of a simulation result is stored, and the data is arranged and displayed in chronological order together with a signal name. It is something that is done.

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, 3 is a simulation result database, in which the signal waveforms of the terminals of the simulation result are stored in association with each other so that they can be referred to by time.

A display processing unit 4 edits the data of the simulation result represented in the code format by using the image information such as the signal waveform pattern and the character pattern to create a signal waveform display screen. Perform processing.

Reference numeral 5 denotes a display, which displays the signal waveform of the simulation result. A printer 6 is used to print the screen data displayed on the display 5.

Reference numeral 7 denotes an effective signal waveform extraction unit, which reads the data in the simulation result database 3 in order of time to check whether or not there is a signal change (rising or falling) for each signal waveform. , Only the signal waveform part is extracted. The extracted signal waveform portion is represented by time, signal type, code for identifying rising or falling, and data indicating its timing position (position subdivided from time).

Reference numeral 8 is a valid signal waveform database,
Only the data of the valid signal waveform portion extracted from the simulation result database 3 by the valid signal waveform extraction unit 7 is stored and referred to by the display processing unit 4.

[0016]

The operation of the present invention will be described with reference to FIG. In the simulation result database 3 shown in FIG. 1, the time (..., t _i-1 , t
_i , t _{i + 1} , t _{i + 2} , ...), and signals (b) of a plurality of terminals in the logic circuit to be simulated are classified.
us1, in1, in2, CLK, out1, out
2, bus 2, in 3, in 4, in 5) waveform data is stored. In this case, it is assumed that there is no space for simultaneously displaying the waveforms of all signals on the screen of the display 5 (for example, as in the conventional example of FIG. 3, the width for displaying the waveforms of seven types of signals in the vertical direction of the screen). Only provided).

Here, the effective signal waveform extraction unit 7 extracts only the data of the change point from each signal waveform data in the simulation result database 3. As a result, for example, the signal in1 is not extracted between the times t _{i and} t _{i + 1 and the} signal in1 is not extracted.
2 is not extracted at times t _i−1 −t _i and t _{i + 1} −t _{i + 2} ,
The signal out2 is not extracted in the period from time t _i-1 to t _{i + 2} . In this way, the data of the signal waveform that does not change is omitted, and the data amount is compressed.

The extracted signal waveform data of the changing point is stored in the effective signal waveform database 8 and then taken out by the display processing unit 4, and the waveform according to whether the signal waveform of the changing point is a rising waveform or a falling waveform. The pattern is selected,
A signal name is added as shown in the display 5, and the signal waveform to be displayed according to time is edited so as to be packed upward, and a display screen is created.

As a result, even if the display space of the display 5 is small, the number of signals that can be displayed at the same time is increased, and the unchanged redundant signal waveform portion is removed.
The number of screen moving operations is small, and it is easy to check whether or not the verification target signal has changed at a predetermined time. For example, the range of the signal waveform displayed on the display 5 of FIG. 1 cannot be covered by the screen of the display 5 in the conventional example of FIG.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 is a block diagram of an effective signal waveform extraction unit 7 in FIG.
It is a processing flow of the embodiment of. Each step of the flow of FIG. 2 will be sequentially described below with reference to FIG.

(1) Simulation result database 3
Since the signal waveform data is extracted in the order of time from, the simulation start time is initialized. (2) The signal waveform data at the set time is taken out from the simulation result database 3.

(3) One signal is selected, and the waveform is checked for changes. (4) If there is a change in the signal waveform, execute the following step (5), and if there is no change, execute the step (6).

(5) Extract the changed signal waveform portion,
It is stored in the effective signal waveform database 8. (6) If there are remaining signals, return to step (3) and select the next signal. If there are no remaining signals, execute step (7).

(7) The set value of time is updated by +1 and step (8) is executed. (8) If the updated time is equal to the end time of the simulation, the process ends. If it does not reach the end time, the process returns to step (2), and the subsequent steps are repeated.

By performing the above processing, it is checked whether or not there is a change in the signals of all terminals at each time from the start time to the end time in the simulation result database 3, and only the waveform portion of the change is checked. Figure 1
Can be extracted and stored in the effective signal waveform database 8.

The display processing unit 4 in FIG. 1 creates a display screen based on the data in the effective signal waveform database 8. On the screen of the display 5, as in the example shown in the figure, the display area of the signal waveform is divided into strips at successive times, and each strip-shaped area shows the signal of each signal that has changed at the corresponding time. A set of waveform portions (rising waveform and falling waveform) and signal names are arranged in order from the top. Therefore, different types of signals may be mixed in the row direction. The display processing unit 4 automatically executes the editing process necessary for creating such a screen based on the data of the effective signal waveform database 8.

[0027]

According to the present invention, since only the changed portions in the signal waveform of the simulation result are collectively displayed, the number of signals which can be simultaneously displayed on one screen is increased as compared with the conventional one, and the difference between different signals is increased. In addition to facilitating the related check, since the unnecessary part of the signal that has not changed is removed from the screen, the signal visibility is improved and the efficiency of the verification work of the simulation result is significantly improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a processing flow of an effective signal waveform extraction unit according to the embodiment of the present invention.

FIG. 3 is a schematic diagram of a conventional simulation system.

[Explanation of symbols]

 3 Simulation Result Database 4 Display Processing Section 5 Display 6 Printer 7 Effective Signal Waveform Extraction Section 8 Effective Signal Waveform Database

Claims (1)

[Claims] 1. A simulation system for simulating a logic circuit, sequentially generating data and time data of each signal waveform at a plurality of terminals of the logic circuit, and storing the data in a database. It is checked whether or not there is a change in each of the signal waveforms of the multiple terminals of the circuit in order, only the part of the signal waveform that has changed is extracted, and the signal name and time are associated and displayed on the display screen in chronological order. How to display the characteristic logic simulation results.