JPH0586873B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to ultra-high-speed transistors, and particularly to a new type of transistor suitable for high integration and having high load driving capability.

[Background of the invention]

Traditionally, transistors that have been highly integrated on Si substrates have been classified into bipolar transistors and MOS (Metal-Oxide-
The two most representative types were MOSFETs (Semiconductor) type field effect transistors (MOSFETs).
While a bipolar transistor is a vertical device that uses the physical phenomena of diffusion and drift of minority carriers, a field effect transistor is a lateral device that uses majority carriers to be driven by an electric field.

In recent years, due to the limitations of the physical constants of Si, it has been possible to
Ultrahigh-speed devices using compound semiconductors centered on gallium-arsenide (GaAs) are being developed.

Among them, transistors using heterojunctions include heterobipolar transistors (e.g., JP-A-49-43583) and selectively doped heterojunction field-effect transistors (e.g., JP-A-56-94779).
can be given. From the point of view of the operating principle, the latter transistor is almost the same as a MOS FET. By the way, in transistors using such compounds, the essential part of transistor operation is the same as in devices using Si, so bipolar transistors and field effect transistors (hereinafter referred to as FETs) each have their own inherent drawbacks. remains unresolved.

That is, in the case of a hetero bipolar transistor, there is a drawback that the degree of integration cannot be increased compared to a FET due to securing an isolation region.
Further, in the case of a bipolar transistor, there is a lower limit to how thin the base layer can be made due to restrictions on the operating principle.

On the other hand, field effect transistors are suitable for high integration, but a common drawback is that they cannot draw a large amount of current.

[Purpose of the invention]

An object of the present invention is to provide an ultrahigh-speed transistor that is suitable for high integration and is based on a new principle in which a two-dimensional carrier flows in a direction perpendicular to the plane on which the carrier is present.

[Summary of the invention]

Figure 1 shows a conventional selectively doped heterojunction type.
The energy band structure is shown to explain the operating principle of FET. Similarly, the cross-sectional structure of the FET is
As shown in the figure. On a semi-insulating GaAs substrate 10, a GaAs layer 11 (generally
In MBE, a weak p ^- type with an impurity concentration of 10 ¹⁵ cm ^-3 or less is grown. Next, add Si to 1×10 ¹⁸
Al _x Ga _1-X As (x ~ 0.3) layer 12 containing about cm ^-3
Grow about Å. Thereafter, source/drain electrodes 21, 22 and gate electrode 13 are formed.

FIG. 1 shows an energy band diagram directly under the gate electrode. 1 doped Si atom
4, the depletion layer due to Schottky junction is 16
Shown below. Since AlGaAs and GaAs have the same type of crystal lattice and very similar lattice constants, it is thought that the number of interface states at the heterojunction interface is very small. _GaAs has a larger electron affinity than _Al
A dimensional carrier 15 is formed.

Conventional FETs are characterized by flowing this two-dimensional carrier along the heterojunction interface, which makes it impossible to obtain a large current.

In the present invention, the two-dimensional carrier 15 present at the heterojunction interface shown in FIG. By introducing a new transistor principle that performs transistor operation by modulating the magnitude of current by controlling generation and annihilation, we can overcome the advantages of conventional selectively doped heterojunction FTEs and heterobipolar transistors. It is intended to overcome the disadvantages of the

The operating principle of the new type of transistor of the present invention will be explained below using a device cross-sectional view [Figure 3] and energy band of the transistor of the present invention made using a heterojunction of p-type _GaAs and _n -type Al This will be explained using the figure [Fig. 4]. After that, the operating characteristics when an external potential is applied will be explained.

As shown in Figure 3, a predetermined semi-insulating AlyGa _1-y
On the n ⁺ layer 18 buried in the As semiconductor substrate 90, there is a heterojunction with the p-type GaAs layer 17 of about 200 Å to 1000 Å, and the n-type Al _x of about 300 Å to 1000 Å is formed.
A Ga _1-x As (about x ~ 0.3) layer 12 is created. Due to the difference in electron affinity, free electrons in the Al _x Ga _1-x As layer accumulate at the heterojunction interface on the p-type GaAs layer 17 side, forming a two-dimensional electron gas layer 15.
FIG. 4 shows a band structure diagram showing this state. The same parts as in FIG. 3 are indicated by the same symbols.

The transistor of the present invention has a source electrode 29 that makes ohmic contact with the two-dimensional carrier 15, and a gate control electrode 30 that generates and annihilates the carrier 15.
Located directly below.

The third semiconductor layer 18 forming a heterojunction with the second semiconductor layer 17 [in this case, the third semiconductor layer 18 has a thickness of about 500 Å.
The basic structure is a drain electrode 31 that is in ohmic contact with a two-dimensional carrier 15' accumulated at the interface with the n ⁺ AlGaAs layer.

The essential point of transistor operation is to take out the two-dimensional carrier 15 as a current to the vertically downward two-dimensional carrier layer 15' and apply an external potential to the gate electrode 30 to change the two-dimensional carrier concentration. This allows the transistor to operate by controlling the vertical current.

FIG. 4 shows an energy band diagram directly under the gate electrode when no external potential is applied. E _F
indicates the position of Fermi energy, and φ _Bo represents the short key potential between the gate electrode metal 30 and the Al _x Ga _1-x As layer 12. Due to the phenomenon of Fermi level pinning, the value of φ _Bo is as follows. It is thought that there is almost no change regardless of the value of the gate voltage. Ionized donor ions in the depletion layer under the gate electrode are indicated by 16.

The transistor operation when an external potential is applied will be explained in more detail below using energy band diagrams shown in FIGS. 5A, 5B, and 6C. Figure 5 shows the energy band diagram when the source electrode is grounded, the source and drain are at the same potential, and a positive gate voltage V _G is applied to the source electrode.
Shown in Figure a. In Figure 5a, a certain positive gate voltage
A two-dimensional carrier 15 is formed with a concentration corresponding to the value of V _G . Since the source and drain are at the same potential, no source-drain current flows in this case. V _G
= 0 and the two-dimensional carrier 15 is substantially present, the depletion type (D type), and the case where the two-dimensional carrier 15 is induced for the first time after applying a certain positive gate potential is the enhancement type (D type). It is called an E-type because it is the same as a normal FET. Also, E type, D
The threshold potential of the type is determined by the impurity concentration and film thickness of each semiconductor layer of (I), (), and (). Hereinafter, the layer in parentheses will be referred to as the pass layer.

Next, in addition to the state shown in Fig. 5a, a case where a positive drain voltage V _D is applied to the source potential [Fig. 5b] and a case where a negative drain voltage V _D is applied [Fig.
Figure c] shows the energy band diagram. Free electron carriers in the two-dimensional carrier 15 and the semiconductor () can be taken out as a current between the source and drain due to the effects of diffusion, drift, and tunneling. Which of the above three effects is dominant is mainly determined by the acceptor concentration and film thickness of the semiconductor layer ().

Next, FIG. 6 shows an energy band diagram when a negative gate potential V _G is applied to eliminate the two-dimensional carrier. In this case, even if a drain voltage V _D is applied, no current substantially flows (except for the breakdown current when a large V _D is applied).

The fact that this transistor can handle a large amount of current will be briefly explained in comparison with a selectively doped heterojunction FET. If the gate length is Lg and the thickness of the two-dimensional carrier is a, the current can be increased by a factor of Lg/a. If a is estimated to be 100 Å, Lg is about 1 μm, so a current of about 100 Å can be obtained.

On the other hand, a major advantage compared to a bipolar transistor is that if the p-type semiconductor layer 17 is thinner and larger than the thickness a of the two-dimensional carrier, it will operate as a transistor, so there is no significant restriction on the thickness of the base layer. will be relaxed.

The symbol of this transistor is shown in FIG. 7a. 3
0 is the gate electrode terminal, 29 is the source electrode terminal, 3
1 is a drain electrode terminal. The transistor operation explained in FIGS. 5 and 6 is for the case where the source electrode is grounded as shown in FIG. 7b. Of course, it is also possible to connect the drain electrodes as shown in FIG. 7c.

In the above description of the operation of the transistor of the present invention, the two-dimensional carriers accumulated at the heterojunction interface were electrons. The transistor of the present invention can also be fabricated using two-dimensional holes by selecting a material for the heterojunction.

Figure 8 shows a p-type GaAs _1-x P _x layer 72 and an n-type GaAs layer 72.
The energy band diagram shows a three-layer structure consisting of a layer 77 and a p-type AlyGa _1-y As layer 78, in which the gate electrode 30 is arranged in a Schottky junction on GaAs _1-x P _x . The difference is that the source/drain electrodes are made of a p-type semiconductor rather than an n-type semiconductor, but the transistor of the present invention can be made using two-dimensional holes.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail through examples of the present invention.

Example 1 Figures 9a to 9d show the main steps when a two-dimensional electron gas is used.

Semi-insulating Al _y Ga _1-y As on semi-insulating GaAs substrate 10
(x ~ 0.3) layer 90 is grown to 2000 Å and then 5000 thick
A SiO _z film 40 of 1.5 Å is deposited by CVD and selectively optically etched to form a drain region. Using this SiO _z film as a mask, a Si ion beam 45 was implanted at an acceleration voltage of 100 kV and a dose of 2×10 ¹³ cm ² to form an impurity region 18 . In this case, the accelerating voltage starts from 20kV.
Ion implantation is performed at a voltage of 150 kV and a dose of 0.5×10 ¹³ cm ² to 5×10 ¹³ cm ² .
A 5000Å SiO _z film was deposited on the entire surface using the CVD method and heated at 820°C.
The implanted Si atoms were activated by annealing for 30 minutes [Figure 9a].

Next, after removing the SiO _z film by chemical etching, using the molecular beam epitaxy (MBE) method,
GaAs at a substrate temperature of 680°C in a vacuum of 10 ^-11 torr.
Layer 17 was grown to 400 Å. At that time, Zn atoms were doped as acceptors to obtain an acceptor concentration of 3×10 ¹⁷ cm ⁻³ .

Next, an Al _x Ga _1-x As (X~0.3) layer 12 was grown to a thickness of 500 Å. At this time, Si atoms were doped as donors to obtain a donor concentration of 1×10 ¹⁸ cm ⁻³ .

Next, in order to install a drain electrode in the drain region 18, the Al _x Ga _1-x As layer 12 and the p-type GaAs layer 17 were selectively etched to expose a part of the drain region 18 layer. Figure 9 b).

Next, 300 Å of SiO _Z 33 was deposited by the CVD method, and the SiO _Z was selectively chemically etched to open windows similar to source/drain electrodes. After that, source/drain metal [AuGe
(1000 Å)-Ni (2000 Å)-Au (1100 Å)] was deposited (FIG. 9c). Thereafter, alloying was carried out at 450°C for 3 minutes. 29 is a source electrode, and 31 is a drain electrode.

Here, the source electrode and the drain region 18 are
It is important not to shoot due to AuGe diffusion. In this case, the closest distance L _SD between the source region and the drain region, shown in FIG. 9d, was about 1 μm. Next, the region directly above the drain region 18
After removing _SiO2 , Ti(1000Å)−Pt(2000Å)−Au
(1000 Å) was deposited to form the gate electrode 30. In this case, two-dimensional electron gas exists at the heterojunction interface of the gap 33 between the source electrode 29 and the gate electrode 30, and this two-dimensional electron gas and the source electrode 29 are in ohmic contact. .

In the case of this embodiment, by using a semi-insulating GaAs substrate, restrictions on the source-drain distance _LSD are weakened, and the concentration of the p-type region 17 is also reduced.
It can be as low as 10 ₁₅ cm ^-3 .

In this embodiment, since the p-type region 17 is as thin as 400 Å, a high speed of about four times that of a bipolar transistor with a base layer thickness of 1000 Å and a similar dimension was obtained.

Example 2 Zn was added in place of the semi-insulating Al _y Ga _1-y As layer 90.
p-type Al _y Ga _1-y As layer 5 with a concentration of ×10 ¹⁷ cm ^-3
FIG. 10 shows a case where the transistor of the present invention is implemented on a semiconductor device.

To form the n ⁺ -type region 18 on the semiconductor substrate 50, ion implantation may be used as in Example 1, but in order to improve the crystallinity of the capiraxial growth on the drain region 18, it is preferable to use Si atoms. Thermal diffusion may also be used.

This is mainly because if 18 layers are formed by ion implantation, the crystallinity after annealing may deteriorate.

In addition to Zn, Be and the like can also be used as the p-type dopant.

As the n-type dopant for the buried layer 18, it is desirable to use an n-type dopant with a diffusion coefficient as small as possible. When using the p-type substrate 50, it is important to prevent the depletion layers extending from the source region and the drain region 18 from overlapping in order to ensure a large margin for transistor operation.

Embodiment 3 FIG. 11 shows an example of the main steps when an E-type transistor and a D-type transistor are separately manufactured on the same substrate. Drain regions 18, 18' and p-type GaAs layer 17 with the same thickness and impurity concentration as in Example 1,
An n-type Al _x Ga _1-X As layer 12 is formed in advance, and approximately
A window is selectively opened in the 2 μm photoresist 49, and Be ions 46 are accelerated at a voltage of 30 kV and at a dose of 1.
Ion implantation was performed under the conditions of ×10 ¹² cm ^-2 (Figure 11a). After removing the photoresist, a 3000 Å SiO ₂ film was deposited by plasma CVD and annealed at 800°C for 30 minutes to activate the Be atoms. After this,
Through the same process as in Example 1, the drain electrode 3
1, 31', source electrode 29, gate electrode 30,
30' was formed (Fig. 11b). The E-type transistor has a gate electrode of 30', and the D-type transistor has a gate electrode of 30. Adjustment of the threshold potential can also be achieved by adjusting the impurity concentration of the drain regions 18, 18'. That is, in the example of ion implantation, the threshold value also changes by changing the implantation energy and dose.

Example 4 An example in which an E-type transistor and a D-type transistor are separately manufactured on the same substrate is shown in FIGS _{. A 1-y} As layer 90 (y~0.3) is formed to form drain regions 18, 18'. Then Ge
500 with acceptor concentration of 5×10 ¹⁷ cm ^-3
A GaAs layer 17' having a thickness of 1.5 Å was formed by the MBE method. Next, Si
Al _x Ga _1-x As containing 7 x 10 ¹⁷ cm ^-3 concentration (X ~ 0.3)
Layer 12' was grown to a thickness of 400 Å, and a GaAs layer 34 containing 10 ¹⁸ cm ^-3 of Si was grown to a thickness of 200 Å (FIG. 12a).

Next, using a mixed gas of CCl ₂ F ₂ and He, the GaAs layer 34 of the gate electrode portion of the E-type transistor is removed by selective etching, and then the gate electrode 34 is removed.
0.30' was formed. source 29, drain 3
The process of forming electrodes 1 and 31' is the same as in Example 1 (FIG. 12b).

Embodiment 5 FIGS. 13a, b, and c show an example of a process for producing a self-aligned type embodiment of the present invention on the same substrate as E-type and D-type.

As in Example 1, a semi-insulating Al _y Ga _1-y As (y ~ 0.3) 90 was formed on a semi-insulating GaAs substrate 10.
Using Si ion implantation method, the n ⁺ type semiconductor layer 18,
18'. After annealing, Zn 5×10 ¹⁶ cm ^-
A ^p -type GaAs layer 17'' with an acceptor impurity concentration of
It was grown using the VPE method. That is, (CH ₃ ) ₃ Ga
and AsH ₃ V/ratio 15, substrate temperature 700℃
The crystals were grown. Dimethylzinc (CH ₃ ) ₂ Zn was used as the p-type dopant.

Next, 5×10 ¹⁷ cm ⁻³ of Si was doped.

Al _x Ga _1-X As (x~0.3) layer 12″ by 600 Å,
Using AsH ₃ , (CH ₃ ) ₃ Ga, (CH ₃ ) ₃ Al, OM−
Crystals were grown using the VPE method. _SiH4 gas was used to dope the donor Si. Next, to make a D-type transistor, photoresist 4 with a thickness of about 1.5 μm is applied.
9 was used to perform selective window opening.

In the figure, in the part where the D-type gate electrode is formed,
The photoresist window is open. Using this photoresist as a mask, Si ions 47' are implanted. The driving conditions were an accelerating voltage of 30kV,
The dose was 1×10 ¹² cm ^-2 (Figure 13a).

As the ion species, Te, Se, etc., which are heavier than Si, may be used.

After depositing a CVDSiO ₂ film of 3000 Å and annealing at 750°C for 20 minutes, selectively deposit an n-type Al _x Ga _1-x As layer 12″, p
The type GaAs layer 17'' was chemically etched (13th
Figure b). Next, apply W silicide to 3000Å at 10 ^-6 torr.
The gate regions 30 and 30' were formed by coating the entire surface using a vacuum evaporation apparatus. Next, using this gate electrode as a mask, ²⁹ Si ions 47 were implanted.

Implant conditions are acceleration voltage 50kV, dose 1×
It was 10 ¹³ cm ^-2 .

Next, 3000 Å of SiO ₂ was deposited on the entire surface by CVD method, and annealing was performed at 800° C. for 30 minutes. Next, leaving a _SiO2 layer 33 for separation between the electrodes,
The source electrode 29 and the drain electrodes 31, 31'
It was formed using AuGe (1200 Å)-Ni (150 Å)-Au (1500 Å) [Fig. 13c].

In the present example, the transistor with gate electrode 30 is of type E, and the transistor with gate electrode 30' is of type D.

This embodiment is characterized in that the D-type transistor is manufactured by ion implantation.

Moreover, as shown in FIG. 13b, the reason why ions were implanted using the gate electrode as a mask to form the source electrode is because the two-dimensional electron gas layer at the hero interface under the gate electrodes 30 and 30' This is to make contact with the people.

In addition, in the case of this embodiment in which the E-type transistor is formed first, the n-type Al _x Ga _1-x As layer 12'' is a weak n-type Al _x Ga _1-x As layer that is not intentionally doped with impurities. may also be used.

In the above embodiments, a case was shown in which a heterojunction of Al _x Ga _1-x As/GaAs was used.

However, it goes without saying that the present invention is effective in other heterojunctions that satisfy the conditions for storing two-dimensional electron gas.

Examples of these include Inp−InGaAsP,
Al _y Aa _1-y As−Al _X Ga _1-X As, GaAs−AlGaAsP,
InP−InGaAs, InAs−GaAsSb, Al _X Ga _1-X As−
These include Ge, GaAs-Ge, CdTe-InSb, GaSb-InAs, etc.

Example 6 An example in which two-dimensional holes are used as carriers is shown in FIGS. 14a, b, and c. A semi-insulating Al _y Ga _1-y As layer 90 of 500 Å is formed on the semi-insulating GaAs substrate 10 , and a layer of 4000 Å is formed on the semi-insulating GaAs substrate 10 to form the drain region 78 .
Using SiO ₂ 40 and selectively opening the window, Zn
Drain region 78 was formed using thermal diffusion. For thermal diffusion of Zn, diffusion lines As and ZN were placed in an ampoule and the ampoule was sealed in vacuum. Vacuum degree is 1x
10 ^-6 Torr. Thereafter, diffusion was performed at a diffusion temperature of 650°C and a diffusion time of 30 minutes. Thereafter, the wafer was removed from the ampoule and washed.
Next, a GaAs layer 7 containing Si at a concentration of 5×10 ¹⁷ cm ^-3
7 was grown to 800 Å using the MBE method. next
GaP _x As _1-X layer 72 containing 1 x 10 ¹⁸ cm ^-3 of Zn
Crystals were grown using the ÅMBE method. Next, chemical etching was performed to connect the drain metal to the p-type GaAs layer 78 (FIG. 14a). Next, using Au--Zn (99:1) with a thickness of 1500 Å as the source/drain metal, alloying was performed at 500° C. for 10 minutes to form a source electrode 89 and a drain electrode 91. Then Mo
Gate electrode 30 using (1000Å)-Al(2000Å)
was formed.

SiO ₂ 33 is a spacer layer for separation between electrodes. Two-dimensional holes generated at the heterojunction interface 7
As a heterojunction forming 5,75', _GaP
Ge may be used instead of As _1-X . That is, the main point of the present invention is that two-dimensional holes can be stored at the heterojunction interface,
The transistor of the present invention can be constructed even in heterojunctions other than GaPxAs _1-x /GaAs and Ge/GaAs systems as long as two-dimensional holes can be accumulated.

In Examples 1 to 6 above, isolation between elements was performed by mesa etching. Etching depth is 1500Å~
The thickness is about 2000 Å, so there is no problem with planarization. Of course, isolation between elements can also be achieved using implants such as oxygen atoms.

The present invention can be summarized as follows.

An important point of the present invention is to provide a transistor that can draw a large amount of current by causing two-dimensional electrons or holes accumulated at the heterojunction interface to flow in a direction perpendicular to the heterojunction interface.

〔Effect of the invention〕

The effects of the present invention can be summarized as follows.

(1) In order to extract the two-dimensional carrier generated at the heterojunction interface as a current in the direction perpendicular to the interface,
Compared to conventional selectively doped heterojunction FETs,
Comparing cases of the same degree of demagnetization,
When the thickness of the two-dimensional carrier is a and the gate length Lg, a current approximately Lg/a times larger can be extracted. When Lg = 1 μm, approximately 20 times the current could be obtained.

(2) In principle, the layer through which the two-dimensional carrier passes in the vertical direction can be made as thin as the thickness of the two-dimensional carrier. Performance can be extracted.

(3) Unlike bipolar transistors, there is no need to secure an isolation area;
High integration similar to selectively doped heterojunction FETs is possible.

(4) When an n-type or p-type third semiconductor layer is selectively formed on a semi-insulating third semiconductor substrate, the depletion layers extending from both the source region and the drain region do not overlap. This has the effect of reducing constraints on determining margins in transistor design.

[Brief explanation of the drawing]

1 and 2 are an energy band diagram and a sectional structure diagram of a conventional FET, respectively, FIGS. 3 and 4 are a sectional diagram and an energy band diagram under a gate electrode of a transistor of the present invention, and 6 is an energy band diagram when an external potential is applied, FIG. 7 is a diagram explaining the symbols of the transistor of the present invention, and FIG. 8 is an energy band diagram of the transistor of the present invention when two-dimensional holes are used. 9th, 10th, 11th, 12th,
FIG. 13 is a cross-sectional view of an apparatus showing the manufacturing process of the transistor of the present invention when a two-dimensional electron gas is used, and FIG. 14 is a cross-sectional view of the apparatus when a two-dimensional hole is used. 15,15'...Two-dimensional electron gas, 17,1
7', 17''...p-type GaAs layer, 12, 12', 1
2″...n-type Al _x Ga _1-x As layer, 18,18′...n ⁺
type AlGaAs layer drain region, 29... source electrode, 31, 31'... drain electrode, 30, 3
0'...gate electrode, 16...ionized donor ion, 72...p type GaPxAs _1-X , 77...n type
GaAs, 78... P ⁺ type GaAs layer, 75... Two-dimensional hole gas, 10... Semi-insulating GaAs substrate, 46
...Acceptor ion, 45, 47, 47'...
Donor ion, 90...semi-insulating Al _y Ga _1-y As,
10... Semi-insulating GaAs substrate.

Claims (1)

[Claims] 1. A first semiconductor layer and a second semiconductor layer are arranged to form a heterojunction, and the second semiconductor layer and a third semiconductor layer are arranged to form a heterojunction. In a semiconductor device having a three-layer structure, a first two-dimensional carrier formed near the heterojunction interface between the first semiconductor layer and the second semiconductor layer and insulated from the second two-dimensional carrier described below; The electrically connected electrode and the first two-dimensional carrier are insulated and the first two-dimensional carrier is generated near the heterojunction interface between the second semiconductor layer and the third semiconductor layer. an electrode electrically connected to a second two-dimensional carrier of the same type; and an electrode connected to the first semiconductor layer for controlling the first two-dimensional carrier. Characteristic semiconductor devices. 2. A semiconductor device according to claim 1, wherein the electron affinity of the first and third semiconductor layers is smaller than the electron affinity of the second semiconductor layer. 3. In the semiconductor device according to claim 2, the first semiconductor layer is an n-type semiconductor layer or a semiconductor layer not intentionally doped with impurities (concentration of 10 ¹⁵ cm ^-3 or less), and the second semiconductor layer is a p-type semiconductor layer or is not intentionally doped with impurities (concentration of 10 ¹⁵ cm ^-3 or less), and the third semiconductor layer is an n-type semiconductor layer. 4. The semiconductor device according to claim 1, characterized in that the sum of electron affinity and band gap in the first and third semiconductor layers is greater than the sum of electron affinity and band gap of the second semiconductor. semiconductor device. 5. In the semiconductor device according to claim 4, the first semiconductor layer is p-type or not intentionally doped with impurities, and the second semiconductor layer is n-type or not intentionally doped with impurities. The semiconductor layer of 3 is p
A semiconductor layer characterized by being a type. 6. The semiconductor device according to any one of claims 1 to 4, comprising: an electrode connecting a two-dimensional carrier formed at a hetero interface between the first and second semiconductor layers; and a third semiconductor layer. A current is drawn from the two-dimensional carrier in a direction perpendicular to the heterojunction interface between the two-dimensional carrier and an electrode connected to the first semiconductor layer, and the two-dimensional carrier is controlled through the electrode that connects the two-dimensional carrier to the first semiconductor layer. Characteristic semiconductor devices. 7. A semiconductor device according to any one of claims 1 to 6, characterized in that the third semiconductor layer is selectively formed on a semi-insulating substrate. 8. The semiconductor device according to any one of claims 1 to 6, characterized in that the third semiconductor layer is selectively formed in a semiconductor substrate of the same conductivity type as the second semiconductor layer. semiconductor device.