JPH0586477B2 - - Google Patents
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- Publication number
- JPH0586477B2 JPH0586477B2 JP60189517A JP18951785A JPH0586477B2 JP H0586477 B2 JPH0586477 B2 JP H0586477B2 JP 60189517 A JP60189517 A JP 60189517A JP 18951785 A JP18951785 A JP 18951785A JP H0586477 B2 JPH0586477 B2 JP H0586477B2
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- Prior art keywords
- substrate
- temperature
- sputtering
- electrode
- gas
- Prior art date
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- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体回路や表面処理などのスパツ
タリング成膜において、被膜対象物を加熱・冷却
して温度制御することにより最適な膜を形成する
様にしたスパツタリング装置に関するものであ
る。[Detailed description of the invention] [Industrial application field] The present invention forms an optimal film by heating and cooling an object to be coated and controlling the temperature in sputtering film formation for semiconductor circuits, surface treatment, etc. The present invention relates to a sputtering device having a similar structure.
半導体回路や表面処理など成膜を行うスパツタ
リング装置としては、特公昭53−19319号公報に
記載のマグネトロンスパツタリング装置や特開昭
58−75839号公報に記載のマイクロ波を用いたス
パツタリング装置などがある。
Examples of sputtering equipment for forming films such as semiconductor circuits and surface treatments include the magnetron sputtering equipment described in Japanese Patent Publication No. 53-19319 and the
There is a sputtering device using microwaves described in Japanese Patent No. 58-75839.
1M〜4MbitDRAM等のVLSIでは高密度集積
化や高速化に対応するため配線の多層化が必須の
技術であり、これに伴い上層配線の断線を防止す
るため層間絶縁膜の平坦化技術が重要である。 In VLSI such as 1M to 4Mbit DRAM, multilayer wiring is an essential technology to support higher density integration and faster speeds, and with this, technology to flatten interlayer insulating films is important to prevent disconnections in upper layer wiring. be.
バイアススパツタ法と呼ばれる方法は、基板に
バイアス電位を与えて基板上に堆積した膜のエツ
チングを行うものである。膜の堆積速度が基板表
面形状に無関係に一定であるのに対しスパツタエ
ツチ速度が傾斜部で大きくなることから、デポジ
シヨンとエツチングを併用することにより１工程
で平坦膜が形成でき、さらにプロセスのドライ化
から最も期待の大きい方法である。 A method called bias sputtering is a method in which a bias potential is applied to a substrate to etch a film deposited on the substrate. While the film deposition rate is constant regardless of the substrate surface shape, the sputter etch rate increases on sloped parts. By using both deposition and etching, a flat film can be formed in one step, and the process can be made dryer. This is the method with the highest expectations.
しかし、この方法は基板に堆積した膜をプラズ
マ中のイオンによりスパツタエツチするため、基
板への熱流入があり、Al配線の場合には耐熱温
度の450℃以上で断線が生じたり、MOSデバイス
においては素子寿命の低下が生じたりする恐れが
ある。 However, since this method sputter-etches the film deposited on the substrate using ions in the plasma, heat flows into the substrate, and in the case of Al wiring, disconnection may occur at temperatures exceeding the allowable temperature of 450°C, and in the case of MOS devices, There is a possibility that the element life may be shortened.
このため、従来のスパツタ装置においては基板
の温度コントロールができないため上記のような
問題があつた。 For this reason, in the conventional sputtering apparatus, the temperature of the substrate cannot be controlled, resulting in the above-mentioned problems.
本発明の目的は、上記した従来技術の欠点をな
くし、成膜時の基板への熱流入による素子ダメー
ジをなくすとともに、膜の結晶制御を可能とする
スパツタリング装置を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a sputtering apparatus that eliminates the drawbacks of the prior art described above, eliminates element damage due to heat flow into a substrate during film formation, and enables control of film crystallization.
本発明は、上記目的を達成するため、真空槽内
でターゲツトをスパツタすることによりターゲツ
トと対向する基板電極に載置された基板上に薄膜
を形成するスパツタリング装置において、基板電
極の基板載置面を薄い誘電体層で覆い、かつ、基
板電極を加熱又は冷却する加熱冷却手段と、基板
の温度を検出する温度検出手段と、前記載置面と
基板の裏面との間にガスを導入するガス導入手段
と、基板バイアス電圧を印加する電圧印加手段と
を備え、電圧印加手段で基板にバイアス電圧を印
加しながらスパツタにより基板上に薄膜を形成す
る時に、温度検出手段で測定した基板の温度に基
づいて加熱冷却手段で基板電極を加熱又は冷却
し、同時にガス導入手段で前記載置面と基板の裏
面との間にガスを導入して前記載置面と基板の裏
面との間の熱伝導を良くすることにより基板の温
度を所定の温度に維持することを可能としたもの
である。
To achieve the above object, the present invention provides a sputtering apparatus for forming a thin film on a substrate placed on a substrate electrode facing the target by sputtering a target in a vacuum chamber. a heating and cooling means for heating or cooling the substrate electrode; a temperature detection means for detecting the temperature of the substrate; and a gas for introducing gas between the mounting surface and the back surface of the substrate. and a voltage application means for applying a substrate bias voltage, and when a thin film is formed on the substrate by sputtering while applying a bias voltage to the substrate with the voltage application means, the temperature of the substrate measured by the temperature detection means is Based on the heating or cooling means, the substrate electrode is heated or cooled, and at the same time, gas is introduced between the mounting surface and the back surface of the substrate using the gas introducing means to conduct heat between the mounting surface and the back surface of the substrate. By improving the temperature of the substrate, it is possible to maintain the temperature of the substrate at a predetermined temperature.
本発明の実施例を図に従つて説明する。第１図
は多層配線を用いたMOS（Metal−Oxide−
Semiconductor）型素子構造の概略を示したもの
である。Siプレート１の表面には、不純物をドー
プしたソース・ドレイン領域２が形成されてい
る。これら各電極からは、コンタクトホール３を
通して最下層の配線４が接続されている。多層配
線ではこの上に絶縁層５が形成され、スルーホー
ル６を通して上層の配線７に接続されている。
Embodiments of the present invention will be described with reference to the drawings. Figure 1 shows MOS (Metal-Oxide-
This diagram schematically shows the structure of a semiconductor type device. On the surface of the Si plate 1, source/drain regions 2 doped with impurities are formed. Each of these electrodes is connected to a lowermost layer wiring 4 through a contact hole 3. In the multilayer wiring, an insulating layer 5 is formed on this, and is connected to an upper layer wiring 7 through a through hole 6.
この多層配線構造を形成するうえで、配線間の
絶縁膜５を平坦にすることは配線の断線をなくす
など信頼性の点から重要な技術である。これを実
現するため、いくつかの方法が考えられているが
最も効果があるものとしてバイアススパツタ法が
ある。 In forming this multilayer wiring structure, flattening the insulating film 5 between the wirings is an important technique from the viewpoint of reliability, such as eliminating disconnection of wiring. Several methods have been considered to achieve this, but the most effective one is the bias sputtering method.
第２図は、このバイアススパツタ法の概要を示
したものである。ａ）は膜堆積と平坦化の関係、
ｂ）は平坦化の原理について１例をあげて説明し
たものである。横軸は堆積部の傾斜角θを縦軸は
デポジシヨンおよびエツチング速度を示してい
る。 FIG. 2 shows an outline of this bias sputtering method. a) is the relationship between film deposition and planarization;
b) explains the principle of planarization by giving an example. The horizontal axis shows the inclination angle θ of the deposited portion, and the vertical axis shows the deposition and etching rates.
点線１０はデポジシヨンを、実線１１はエツチ
ングを示す。この結果、デポジシヨン速度とエツ
チング速度が等しくなる傾斜角θ0に対し、θ＞θ0
の傾斜角をもつ基板１上の配線４に対しては、絶
縁物５が傾斜部ではデポジシヨン速度よりエツチ
ング速度が大きいため堆積せず、平坦部のみに堆
積し）））のように進んで平坦膜が形成さ
れる。 The dotted line 10 shows the deposition and the solid line 11 shows the etching. As a result, for the tilt angle θ 0 at which the deposition rate and etching rate are equal, θ>θ 0
For the wiring 4 on the substrate 1 having an inclination angle of A film is formed.
第３図は、上記のバイアススパツタ法を実現す
るようにしたマイクロ波放電スパツタ装置の例で
あり、第４図は上記装置において基板の温度制御
を行うようにした基板固定電極部の一実施例であ
る。 FIG. 3 shows an example of a microwave discharge sputtering device that implements the bias sputtering method described above, and FIG. 4 shows an example of an embodiment of the substrate-fixed electrode part that controls the temperature of the substrate in the above-mentioned device. This is an example.
ターゲツト２０はパツキングプレート２１を介
して陰極２２に、また陰極２２は絶縁物２３を介
して真空槽２４に設置されている。２５は陽極で
ある。この陽陰電極間に電源２６が設置されてい
る。２７はプラズマ発生室であり、外周には導波
管２８が絶縁物２９を介して陰極２２に固定され
ており、前記導波管２８の他端にはマイクロ波発
生源３０が設置されている。前記導波管２８には
同心状に磁気装置３１が設置されている。 The target 20 is placed on a cathode 22 via a packing plate 21, and the cathode 22 is placed on a vacuum chamber 24 via an insulator 23. 25 is an anode. A power source 26 is installed between the positive and negative electrodes. 27 is a plasma generation chamber, on the outer periphery of which a waveguide 28 is fixed to the cathode 22 via an insulator 29, and at the other end of the waveguide 28 a microwave generation source 30 is installed. . A magnetic device 31 is installed concentrically in the waveguide 28 .
また、基板３２は基板ホルダ３３上にチヤツク
３４により押し付けられる。基板ホルダ３３の上
面は数十μm厚の誘電体３５から成り、表面はな
だらかな凸形状をしている。基板ホルダ３３の中
央には微小穴３６が加工されており、ガス３７の
供給パイプ３８につながつている。さらに基板ホ
ルダ３３にはシースヒータ３９が埋め込まれてい
ると同時に裏面には冷却水用流路４０がうず巻き
状に形成されている。冷却水流路４０はパイプ４
１、供給電極４２により形成の流入冷却水４３用
流路４４および流出冷却水４５用流路４６と接続
している。基板電極４２は絶縁物４７を介して真
空槽２４に固定されている。４８は陽極である。
ターゲツトと同様に基板電極４２と陽極４８の間
に電源４９が設置されている。５０は温度検出器
で、ばね５１を介して基板ホルダ３３に設置され
ている。 Further, the substrate 32 is pressed onto the substrate holder 33 by a chuck 34. The upper surface of the substrate holder 33 is made of a dielectric material 35 with a thickness of several tens of micrometers, and the surface has a gently convex shape. A microhole 36 is formed in the center of the substrate holder 33 and is connected to a gas 37 supply pipe 38 . Furthermore, a sheath heater 39 is embedded in the substrate holder 33, and at the same time, a cooling water flow path 40 is formed in a spiral shape on the back surface. The cooling water flow path 40 is a pipe 4
1. It is connected to a flow path 44 for inflow cooling water 43 and a flow path 46 for outflow cooling water 45 formed by the supply electrode 42. The substrate electrode 42 is fixed to the vacuum chamber 24 via an insulator 47. 48 is an anode.
Similar to the target, a power source 49 is installed between the substrate electrode 42 and the anode 48. A temperature detector 50 is installed on the substrate holder 33 via a spring 51.
以上の構成において、磁気装置３１はミラー磁
場を構成し、マイクロ波発生源３０からのマイク
ロ波を導波管２８によりプラズマ発生室２７に導
くと、前記磁気装置３１によつて作られる静磁界
によつてマイクロ波はプラズマ発生室２７内の零
囲気ガスを電離し、プラズマ状態とする。さらに
プラズマは磁力線５２に沿つてターゲツト２０の
表面全面に輸送される。ここで、陽陰電極間に電
源２６により電力を印加するとスパツタリングガ
生じ基板３２上に膜が形成される。 In the above configuration, the magnetic device 31 forms a mirror magnetic field, and when the microwave from the microwave generation source 30 is guided into the plasma generation chamber 27 through the waveguide 28, the static magnetic field created by the magnetic device 31 Therefore, the microwave ionizes the ambient gas in the plasma generation chamber 27 and turns it into a plasma state. Furthermore, the plasma is transported along the magnetic field lines 52 over the entire surface of the target 20. Here, when power is applied from the power source 26 between the positive and negative electrodes, sputtering occurs and a film is formed on the substrate 32.
ところで、基板３２はチヤツク３４により基板
ホルダ３３上の凸形状をした絶縁物３５上に押し
付けられ固定されており、電源４９により基板電
極４２と陽極４８間に電力を供給するとプラズマ
を介して静電吸着により全面が絶縁物に吸着され
る。 By the way, the substrate 32 is pressed and fixed onto a convex insulator 35 on the substrate holder 33 by a chuck 34, and when power is supplied between the substrate electrode 42 and the anode 48 by a power source 49, electrostatic charge is generated via plasma. The entire surface is attracted to the insulator by adsorption.
同時に、基板上に付着の膜もバイアススパツタ
され膜の平坦化が行われる。この時、基板には熱
流入があり、例えばAr，N2などのガス３７を基
板ホルダ３３の微小穴３６から絶縁物３５・基板
３２の微小すきまに供給し、さらに冷却水４３を
流路４０に流すことにより前記ガス３７を介して
効果的に基板３２の冷却が可能となる。一方、基
板３２の温度をさらに上げたい場合には、冷却水
４３の供給をやめシースヒータ３９を作動させる
ことにより、同様にガス３７を介して効率よく加
熱することができる。 At the same time, the film deposited on the substrate is also subjected to bias sputtering to flatten the film. At this time, heat flows into the substrate, and a gas 37 such as Ar or N 2 is supplied from the minute hole 36 of the substrate holder 33 into the minute gap between the insulator 35 and the substrate 32, and cooling water 43 is supplied to the flow path 40. By flowing the gas 37, the substrate 32 can be effectively cooled through the gas 37. On the other hand, if it is desired to further raise the temperature of the substrate 32, by stopping the supply of the cooling water 43 and activating the sheath heater 39, it is possible to similarly efficiently heat the substrate 32 via the gas 37.
また、基板を一定温度に維持したい場合には、
基板３２にばね５１をダンパーにして接する温度
計５０を用いて、冷却水４３の供給・停止および
シースヒータ３９のON・OFFを行うことにより
実現できる。ここでは、温度計を接触形に限定し
て述べたが、非接触形の温度計を用いても同様に
制御ができるのは言うまでもない。 Also, if you want to maintain the board at a constant temperature,
This can be achieved by supplying and stopping the cooling water 43 and turning the sheath heater 39 on and off using a thermometer 50 that is in contact with the substrate 32 using a spring 51 as a damper. Although the thermometer described here is limited to a contact type, it goes without saying that the same control can be performed using a non-contact type thermometer.
なお、上記はマイクロ波を用いてプラズマを形
成しスパツタを行う装置の基板温度制御について
述べたが、従来のプレーナマグネトロン型スパツ
タリング装置の場合にも同様に応用可能であるこ
とは言うまでもない。 Although the above description has been made regarding substrate temperature control of an apparatus that performs sputtering by forming plasma using microwaves, it goes without saying that the present invention can be similarly applied to a conventional planar magnetron type sputtering apparatus.
以上のごとくスパツタリング装置の基板温度を
制御可能とすることにより、素子の耐熱条件を満
足できるとともに、素子寿命の確保が実現でき
た。 By making it possible to control the substrate temperature of the sputtering apparatus as described above, it was possible to satisfy the heat resistance conditions of the element and ensure the life of the element.
以上述べたように、スパツタリング装置でバイ
アススパツタのように基板への熱流入がある場
合、基板温度を制御可能に基板ホルダを構成する
ことにより、素子内配線や不純物ドーププロフイ
ルの様に熱影響をうけやすい対象を保護すること
が可能となる。また、基板温度を最適温度に制御
することにより素子寿命の低下が妨げるなど素子
の信頼性および性能を向上することができる。
As mentioned above, when heat flows into the substrate in sputtering equipment such as bias sputtering, by configuring the substrate holder so that the substrate temperature can be controlled, thermal effects such as internal wiring and impurity doped profiles can be reduced. This makes it possible to protect subjects who are susceptible to damage. Further, by controlling the substrate temperature to an optimum temperature, it is possible to improve the reliability and performance of the device by preventing a decrease in the device life.
また、通常スパツタ膜は堆積原子・分子が複雑
に並んだアモルフアス状態を呈しているが、基板
温度制御を行うことにより、多結晶状態を形成す
ることも可能であり、膜の結晶制御も可能とな
る。 In addition, although sputtered films normally exhibit an amorphous state in which the deposited atoms and molecules are arranged in a complicated manner, by controlling the substrate temperature, it is possible to form a polycrystalline state, making it possible to control the crystalline structure of the film. Become.
第１図は本発明の一実施例の半導体の多層配線
構造の一例を示す縦断面図、第２図はバイアスス
パツタ法の原理を示す説明図、第３図は本発明の
実施例を応用したスパツタリング装置の構造を示
す断面図、第４図は本発明の実施例を示す基板温
度制御部の構造を示す断面図である。
２０……ターゲツト、３２……基板、３３……
基板ホルダ、３７……ガス、３９……シースヒー
タ、４３……冷却水、５０……温度計。
FIG. 1 is a vertical cross-sectional view showing an example of a semiconductor multilayer wiring structure according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the principle of the bias sputtering method, and FIG. 3 is an application of the embodiment of the present invention. FIG. 4 is a cross-sectional view showing the structure of a substrate temperature control section showing an embodiment of the present invention. 20...Target, 32...Substrate, 33...
Substrate holder, 37...Gas, 39...Sheath heater, 43...Cooling water, 50...Thermometer.
Claims (1)
より前記ターゲツトと対向する基板電極に載置さ
れた基板上に薄膜を形成するスパツタリング装置
であつて、前記基板電極は前記基板電極を加熱又
は冷却する加熱冷却手段と、前記基板の温度を検
出する温度検出手段と、前記載置面と前記基板の
裏面との間にガスを導入するガス導入手段と、前
記基板にバイアス電圧を印加する電圧印加手段を
備え、該電圧印加手段で前記基板にバイアス電圧
を印加しながらスパツタにより前記基板上に薄膜
を形成する時に、前記温度検出手段で測定した前
記基板の温度に基づいて前記加熱冷却手段で前記
基板電極を加熱又は冷却し、同時に前記ガス導入
手段で前記載置面と前記基板の裏面との間にガス
を導入して前記載置面と前記基板の裏面との間の
熱伝導を良くすることにより前記基板の温度を所
定の温度に維持することを特徴とするスパツタリ
ング装置。 ２ 前記基板電極は、前記基板の載置面が薄い誘
電体層で覆われており、前記バイアス電力を印加
することにより前記薄い誘電体層の表面に発生す
る静電気力で前記基板を前記基板電極に吸引する
ことにより前記基板を保持し、前記基板の温度を
所定の温度に維持することを特徴とする特許請求
の範囲第１項に記載のスパツタリング装置。[Scope of Claims] 1. A sputtering device for forming a thin film on a substrate placed on a substrate electrode facing the target by sputtering a target in a vacuum chamber, wherein the substrate electrode heating and cooling means for heating or cooling; temperature detection means for detecting the temperature of the substrate; gas introduction means for introducing gas between the mounting surface and the back surface of the substrate; and applying a bias voltage to the substrate. and a voltage applying means for forming a thin film on the substrate by sputtering while applying a bias voltage to the substrate with the voltage applying means, the heating and cooling is performed based on the temperature of the substrate measured by the temperature detecting means. The device heats or cools the substrate electrode, and at the same time, the gas introduction device introduces gas between the placement surface and the back surface of the substrate to conduct heat between the placement surface and the back surface of the substrate. A sputtering apparatus characterized in that the temperature of the substrate is maintained at a predetermined temperature by improving the temperature of the substrate. 2. In the substrate electrode, a surface on which the substrate is placed is covered with a thin dielectric layer, and when the bias power is applied, an electrostatic force generated on the surface of the thin dielectric layer causes the substrate to be placed on the substrate electrode. 2. The sputtering apparatus according to claim 1, wherein the substrate is held by suction to maintain the temperature of the substrate at a predetermined temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18951785A JPS6250462A (en) | 1985-08-30 | 1985-08-30 | Sputtering device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18951785A JPS6250462A (en) | 1985-08-30 | 1985-08-30 | Sputtering device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6250462A JPS6250462A (en) | 1987-03-05 |
| JPH0586477B2 true JPH0586477B2 (en) | 1993-12-13 |
Family
ID=16242606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18951785A Granted JPS6250462A (en) | 1985-08-30 | 1985-08-30 | Sputtering device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6250462A (en) |
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|---|---|---|---|---|
| US6855992B2 (en) | 2001-07-24 | 2005-02-15 | Motorola Inc. | Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same |
| US6885065B2 (en) | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
| US6916717B2 (en) | 2002-05-03 | 2005-07-12 | Motorola, Inc. | Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate |
| US6965128B2 (en) | 2003-02-03 | 2005-11-15 | Freescale Semiconductor, Inc. | Structure and method for fabricating semiconductor microresonator devices |
| US6992321B2 (en) | 2001-07-13 | 2006-01-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
| US7005717B2 (en) | 2000-05-31 | 2006-02-28 | Freescale Semiconductor, Inc. | Semiconductor device and method |
| US7020374B2 (en) | 2003-02-03 | 2006-03-28 | Freescale Semiconductor, Inc. | Optical waveguide structure and method for fabricating the same |
| US7019332B2 (en) | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
| US7045815B2 (en) | 2001-04-02 | 2006-05-16 | Freescale Semiconductor, Inc. | Semiconductor structure exhibiting reduced leakage current and method of fabricating same |
| US7067856B2 (en) | 2000-02-10 | 2006-06-27 | Freescale Semiconductor, Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
| US7105866B2 (en) | 2000-07-24 | 2006-09-12 | Freescale Semiconductor, Inc. | Heterojunction tunneling diodes and process for fabricating same |
| US7161227B2 (en) | 2001-08-14 | 2007-01-09 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for detecting an object |
| US7169619B2 (en) | 2002-11-19 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process |
| US7211852B2 (en) | 2001-01-19 | 2007-05-01 | Freescale Semiconductor, Inc. | Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate |
| US7342276B2 (en) | 2001-10-17 | 2008-03-11 | Freescale Semiconductor, Inc. | Method and apparatus utilizing monocrystalline insulator |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2594935B2 (en) * | 1987-04-01 | 1997-03-26 | 株式会社日立製作所 | Sputter film forming method and apparatus |
| JPH07105422B2 (en) * | 1987-03-16 | 1995-11-13 | 東京エレクトロン株式会社 | Semiconductor wafer mounting table |
| JPH083146B2 (en) * | 1989-10-16 | 1996-01-17 | 富士通株式会社 | Thin film formation method |
| KR940011708B1 (en) * | 1990-04-09 | 1994-12-23 | 니찌덴 아네루바 가부시끼가이샤 | Temperature control device for semiconductor wafer |
| KR19990085791A (en) * | 1998-05-21 | 1999-12-15 | 윤종용 | Measuring Equipment for Semiconductor Manufacturing Process |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5940439U (en) * | 1982-09-08 | 1984-03-15 | アイジ−工業株式会社 | Corner panel for inside corner |
| JPS59181622A (en) * | 1983-03-31 | 1984-10-16 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1985
- 1985-08-30 JP JP18951785A patent/JPS6250462A/en active Granted
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7067856B2 (en) | 2000-02-10 | 2006-06-27 | Freescale Semiconductor, Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
| US7005717B2 (en) | 2000-05-31 | 2006-02-28 | Freescale Semiconductor, Inc. | Semiconductor device and method |
| US7105866B2 (en) | 2000-07-24 | 2006-09-12 | Freescale Semiconductor, Inc. | Heterojunction tunneling diodes and process for fabricating same |
| US7211852B2 (en) | 2001-01-19 | 2007-05-01 | Freescale Semiconductor, Inc. | Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate |
| US7045815B2 (en) | 2001-04-02 | 2006-05-16 | Freescale Semiconductor, Inc. | Semiconductor structure exhibiting reduced leakage current and method of fabricating same |
| US6992321B2 (en) | 2001-07-13 | 2006-01-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
| US7019332B2 (en) | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
| US6855992B2 (en) | 2001-07-24 | 2005-02-15 | Motorola Inc. | Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same |
| US7161227B2 (en) | 2001-08-14 | 2007-01-09 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for detecting an object |
| US7342276B2 (en) | 2001-10-17 | 2008-03-11 | Freescale Semiconductor, Inc. | Method and apparatus utilizing monocrystalline insulator |
| US6916717B2 (en) | 2002-05-03 | 2005-07-12 | Motorola, Inc. | Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate |
| US7169619B2 (en) | 2002-11-19 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process |
| US6885065B2 (en) | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
| US6965128B2 (en) | 2003-02-03 | 2005-11-15 | Freescale Semiconductor, Inc. | Structure and method for fabricating semiconductor microresonator devices |
| US7020374B2 (en) | 2003-02-03 | 2006-03-28 | Freescale Semiconductor, Inc. | Optical waveguide structure and method for fabricating the same |
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| Publication number | Publication date |
|---|---|
| JPS6250462A (en) | 1987-03-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |