JPH0584130B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an automatic synchronization device, and in particular, a device that is necessary when operating multiple generators in parallel or when operating a generator in grid connection with a commercial power source. The present invention relates to an automatic synchronous closing device that automatically closes a circuit breaker.

[Prior Art] If the circuit breaker is carelessly closed, it may not only cause the circuit breaker to fail, but also cause serious accidents such as equipment damage, fire, and personal injury.
In order to perform the circuit breaker closing operation reliably, automation of the circuit breaker closing operation is being carried out.

FIG. 6 is a block diagram showing an example of such a device. Referring to FIG. 6, an alternator 1 is connected to a circuit breaker 2 for connecting the alternator 1 to a bus bar. A voltage transformer 3 is connected to the generator side of the circuit breaker 2, and a voltage transformer 4 is connected to the busbar side. Instrument transformer 3, 4
An automatic synchronization input device 16 is connected to the secondary side of each of the. The automatic synchronization device 16 includes auxiliary transformers 5 and 6, the auxiliary transformer 5 is connected to the secondary side of the voltage transformer 3, and the auxiliary transformer 6 is connected to the secondary side of the voltage transformer 4. ing. A frequency high/low discrimination circuit 7, a phase difference detection circuit 8, and a voltage difference detection circuit 9 are connected to the secondary sides of the auxiliary transformers 5 and 6. A frequency high/low discrimination circuit 7 is provided to determine whether the frequency is high or low between the generator side and the bus side, and a phase difference detection circuit 8 is provided to detect the phase difference between the voltages on the generator side and the bus side. A voltage difference detection circuit 9 is provided to detect a voltage difference between the generator side and the bus bar side.

The output of the phase difference detection circuit 8 is applied to a smoothing circuit 10 and smoothed into a DC voltage, and this DC voltage is applied to a differentiating circuit 11 and a comparison circuit 14.
The differentiating circuit 11 differentiates the output of the smoothing circuit 10, provides the differentiated output to the comparator circuit 13 and the variable resistor 12, and outputs it to the output terminal. Variable resistor 12
divides the output voltage of the differentiating circuit 11 and supplies it to the comparator circuit 14 as a reference voltage. On the other hand, comparison circuit 13
compares the output of the differentiating circuit 11 with a preset value and supplies the comparison output to the closing condition check circuit 15. A comparison circuit 14 is provided to compare phases, and its comparison output is given to a closing condition check circuit 15. The voltage detected by the voltage difference detection circuit 9 is applied to the closing condition check circuit 15. The closing condition check circuit 15 checks the closing signal generation conditions based on the outputs of the comparison circuits 13 and 14 and the output of the voltage difference detection circuit 9, and outputs the closing signal.

7A, 7B, 8, and 9 are waveform diagrams showing the operating states of each part of the automatic synchronization device shown in FIG. 6.

Next, the operation of the conventional automatic synchronization input device 16 will be explained with reference to FIGS. 6 to 9.
When the circuit breaker 2 is turned on, it is necessary that the contacts of the circuit breaker 2 come into contact at a point where the phases of the generator side and the busbar side match (hereinafter referred to as a phase matching point). For this reason, regardless of the frequency difference, the closing command needs to be output at a time point (hereinafter referred to as progressive time) before the phase matching point by the time required for the contacts of the circuit breaker 2 to come into contact. These things are explained by the phase difference detection circuit 8, smoothing circuit 10, and differentiation circuit 11.
This is realized by the variable resistor 12 and the comparison circuit 14.

That is, the phase difference detection circuit 8 is configured as shown in FIG.
As shown in b, bus voltage v ₁ and generator voltage v ₂
are waveform-shaped and converted into rectangular wave signals e ₁ and e ₂ as shown in FIG. 7A c and d. Next, the phase difference detection circuit 8 takes the exclusive OR of the rectangular wave signals e ₁ and e ₂ to generate a rectangular wave signal e ₃ as shown in FIG. 7A e. The time Tθ during which the rectangular wave _e3 shown in FIG. 7A is at the "H" level is proportional to the phase difference θ between the voltages of the bus and the generator. The smoothing circuit 10 is constituted by a reduction filter circuit, and calculates the average voltage of the rectangular wave signal e ₃ that is the output of the phase difference detection circuit 8, and
It outputs a DC voltage _E1 as shown in Figure A f. Here, if the voltage when the rectangular wave signal e ₃ is at "H" level is Em, the voltage when it is at "L" level is OV, and the period is T ₁ , then the output E ₁ of the smoothing circuit 10 is
is T〓∝θ ……(1) E ₁ =T〓/T ₁・Em ……(2) Therefore, E ₁ ∝θ ……(3) When θ=O, E ₁ = OV(T 〓=O) ……(4) When θ=180°, E ₁ =Em(T〓=T ₁ ) ……(5) The relationship between the phase difference θ and the output E ₁ of the smoothing circuit 10 is the 7th B. The result will be as shown in the figure.

If the phase difference θ is constant, the output of the smoothing circuit 10
E ₁ becomes a constant value as shown in Figure 7A f, but
If there is a difference in frequency between the busbar side and the generator side, the phase difference θ changes with time. If the frequency difference ΔF between the bus side and the generator side is constant, the output _E1 of the smoothing circuit 10 changes with time and becomes a triangular waveform, as shown in FIG. 8d. Output of smoothing circuit 10
E ₁ is applied to the differentiating circuit 11, and a voltage proportional to the differential value of the output E ₁ of the smoothing circuit 10 is obtained, and a voltage E ₂ (Fig. 8e) with the polarity of the voltage inverted is applied to the differentiating circuit 11. is output from. When the frequency difference ΔF is constant, the output E ₂ of the differentiating circuit 11 is the 8th
The waveform will be as shown in Figure e.

The comparison circuit 14 is provided to compare the magnitude of the input voltage, and the output E ₁ of the smoothing circuit 10 is given to this comparison circuit 14 as a comparison input, and the output E ₂ of the differentiating circuit 11 is applied to the variable resistor 12. The voltage E ₂ ' divided by is input as the reference voltage. The output E ₃ of the comparator circuit 14 is as follows: When E ₁ > E ₂ ′, E ₃ = “L” ... (6) When E ₁ < E ₂ ', E ₃ = “H” ... (7) Become.

In FIG. 8, if the phase matching point is time t=0 and the time from the time t _c when voltages E ₁ and E ₂ ' become equal to the phase matching point is Tc, then E ₂ , E ₂ '∝ΔF... …(8) E ₁ =-2・ΔF・Em・t(-1/(2・ΔF)
t0) ...(9) E ₂ '=-K・dE ₁ /dt=2・K・ΔF・Em
(-1/(2・ΔF)t0) ...(10) However, K is the constant of proportionality E ₁ = E ₂ ' (t=t _c ) ...(11) t _c =-K ...(12) ∴ Tc=K (13), and the time Tc is a constant time regardless of the frequency difference ΔF.

By changing the voltage division ratio of the variable resistor 12, the time Tc can be varied, and by adjusting the time Tc to the closing time of the circuit breaker 2 and making it a gradual time, the contacts of the circuit breaker 2 can be changed. It can be turned ON at the phase matching point.

On the other hand, the comparison circuit 13 receives the input differentiation circuit 1
Compare the output E ₂ of 1 with a preset voltage,
When the voltage _E2 becomes smaller than a preset voltage, that is, a voltage corresponding to the frequency difference that can close the circuit breaker 2, the output _E4 is set to the "H" level. In addition, a voltage difference detection circuit 9 receives a voltage proportional to the voltage on the generator side and the busbar side obtained by the instrument transformers 3 and 4 and the auxiliary transformers 5 and 6, and rectifies the input voltage. , calculate the difference, convert it to a DC voltage using a built-in smoothing circuit, and compare it with a preset voltage, that is, a voltage corresponding to the voltage difference that can close the circuit breaker. When the voltage becomes smaller than the set voltage, the output E ₅
to “H” level.

The closing condition check circuit 15 detects that when the output E ₃ of the comparison circuit 14 rises to the "H" level, the output E ₄ of the comparison circuit 13 and the output E ₅ of the voltage difference detection circuit 9 are at the "H" level. Check whether or not. The closing condition check circuit 15 determines that when the output E ₃ of the comparison circuit 14 rises to the "H" level, the output E ₄ of the comparison circuit 13 and the output E ₅ of the voltage difference detection circuit 9 both go "H". If the level
A signal E ₆ having the same waveform as the output E ₄ of the comparison circuit 13 is output.

When the output _E3 of the comparison circuit 14 rises to the "H" level, if both the output _E4 of the comparison circuit 13 and the output _E5 of the voltage difference detection circuit 9 are not at the "H" level, the closing condition check circuit is activated. 15 output E ₆
remains unchanged at "L" level. The output E ₆ of this closing condition check circuit 15 is power amplified and drives a circuit breaker closing command output relay (not shown).
Turn on the circuit breaker.

On the other hand, the frequency high/low discrimination circuit 7 detects the high/low frequencies of the generator side and busbar side frequencies inputted via the auxiliary transformers 5 and 6. The output of the frequency high/low discrimination circuit 7 and the output of the differentiating circuit 11, which is proportional to the magnitude of the frequency difference between the generator side and the bus side, are output to the speed equalization circuit to control the frequency difference. The frequency high/low discrimination circuit 7 shapes the voltage signals v ₁ and v ₂ on the generator side and the busbar side as shown in FIGS. Create the rectangular wave signals e ₁ and e ₂ shown in Figures c and e, and send the rectangular wave signal e _1T (Figure 9 d), which remains at "H" level for a certain period of time after the rectangular wave signal e ₁ rises, to a timer circuit. and a pulse signal e _2P (FIG. 9f) which becomes "H" level when the rectangular wave signal e ₂ rises.

If there is a difference in frequency between the bus side and the generator side, the phase difference θ changes over time, and the rectangular wave signals e ₁ , e _1T shown in Fig. 9 c and d and the rectangular waves shown in Fig. 9 e and f wave signal
The relative positional relationship between e ₂ and pulse signal e _2P changes over time. That is, when the frequency on the generator side is lower than that on the busbar side, the position of the pulse signal e _2P moves to the right over time with respect to the rectangular wave signals e ₁ and e _1T . If the frequency on the generator side is higher than that on the busbar side, for the square wave signals e ₁ and e _1T ,
The position of pulse signal e _2P moves to the left as time passes. Here, at the position of the pulse signal _e2P , from the position where the rectangular wave signal _e1 is at "L" level,
When it moves to the “H” level position, the square wave signal
Depending on whether e _2P is at the “H” level or “L” level, the square wave signals e ₁ and e _1T of the pulse signal e _2P
It is possible to detect whether the relative positional relationship to the generator is moving to the right or to the left, that is, whether the frequency on the generator side is lower or higher than that on the busbar side.

[Problems to be Solved by the Invention] A conventional automatic synchronization input device is constructed of a circuit as shown in FIG. 6, but it has the following problems. That is, the portion that detects the gradual time is mainly composed of analog circuits, and the gradual time is set using a variable resistor. For this reason, setting changes after shipment from the factory rely on the scale, and the influence of scale reading errors is large, making it difficult to set and read accurately.

In addition, when operating an AC synchronous generator in a grid-connected manner with a commercial power source in a cozi energy system, etc., reverse power flow often becomes a problem. It is sometimes desirable to be able to limit the frequency relationship between the grid side and the generator side as a condition for enabling power supply.
However, with conventional automatic synchronization devices, there are few points at which high and low frequencies can be determined, and the phase difference is 0 to 0.
It was detected only at one or a few points in a 360° range. For this reason, it has been difficult to limit the frequency relationship between the system side and the generator side at the time of power-on.

Therefore, the main purpose of the present invention is to digitize settings such as the gradual time, eliminate reading errors and reset errors, and detect high and low frequencies on the bus side and the generator side every cycle. By providing an automatic synchronization start-up device that can limit the frequency relationship between the grid side and the generator side at the time of the start-up signal generation, and increase stability during grid-connected operation with a commercial power source. be.

[Means for Solving the Problems] This invention provides a system in which multiple generators are operated in parallel or in a system where the generators are operated in connection with a commercial power source, and when the generators are connected in parallel to the bus bar, the circuit breaker is closed. an automatic synchronization device that automatically gives commands, and first waveform shaping means that converts sinusoidal voltages on the bus side and the generator side into rectangular waves, respectively;
phase lag detection means for selectively outputting a pulse train signal whose pulse width is the phase lag of the output rectangular wave of the second waveform shaping means with respect to the output rectangular wave of the first waveform shaping means, or the opposite phase lag time, respectively; basic clock signal generating means for generating a basic clock signal; pulse signal generating means for outputting a first pulse signal in response to the pulse train signal output from the phase delay detecting means and the basic clock signal; A first counter means that counts the signal and outputs a count value proportional to the phase delay time, and a previous count value of the output of the first counter means that is proportional to the frequency difference between the generator side and the bus side as a set value. , 1st
a second counter means that counts the pulse signals of and calculates the difference between the previous count value output from the first counter means and the current count value; and count outputs of the first and second counter means as address inputs. and a storage means for outputting data proportional to the time until the phase matching point, and the data read from the storage means are set, and a second clock signal is counted to output data proportional to the time until the phase matching point. a third counter means for outputting a numerical value; a circuit breaker closing time setting means for digitally setting the circuit breaker closing time; and a count output of the third counter means and a set value of the circuit breaker closing time setting means. a first comparison means that outputs a signal when the count output of the third counter means is equal to or smaller than the set value;
A closing frequency difference limit value setting means for digitally setting a closing frequency difference limit value, and a count value of the output of the second counter means and a setting value set by the closing possible frequency difference limit setting means. and a second comparison means that outputs a signal when the count value output from the second counter means is smaller than the set value, and a basic clock signal is counted each time a pulse train signal is output from the phase delay detection means. The third counter means is given a first pulse for presetting, the second counter means is given a second pulse for reset, and the first counter means is given a third pulse for reset. and a decode counter means that sequentially generates a fourth pulse to stop its own counting, and a decode counter means that calculates a DC voltage proportional to the difference voltage between the voltage on the generator side and the voltage on the bus side, and calculates a DC voltage proportional to the voltage difference between the generator side voltage and the bus side voltage, and When the voltage difference detection means that performs a comparison with the predetermined closing limit voltage difference and the first comparison means output a signal, the output of the second comparison means and the respective outputs of the voltage difference detection means both reach the output of the circuit breaker. If the closing conditions are satisfied, the same signal as the output of the first comparison means is output, and the output of the second comparison means and each output of the voltage difference detection means must both satisfy the circuit breaker closing conditions. For example, it includes a closing condition check means for blocking the output signal.

[Function] The automatic synchronization device according to the present invention digitizes the gradual time detection unit and the input frequency difference detection unit, so that the gradual time setting and the input frequency difference limit are set using a digital switch. This solves the problem of reading errors and resetting errors.

[Embodiment of the Invention] FIG. 1 is a block diagram showing the overall configuration of an embodiment of the invention, FIG. 2 is a block diagram of the phase lag detection circuit shown in FIG. 1, and FIG. 2 is a block diagram of the voltage difference detection circuit shown in FIG. 1. FIG.

Next, the configuration of an embodiment according to the present invention will be described with reference to FIGS. 1 to 3. The alternating current generator 1, circuit breaker 2, potential transformers 3, 4, and auxiliary transformers 5, 6 shown in FIG. 1 are connected in the same manner as in the example shown in FIG. 6 described above. The automatic synchronization device 38 is connected to the generator side and the busbar side via the voltage transformers 3 and 4. Auxiliary transformer 5 is connected to the secondary side of voltage transformer 3 , and auxiliary transformer 6 is connected to the secondary side of voltage transformer 4 . A waveform shaping circuit 22 is connected to the secondary side of the auxiliary transformer 5.
The secondary side of the auxiliary transformer 6 is connected to a waveform shaping circuit 21. The waveform shaping circuits 21 and 22 each shape a sine wave into a rectangular wave. Further, the secondary side of each of the auxiliary transformers 5 and 6 is connected to a voltage difference detection circuit 2.
It is also connected to 3. The voltage difference detection circuit 23 detects the voltage difference between the generator side and the busbar side, and as shown in FIG.
46, an adder circuit 47 that adds the outputs of the diodes 45 and 46, and a comparison circuit 48 that compares the voltage set by the variable resistor 49 and the output of the adder circuit 47.

The outputs of the waveform shaping circuits 21 and 22 are given to a phase lag detection circuit 24. The phase lag detection circuit 24 detects the phase lag on the generator side with respect to the bus side or the phase lag on the bus side with respect to the generator side, and as shown in FIG. 41 and D-type flip-flops 42 and 43. A FAST/SLOW closing selection switch 50 is connected to the phase lag detection circuit 24, which is a switch that selects the frequency relationship between the bus side and the generator side when the closing signal is generated.

The oscillation circuit 25 is composed of a crystal oscillator,
Generates basic clock signal CL ₀ and AND gate 2
6, the frequency divider circuit 27, and the decode counter 28. The aforementioned phase lag detection circuit 24
The detection signal is given to the decode counter 28 as a reset signal, and the AND gate 26
is applied to the other input terminal of . decode counter 2
8 is reset by the detection signal of the phase delay detection circuit 24, counts the basic clock signal _CL0 from the oscillation circuit 25, and sends the counted output _P1 to the latch circuit 3.
6 as a clock signal and the presettable down counter 32 as a load signal, the count output _P2 is given as a load signal to the presettable down counter 30, the count output _P3 is given as a reset signal to the up counter 29,
Count output P ₄ INH to stop self counting
give to input. The output signal of the AND gate 26 is applied to an up counter 29 and a presettable down counter 30 as a clock signal.

The frequency dividing circuit 27 counts the basic clock signal _CL0 given from the oscillation circuit 25, and supplies the counting output to the presettable down counter 32 as a clock signal. The count output of the up counter 29 is applied to a presettable down counter 30 and also to a memory 31 as an address signal. The count output of the presettable down counter 30 is also given to the memory 31 as an address signal, and the magnitude comparator 35
It is also given to The memory 31 is composed of, for example, a ROM, and data read from the memory 31 is applied to a presettable down counter 32.

The presettable down counter 32 outputs data from the memory 3 based on the count output _P1 of the decode counter 28.
1 is loaded, and its count output is applied to the comparison input A of the magnitude comparator 33. A comparison input B of the magnitude comparator 33 is connected to a circuit breaker closing time setting digital switch 39 . The comparison output of the magnitude comparator 33 is the input condition check circuit 3.
7 is given. The closing condition check circuit 37 includes the output PΔF of the latch circuit 36 and the voltage difference detection circuit 2.
Detection signal PΔV is given from 3. The closing condition check circuit 37 checks the closing conditions in response to these applied signals and outputs a closing signal.

4 and 5 are waveform diagrams showing the operating states of each part in FIG. 1.

Next, with reference to FIGS. 1 to 5, a specific operation of an embodiment of the present invention will be described.
The waveform shaping circuits 21 and 22 are shown in FIG.
As shown in b, a voltage v ₁₁ similar to the bus voltage,
When the polarity of each voltage v ₁₂ similar to the voltage on the generator side is positive, the output signals e ₁₁ and e ₁₂ are converted to "H" level as shown in Fig. 4c and d, and when the polarity is negative At this time, the output signals e ₁₁ and e ₁₂ are converted to the “L” level and output to the phase lag detection circuit 24. In the phase lag detection circuit ₂₄ , as shown in FIG. The output signal e ₁₂ of the waveform shaping circuit 22 is connected to the D-type flip-flop 43. Hereinafter, a case will be described in which the FAST/SLOW input selection switch 50 is switched to "OFF".

The D type flip-flop 42 is set to "H" level at the rise of the output signal _e11 of the waveform shaping circuit 21, and the D type flip-flop 23 is set to "H" level at the rise of the output signal _e12 of the waveform shaping circuit 22. ”
is set to the level. Further, when the Q output of the D type flip-flop 43 is set to the "H" level, the D type flip-flop 42 goes "L".
When the Q output of the D type flip-flop 42 is reset to the "L" level, the D type flip-flop 43 is reset to the "L" level.

Therefore, the voltage on the bus side and the voltage on the generator side are
When changing as shown in Figures a and b, the output signal e ₁₃ of the Q output of the D type flip-flop 42
As shown in FIG. 4e, when the output signal _e11 of the waveform shaping circuit 21 rises, it becomes "H" level, and when the output signal _e12 of the waveform shaping circuit 22 rises, it becomes "L" level.
level, and the output signal of the phase lag detection circuit 24
The time during which e ₁₃ is at the “H” level is the waveform shaping circuit 2 for the output signal e ₁₁ of the waveform shaping circuit 21
It is proportional to the delayed phase difference between the two output signals _e12 . That is, it is proportional to the delay phase difference of the generator side voltage with respect to the bus line side voltage.

Proceeding with the explanation from the timing when the output signal e ₁₃ of the phase lag detection circuit 24 rises, when the output signal e ₁₃ of the phase lag detection circuit 24 becomes "H" level, the decode counter 28 is reset and the AND Gate 26 is opened. the result,
Basic clock signal output from oscillation circuit 25
CL ₀ is applied to an up counter 29 and a presettable down counter 30. up counter 2
9 starts counting up, and the presettable down counter 30 starts counting down, and this state continues while the output signal _e13 of the phase lag detection circuit 24 is at the "H" level. Phase delay detection circuit 24
When the output signal _e13 becomes "L" level, the up counter 29 stops counting up, and the presettable down counter 30 stops counting down.

The output signal _e13 of the phase lag detection circuit 24 is “L”
The count end output value _P〓E (Fig. 4g) of the up counter 29 at the time when the up-counter 29 reaches the level becomes a value proportional to the delayed phase difference of the generator side voltage with respect to the bus side voltage. The count end output value _ΔP〓E (Fig. 4h) of the presettable down counter 30 is obtained by subtracting the current count end output value of the up counter 29 from the previous count end output value of the up counter 29, as described later. Becomes a value.

The output signal _e13 of the phase lag detection circuit 24 is “L”
When the level is reached, the decode counter 28 starts counting, and the output signal of the decode counter 28
P ₁ , P ₂ , P ₃ , and _{P 4} change from "L" to "H" to "L" in the order shown in FIG. When the count ends, the output value of the up counter 29
_P〓E is loaded (preset) into the presettable down counter 30.

Output signal _P3 of decode counter 28 is “H”
When the output signal reaches the "H" level, the up counter 29 is reset, and when the output signal ₄ of the decode counter 28 becomes "H" level, the decode counter 28 is prohibited from counting and enters a standby state, and the output of the phase lag detection circuit 24 is output again. When the signal _e13 becomes "H" level, the same operation is performed. As a result, the preset value of the presettable down counter 30 is
This becomes the last count end output value of the up counter 29. When the output signal _e13 of the phase lag detection circuit 24 becomes “H” level, the presettable down counter 30 starts counting down from the previous count output value of the up counter 29. When the output value _e13 reaches the "L" level, the count end output value ΔP of the presettable down counter 30 is
It becomes equal to the value obtained by subtracting the current count end output value from the previous count end output value of the up counter 29.

Here, as shown in FIG. 4e, the previous time when the output signal _e13 of the phase lag detection circuit 24 was at the "H" level is T〓o _-1 , and the current time is _T〓o . , the frequency of the basic clock signal CL ₀ output from the oscillation circuit 25 is _CL0 , the frequency of the voltage on the bus side is F _B , the frequency of the voltage on the generator side is F _G , the frequency of the voltage on the generator side with respect to the voltage on the bus side Letting the difference be ΔF, ΔF＝F _G −F _B ……(14) T〓 _o ＝T〓 _o-1 +1/F _G −1/F _B ……(15) Therefore, ΔP〓 _E = ( T〓 _o-1 −T〓 _o )× _CL0 = (1/F _B −1/F _G )× _CL0 = (ΔF×f _CL0 )/F _B ² (1+ΔF/F _B )
...(16), and since ΔF/F _B ≪1 ...(17), ΔP〓 _E ≒ΔF/F _B ² × _CL0 ...(18).

Here, the rated frequency is F _O , the difference between the bus side voltage frequency F _B and the rated frequency F _O is ΔF _B , and K ₁ and K ₂ are constants, f _CL0 = K ₁ × F _O ……(19 ) ΔF _B =F _B −F _O ...(20) Therefore, from equation (16), ΔP〓 _E ≒ΔF／{F _O ² (1+ΔF _B /F _O )}×K ₁ ×F _O
...(21), and since ΔF _B /F _O ≪1 ...(22), ΔP〓 _E ≒K ₁ × ΔF／F _O ......(23) ΔP〓 _E ≒K ₂ × ΔF …… (24) However, K ₂ = K ₁ /F _O ...(25). The count end output value _ΔP〓E of the presettable down counter 30 is proportional to the frequency difference ΔF between the generator side voltage and the bus side voltage. For example, if the constant K ₂ is 100, the resolution is 0.01 Hz.

On the other hand, the relationship between the previous time T〓o _-1 during which the output signal _e13 of the phase lag detection circuit 24 was at the "H" level, the current time _T〓o and the time _Tzo until the phase matching point is Figure 5 and below.

T _Zo = 1/F _G / (T〓 _o-1 −T〓 _o ) × T〓 _o ...(26) T _Zo = _CL0 /ΔP〓 _E ×1/F _G ×P〓 _E / _CL0 = P〓 _E /ΔP〓 _E ×1/F _G …(27) T _Zo =P〓 _E /ΔP〓 _E ×1/F _O (1+ΔF _G /F _O )
...(28) However, F _C = F _O + ΔF _G ...(29), which is approximately ΔF _G /F _O ≪1 ...(30), so T _Zo ≒P〓 _E /ΔP〓 _E ×1 /F _O ...(31) Therefore, the time T _Zo until the phase matching point can be obtained from the count end output value _P〓E of the up counter 29 and the count end output value _ΔP〓E of the presettable down counter 30. .

In the above equation (31), the division P〓 _E /ΔP _CE is required, and in one embodiment of the present invention, the memory 31 is used to realize this division. That is, the output of the up counter 29 and the output of the presettable down counter 30 are given as address signals of the memory 31, and the address conditions, that is, the count end output value _P〓E of the up counter 29 and the presettable down counter The value D _Zo , which is proportional to the time T _Zo until the phase matching point with respect to the count end output value _ΔP〓
1, a value D _Zo proportional to the time T _Zo until the phase matching point can be obtained as the output of the memory 31 at approximately every time interval of 1/rated frequency.

The output signal _e13 of the phase lag detection circuit 24 is “H”
When the output signal P1 of the decode counter 28 becomes "H" level, the up counter 29 and presettable down counter 30 stop counting, and the output signal _P1 of the decode counter 28 becomes "H" level.
1 output data D _Zo is loaded (preset) into the presettable down counter 32. The presettable down counter 32 is then counted down by the output signal _CL1 of the frequency divider circuit 27. The frequency of the output signal CL ₁ of the frequency divider circuit 27 is _{set to CL1}
If the output data D _Zo of the memory 31 is set as D _Zo = T _Zo × _CL1 ...(32), then the presettable down counter 3
The count output value _PZ of 2 is always the time _TZ up to the phase coincidence point at that point in time and the frequency _CL1 of the output signal _CL1 of the frequency dividing circuit 27.

P _Z = T _Z × _CL1 (33) In this case, the frequency division ratio of the frequency divider circuit 27 is K _f = _CL0 / _CL1 (34) where K _f is the frequency division ratio. Here, the progressive time (breaker closing time)
Let T _CB be T CB, set value of circuit breaker closing time setting digital switch 39 be P _CB , P _CB = T _CB × _CL1 ...(35), and connect a presettable down counter to input A of magnitude comparator 33. 32 and the set value of the circuit breaker closing time setting digital switch 39 is given to the input B, the magnitude comparator 33 compares the magnitudes of the inputs A and B, and the magnitude comparator 3
As shown in FIG. 4, the output signal P ₂₅ of No. 3 becomes "H" level while satisfying P _Z ≦P _CB (36) ∴ T _Z ≦T _CB (37).

The above explanation is for when the result of Equation (14) is positive, but when the frequency F _G on the generator side is lower than the frequency F _B on the busbar side, that is, Equation (14)
If the result of the formula is negative, T〓 _o-1 <T〓 _o ...(38), and the presettable down counter 30 becomes 0.
Counts down to a negative value less than or equal to the count (negative values are expressed as complements). If the address input of the memory 31 is the presettable down counter 30's count end output value ΔP〓 _E is a negative number, if the data in the memory 31 is set to the maximum value in advance, then equation (36) will hold true. Therefore, the result of equation (14) is that under the condition that the magnitude comparator 33 becomes negative, the output P ₂₅ does not reach the "H" level.

The above explanation is for the case where the FAST/SLOW input selection switch 50 is “OFF”;
When the SLOW input selection switch 50 is turned "ON", the signals on the bus side and the generator side are switched by the phase delay detection circuit 24, and the above-mentioned frequency on the bus side is switched.
The conditions of F _B and frequency F _G on the generator side are reversed.
This makes it possible to select between FAST side input and SLOW side input.

Next, the limit value of the frequency difference at which the circuit breaker may be closed (hereinafter referred to as the closing frequency difference limit) is ΔF _H , the set value of the closing frequency difference limit setting digital switch 40 is ΔP〓 _H , ΔP〓 _H = K ₂ × ΔF _H ...(39), connect the output of the presettable down counter 30 to the input A of the magnitude comparator 35, and connect the frequency difference limit setting digital switch 40 to the input B. The magnitude comparator 35 compares the magnitude of input A/B, and the output A of the magnitude comparator 35
<B is connected to the data input D of the latch circuit 36,
When the output signal P ₁ of the decode counter 28 is connected to the clock input CK of the latch circuit 36, the output signal PΔF of the latch circuit 36 becomes ΔP〓 _E ＜ΔP〓 _H ……(40) ∴ ΔF＜ΔF _H …… It becomes “H” level when (41) is satisfied.

The closing condition for the circuit breaker further requires a voltage difference condition, and this condition is checked by the voltage difference detection circuit 23. That is _, for example, in the voltage difference detection circuit ₂₃ shown in FIG. The signals are rectified by a polarity-connected diode 46 and added by an adder circuit 47. Since the diode 45 and the diode 46 are connected with opposite polarities, a DC voltage proportional to the difference voltage between the voltage on the generator side and the voltage on the bus bar side is obtained as the output of the adder circuit 47, and the adder circuit 47 is of a reduction filter type. If you do so, you can obtain a DC voltage proportional to the voltage difference with small ripple.

The comparator circuit 48 determines the voltage difference (hereinafter referred to as
The output of the adder circuit 47 is compared with the set value corresponding to the limit voltage difference that can be applied.
When the output of the comparator 7 becomes equal to or less than a preset value, the output signal PΔV of the comparison circuit 48 becomes “H” level.

Magnitude comparator 33 mentioned above
output signal P ₂₅ and output signal of latch circuit 36
_PΔF and the output signal PΔV of the voltage difference detection circuit 23
is applied to the closing condition check circuit 37. The closing condition check circuit 37 checks the latch circuit 36 when the output signal _P25 of the magnitude comparator 33 rises from the "L" level to the "H" level.
It is checked whether the output signal PΔF of the voltage difference detection circuit 23 and the output signal PΔV of the voltage difference detection circuit 23 are both at the "H" level. If both of them are at "H" level, the same signal as the output signal _P25 of the magnitude comparator 33 is input to the condition check circuit 37.
When the output signal _P25 of the magnitude comparator 33 rises from the "L" level to the "H" level, the output signal PΔF of the latch circuit 36 and the output of the voltage difference detection circuit 23 If both signals PΔV are not at “H” level,
The output signal 25X of the closing condition check circuit 37 is set to the "L" level.

Output signal 25 of this closing condition check circuit 37
By amplifying X and outputting it, for example, as a relay contact signal to the circuit breaker's closing operation circuit (not shown), an accurate breaker closing signal is generated within the closing frequency limit and within the closing voltage difference limit. can be output.

In the above description, the clock input signal CL ₁ of the presettable down counter 32 is divided into the basic clock signal CL ₀ of the oscillation circuit 25 by the frequency dividing circuit 27.
Although the frequency is divided by the frequency dividing circuit 27, an oscillation circuit separate from the oscillation circuit 25 may be provided instead of the frequency division circuit 27.

Furthermore, the same function can be achieved by using a shift register or a counter and a decoder instead of the decode counter 28.

Furthermore, FAST/SLOW input selection switch 50
By replacing the signal with a signal from outside the device, more organic operation can be achieved.

[Effects of the Invention] As described above, according to the present invention, by digitizing the gradual time detection unit and the input frequency difference detection unit, the gradual time setting device and the input frequency difference limit setting device can be improved. A digital switch can be used as a digital switch to solve the problem of reading error and resetting error. In addition, since it is possible to distinguish between high and low frequencies on the bus side and the generator side every cycle, it is possible to reliably supply power from the FAST side or from the SLOW side, making these selections very easy. This is easy to do and can improve stability during grid-connected operation with commercial power sources. Further, by digitizing, accuracy, repeatability error, temperature characteristics, and aging changes can be improved to a large extent.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. FIG. 2 is a block diagram showing an example of the phase lag detection circuit shown in FIG. 1. FIG. 3 is a block diagram showing an example of the voltage difference detection circuit shown in FIG. 1. 4 and 5 are waveform diagrams showing the operating states of each part of the automatic synchronization entry device shown in FIG. 1. FIG. 6 is a block diagram of a conventional automatic synchronization input device. 7A, 7B, 8, and 9 are waveform diagrams showing the operating states of each part of the automatic synchronization device shown in FIG. 6. In the figure, 1 is an alternator, 2 is a circuit breaker,
3 and 4 are instrument transformers, 5 and 6 are auxiliary transformers, 2
1 and 22 are waveform shaping circuits, 23 is a voltage difference detection circuit, 24 is a phase lag detection circuit, 25 is an oscillation circuit,
26 is an AND gate, 27 is a frequency dividing circuit, 28 is a decode counter, 29 is an up counter, 30,
32 is a presettable down counter, 31 is a memory, 33 and 35 are magnitude comparators, 36 is a latch circuit, 37 is a closing condition check circuit, 40 is a digital switch for setting the frequency difference limit that can be loaded, and 50 is a FAST/SLOW closing Shows selection switch.

Claims (1)

[Scope of Claims] 1. In a system in which a plurality of generators are operated in parallel or a generator is operated in grid connection with a commercial power source, when the generators are connected in parallel to a bus bar, a closing command is automatically issued to a circuit breaker. an automatic synchronization device that provides the following: a first waveform shaping means for converting the sine wave voltage on the bus side into a rectangular wave; a second waveform shaping means for converting the sine wave voltage on the generator side into a rectangular wave; Means: a phase delay time of the output rectangular wave of the second waveform shaping means with respect to the output rectangular wave of the first waveform shaping means, or the first waveform shaping means with respect to the output rectangular wave of the second waveform shaping means. phase lag detection means for selectively outputting a pulse train signal whose pulse width is the phase lag time of the output rectangular wave; basic clock signal generation means for generating a basic clock signal; and a pulse train signal output from the phase lag detection means. and said basic clock signal.
a first clock signal generated from the clock signal generating means;
a first counter means for counting the clock signal of the clock signal and outputting a count value proportional to the phase delay time; a second clock which counts the first clock signal generated from the clock signal generating means and calculates the difference between the previous counted value and the current counted value of the output of the first counter means, with the counted value as a set value; counter means, storage means for storing a predetermined value, receiving count outputs of the first and second counter means as address inputs, and outputting data proportional to the time to the phase matching point; read from the storage means; The third clock signal is set to the second clock signal and outputs a count value that is constantly proportional to the time until the phase matching point.
a counter means, a circuit breaker closing time setting means for digitally setting the closing time of the circuit breaker, and a count output of the third counter means and a set value of the circuit breaker closing time setting means are compared. , a first comparing means for outputting a signal when the count output of the third counter means is equal to or smaller than the set value; a possible frequency difference limit for digitally setting a possible frequency difference limit; value setting means, comparing the count value of the second counter means with the set value set by the input possible frequency difference limit value setting means, and the count value of the second counter means being greater than the set value; The second one outputs a signal when is also small.
a comparison means for counting the basic clock signal every time a pulse train signal is output from the phase delay detection means;
a first pulse for presetting data read out from the storage means in the third counter means; a second pulse for presetting a set value in the second counter means; a third pulse for resetting the counter means;
Decode counter means that sequentially generates a fourth pulse for stopping its own counting, a DC voltage proportional to the difference voltage between the voltage on the generator side and the voltage on the bus bar side is determined, and the DC voltage and a predetermined input voltage are determined. Voltage difference detection means for comparing with a possible limit voltage difference, and when the first comparison means outputs a signal, both the output of the second comparison means and the respective output of the voltage difference detection means meet the cutoff. If the closing conditions of the circuit breaker are satisfied, the same signal as the output of the first comparing means is output, and the output of the second comparing means and the respective outputs of the voltage difference detecting means both close the circuit breaker. An automatic synchronous input device equipped with input condition checking means that blocks the output signal if the conditions are not satisfied. 2 further comprising latching means for latching the output of the second comparing means in response to the first pulse output from the decoding counter means and applying the latch output to the closing condition checking means;
The automatic synchronization input device according to claim 1. 3. The automatic synchronization input device according to claim 1, further comprising frequency dividing means for dividing the frequency of said reference clock signal to generate said second clock signal and supplying said second clock signal to said third counter means. 4 further generating the second clock signal;
2. The automatic synchronization device according to claim 1, further comprising oscillation means for supplying said third counter means.