JPH071978B2 - Inverter open phase detection circuit - Google Patents
Inverter open phase detection circuitInfo
- Publication number
- JPH071978B2 JPH071978B2 JP61239750A JP23975086A JPH071978B2 JP H071978 B2 JPH071978 B2 JP H071978B2 JP 61239750 A JP61239750 A JP 61239750A JP 23975086 A JP23975086 A JP 23975086A JP H071978 B2 JPH071978 B2 JP H071978B2
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- Japan
- Prior art keywords
- current
- phase
- output
- inverter
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Inverter Devices (AREA)
Description
【発明の詳細な説明】 〔発明の属する技術分野〕 この発明は三相を含む多相インバータの欠相保護回路に
関する。Description: TECHNICAL FIELD The present invention relates to an open phase protection circuit for a multi-phase inverter including three phases.
従来のこの種インバータの欠相検出回路としては第4図
(a)及び(b)に示す三相インバータを例とした三相
出力電流欠相時の波形変化を利用するものが知られてい
る。第4図の(a)は三相インバータ出力電流が各相共
に正常な場合を示し、該図(b)はW相欠相時のU相及
びV相電流波形を示す。すなわちW相欠相時U相電流Iu
はV相電流Ivと大きさが等しく位相が反転する。逆にV
相電流IvはU相電流Iuの反転電流と等しくなる。今各相
電流Iu、Iv及びIwにつきそれぞれの反転電流u、v
及びwと表はすと上記のW相欠相時の各相電流関係は
Iu=v、Iv=u、Iw=0で表はせる。同様にV相欠
相時はIw=u、Iu=w、Iv=0となりU相欠相時に
はIv=w、Iw=v、Iu=0の関係がそれぞれ成立す
る。つまり三相中のいづれか一相の欠相時、他の二相中
のいづれかの相電流と残りの相の反転電流とが等しくな
る。従来の三相インバータ欠相検出回路は上記の諸関係
を組み合せ演算するものであり回路構成が複雑にならざ
るを得なかった。As a conventional open-phase detection circuit for this kind of inverter, there is known one using the waveform change at the open-phase of the three-phase output current as an example of the three-phase inverter shown in FIGS. 4 (a) and 4 (b). . FIG. 4 (a) shows the case where the output currents of the three-phase inverter are normal for each phase, and FIG. 4 (b) shows the U-phase and V-phase current waveforms when the W-phase is open. That is, U phase current Iu when W phase is open
Has the same magnitude as the V-phase current Iv and the phase is inverted. Conversely, V
The phase current Iv becomes equal to the reversal current of the U-phase current Iu. For each phase current Iu, Iv, and Iw, the reversal current u, v
And w, the relationship between the currents in each phase when the above W phase is lost is
It can be represented by Iu = v, Iv = u, and Iw = 0. Similarly, when the V phase is open, Iw = u, Iu = w, and Iv = 0, and when the U phase is open, the relationships of Iv = w, Iw = v, and Iu = 0 are established. That is, when any one of the three phases is open, the phase current of any of the other two phases becomes equal to the reversal current of the remaining phase. The conventional three-phase inverter open-phase detection circuit is a combinational calculation of the above-mentioned various relations, and thus the circuit configuration must be complicated.
この発明は上記に鑑み従来方法に比して回路構成の簡素
化と検出動作の信頼性の向上を計ったインバータの欠相
検出回路を提供することを目的とする。SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an inverter open-phase detection circuit that simplifies the circuit configuration and improves the reliability of the detection operation as compared with the conventional method.
この発明は前記目的を達成するために、インバータの直
流入力電流値を検出する直流変流器と、該インバータの
多相交流出力電流の各相電流値をそれぞれ検出する複数
の交流変流器と、前記直流変流器の検出電流値を適当な
値に減値変成する演算増巾器と、該演算増巾器の出力値
を基準値として前記多相交流出力電流の各相検出値との
大小を判別する複数の電流比較器と、該比較器出力信号
を入力とする複数の時限継電回路と、該複数の時限継電
回路出力信号を入力とする論理和素子と前記インバータ
の出力交流周波数が特定値以上にある場合に出力信号を
発する周波数リミッタと、該リミッタ出力信号と前記論
理和素子の出力信号とを入力とする論理積素子とから成
り、前記演算増巾器による電流基準値よりも前記多相交
流出力電流の各相電流検出値の方が小である期間が前記
インバータの最低動作周波数との関係で決定され且つ前
記複数の時限継電回路に共通の値として設定される設定
時間よりも長くなった場合には前記インバータの出力欠
相状態として欠相信号を発するものとする。In order to achieve the above object, the present invention provides a DC current transformer that detects a DC input current value of an inverter, and a plurality of AC current transformers that detect respective phase current values of a multiphase AC output current of the inverter. , An operational amplifier for degrading the detected current value of the DC current transformer to an appropriate value, and a detected value for each phase of the multi-phase AC output current with the output value of the operational amplifier as a reference value. A plurality of current comparators for discriminating the magnitude, a plurality of time relay circuits having the comparator output signals as inputs, an OR element having the plurality of time relay circuit output signals as inputs, and the output AC of the inverter A frequency limiter that emits an output signal when the frequency is equal to or higher than a specific value, and a logical product element that receives the limiter output signal and the output signal of the logical sum element as input, and a current reference value by the operational amplifier. Than each phase of the polyphase AC output current When the period in which the current detection value is smaller is determined in relation to the minimum operating frequency of the inverter and is longer than the set time set as a value common to the plurality of time relay circuits, It is assumed that an open phase signal is issued as the output open phase state of the inverter.
以下この発明の実施例を図面により説明する。第1図は
三相インバータを欠相検出対象例としたこの発明の実施
例を示す回路図、第2図は第1図に対応してU相電流欠
相時を例とする検出動作波形図、第3図は第2図に対し
てインバータ出力周波数が1/2に低下した場合を併記し
た検出動作波形図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention in which a three-phase inverter is used as an open phase detection target example, and FIG. 2 is a detection operation waveform diagram corresponding to FIG. , FIG. 3 is a detection operation waveform diagram in which the case where the inverter output frequency is reduced to 1/2 of that of FIG. 2 is also shown.
第1図において、直流電源1はトランジスタ2と転流ダ
イオード3を基本素子とする三相トランジスタインバー
タ20に電力を供給し、該インバータ20は三相負荷22に対
し三相可変周波数交流電力を供給する。前記インバータ
20の入力側直流電流検出用の直流変流器4の検出電流Id
cと出力交流変流回路5を構成する交流変流器5a、5b及
び5cにより検出された前記インバータ20の三相交流出力
電流の検出値Iu、Iv及びIwとはそれぞれ欠相演算回路21
に加えられる。該演算回路21において、演算増巾器6は
前記直流検出電流Idcの減値変成用演算器であり、電流
比較器8は前記増巾器6の出力値と前記電流検出値Iuと
の比較演算器であり、時限コンデンサ9aと時限抵抗10a
と電圧比較器11aとは前記電流検出値Iuの継続時間に対
する時限継電回路を構成する。同様に電流比較器8bと時
限コンデンサ9bと時限抵抗10bと電圧比較器11bとは前記
電流検出値Ivの比較判定用のものであり、電流比較器8c
と時限コンデンサ9cと時限抵抗10cと電圧比較器11cとは
前記電流検出値Iwの比較判定用のものである。In FIG. 1, a DC power supply 1 supplies electric power to a three-phase transistor inverter 20 having a transistor 2 and a commutation diode 3 as basic elements, and the inverter 20 supplies three-phase variable frequency AC power to a three-phase load 22. To do. The inverter
Detected current Id of DC current transformer 4 for detecting 20 input side DC current
c and the detected values Iu, Iv, and Iw of the three-phase AC output current of the inverter 20 detected by the AC current transformers 5a, 5b, and 5c forming the output AC current transformer circuit 5, respectively, are the open-phase operation circuit 21.
Added to. In the calculation circuit 21, the calculation amplifier 6 is a calculator for changing the value of the DC detection current Idc, and the current comparator 8 compares the output value of the amplifier 6 and the detected current value Iu. A timed capacitor 9a and a timed resistor 10a
And the voltage comparator 11a constitute a time relay circuit for the duration of the current detection value Iu. Similarly, the current comparator 8b, the timed capacitor 9b, the timed resistor 10b, and the voltage comparator 11b are for comparing and determining the current detection value Iv, and the current comparator 8c
The timed capacitor 9c, the timed resistor 10c, and the voltage comparator 11c are for comparing and determining the current detection value Iw.
論理和素子(OR素子)12は電圧比較器11a、11b及び11c
それぞれの出力信号を入力としその出力信号は周波数リ
ミッタ7の出力信号と共に論理積素子(AND素子)13に
入力され該素子13の出力信号が所要のインバータ20の欠
相検出信号となる。The OR element (OR element) 12 is a voltage comparator 11a, 11b and 11c.
Each output signal is input, and the output signal is input to the logical product element (AND element) 13 together with the output signal of the frequency limiter 7, and the output signal of the element 13 becomes the required open phase detection signal of the inverter 20.
この発明の実施例において、前記直流電流Idcは演算増
巾器6に入力され該増巾器6において1/2に減値されIdc
/2となって出力される。該電流値Idc/2は前記三相交流
出力電流検出値Iu、Iv及びIwとの比較演算の基準値とな
るものであり、前記インバータ20の三相交流出力各相に
欠相異常のない場合には前記電流Iu、Iv及びIwのそれぞ
れがその時間変動において必づ通過する値として設定さ
れたものである。上記の交直両電流の大小比較演算は、
前記電流Iu、Iv及びIwに応じてそれぞれ電流比較器8a、
8b及び8cにおいて行なはれる。例えばU相電流に関して
は前記電流Iuが前記基準値Idc/2より小となると電流比
較器8aは出力信号を発し次段時限コンデンサ9aの端子電
圧Vcは負電位V-から正電位V+に向って充電昇圧し逆に前
記電流Iuがその基準値Idc/2より大となると電流比較器8
aはその出力を反転し時限コンデンサ9aの端子電圧Vcは
負電位V-にリセットされる。前記U相出力回路が正常な
場合には前記端子電圧Vcの充電及びリセット動作は前記
電流Iuの各サイクル毎に繰り返され且つ該電圧Vcの値が
零電位0Vに達することはない。上記の電圧Vc及び電流Iu
の変動模様を第2図に示す。第2図において、もし時刻
Tfにおいて前記電流Iuが欠相消滅すると前記端子電圧Vc
は時間Ts経過後零電位0Vに達しこの時点で次段電圧比較
器11aは欠相発生を示す出力信号を発する。すなわち前
記時間Tsは前記時限継電回路の設定時間を与えるもので
あり、時限コンデンサ9aの値Cと時限抵抗10aの値Rと
によりRs=0.693RCで与えられる。因に前記端子電圧Vc
の充電時定数はRCである。In the embodiment of the present invention, the direct current Idc is input to the operational amplifier 6 and is reduced to 1/2 in the amplifier 6 Idc.
It is output as / 2. The current value Idc / 2 serves as a reference value for comparison calculation with the three-phase AC output current detection values Iu, Iv, and Iw, and when there is no open phase abnormality in each phase of the three-phase AC output of the inverter 20. Is set as a value through which each of the currents Iu, Iv, and Iw necessarily passes in the time variation. The above size comparison operation of both AC and DC current is
According to the current Iu, Iv and Iw current comparator 8a, respectively
This is done in 8b and 8c. For example, regarding the U-phase current, when the current Iu becomes smaller than the reference value Idc / 2, the current comparator 8a outputs an output signal and the terminal voltage Vc of the next-stage time-limit capacitor 9a goes from the negative potential V − to the positive potential V + . When the current Iu becomes larger than the reference value Idc / 2, the current comparator 8
a is the terminal voltage Vc timed capacitor 9a inverts the output negative potential V - is reset to. When the U-phase output circuit is normal, the charging and resetting operations of the terminal voltage Vc are repeated for each cycle of the current Iu and the value of the voltage Vc does not reach the zero potential 0V. Above voltage Vc and current Iu
Fig. 2 shows the fluctuation pattern of. In Figure 2, if the time
When the current Iu disappears at Tf, the terminal voltage Vc
Reaches the zero potential 0V after the lapse of time Ts, at which point the next-stage voltage comparator 11a outputs an output signal indicating the occurrence of a phase loss. That is, the time Ts gives the set time of the time relay circuit, and is given by Rs = 0.693RC by the value C of the time capacitor 9a and the value R of the time resistor 10a. Because of the above terminal voltage Vc
The charging time constant of is RC.
第3図は第2図に示す周波数fのU相電流Iu(f)とそ
の1/2の周波数をもつ電流 とに対する欠相検出動作模様を併記したものであり、該
両電流が正常な場合には前記端子電圧Vcの充電及び放電
動作周期は前記電流Iu(f)及び に関しそれぞれT0及びT2となる。また前記端子電圧Vcが
電圧比較器11aの動作信号電位0Vに達する時間T1は前記
時間T2より短くT0より長くなる。従って前記電流 に関してはその正常動作時にも電圧比較器11aによる欠
相信号発生の不都合が生じることになる。これを避ける
ために前記時限継電回路の設定時間Tsは前記インバータ
20の最低運転周波数での電流波形における前記T2相当時
間に対し適当な余裕をもったより長い時間として決定さ
れる。該設定時間Tsは前記の他相電流Iv及びIwに関して
もそれぞれの欠相確認用時間として共通に用いられ、そ
れぞれの欠相確認演算結果はU相電流Iuの場合と同様に
してそれぞれ電圧比較器11b及び11cから出力され、電圧
比較器11aの出力信号と共に論理和素子(OR素子)12に
対する入力信号となる。該OR素子12の出力信号は、前記
インバータ20の規定最低運転周波数以上において出力信
号を発する周波数リミッタ7の出力信号と共に論理積素
子(AND素子)13に入力され、該両信号が同時に入力さ
れたこれを条件に該AND素子は出力信号Sを発する。従
って該信号Sは前記時限継電回路の設定時間Tsによる時
間的確認と周波数リミッタ7による周波数確認との二者
による制約を受けその信頼性を高めたものであり、前記
インバータ20の運転週波数が規定値以上にある状態で該
インバータ20の三相交流出力相のいづれかに欠相異常が
発生した場合に出力される欠相検出信号である。Fig. 3 shows the U-phase current Iu (f) of frequency f shown in Fig. 2 and the current having half the frequency When the both currents are normal, the charging and discharging operation cycle of the terminal voltage Vc is the current Iu (f) and Are T0 and T2, respectively. Further, the time T1 when the terminal voltage Vc reaches the operation signal potential 0V of the voltage comparator 11a is shorter than the time T2 and longer than T0. Therefore the current With respect to the above, the inconvenience of the open phase signal generation by the voltage comparator 11a occurs even during the normal operation. In order to avoid this, the set time Ts of the time relay circuit is set to the inverter
It is determined as a longer time with an appropriate margin for the time corresponding to T2 in the current waveform at the lowest operating frequency of 20. The set time Ts is commonly used as the open phase confirmation time for each of the other phase currents Iv and Iw, and each open phase confirmation calculation result is the same as in the case of the U phase current Iu. It is output from 11b and 11c, and becomes an input signal to the logical sum element (OR element) 12 together with the output signal of the voltage comparator 11a. The output signal of the OR element 12 is input to the AND element 13 together with the output signal of the frequency limiter 7 which outputs an output signal at the specified minimum operating frequency of the inverter 20 or more, and both signals are simultaneously input. Under this condition, the AND element emits the output signal S. Therefore, the signal S is enhanced in its reliability under the restriction of two factors, that is, the time confirmation by the set time Ts of the time relay circuit and the frequency confirmation by the frequency limiter 7, and the operating frequency of the inverter 20 is increased. Is a phase loss detection signal that is output when a phase loss abnormality occurs in any of the three-phase AC output phases of the inverter 20 in a state where is above a specified value.
上記のようにこの発明はインバータの交流出力各相の欠
相検出を該交流各相電流それぞれの大きさとその継続時
間による直接判定により行なうために、従来手段に比し
て回路構成の単純化と簡素化とを計っており原理的に三
相を含む多相交流回路に一般的に適用できると共に出力
交流電流の瞬断等に対する誤検出を回避し得るように信
頼性の向上を計ったものである。As described above, according to the present invention, the open phase detection of each phase of the AC output of the inverter is performed by the direct judgment based on the magnitude of each AC phase current and the duration thereof. In principle, it can be generally applied to a multi-phase AC circuit including three phases and has improved reliability so as to avoid erroneous detection due to momentary interruption of the output AC current. is there.
第1図はこの発明の実施例を示す回路図、第2図は第1
図に対応してU相電流欠相時を例とする検出動作波形
図、第3図は第2図に対してインバータ出力周波数が1/
2に低下した場合を併記した検出動作波形図、第4図の
(a)は三相交流出力電流が各相共に正常な場合の各相
電流波形図、第4図の(b)は前記(a)図においてW
相欠相時のU相及びV相電流の波形図である。 1……直流電源、2……トランジスタ、3……転流ダイ
オード、4……直流変流器、5……出力交流変流回路、
5a.5b.5c……交流変流器、6……演算増巾器、7……周
波数リミッタ、8a.8b.8c……電流比較器、9a.9b.9c……
時限コンデンサ、10a.10b.10c……時限抵抗、11a.11b.1
1c……電圧比較器、12……OR素子、13……AND素子、20
……インバータ、21……欠相演算回路、22……インバー
タ負荷、S……インバータ欠相信号。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
Corresponding to the figure, the detection operation waveform diagram when the U-phase current is out of phase is shown in FIG.
Fig. 4 (a) shows the waveform of each phase current when the three-phase AC output current is normal for each phase, and Fig. 4 (b) shows the above ( a) W in the figure
It is a wave form diagram of U-phase and V-phase current at the time of phase loss. 1 ... DC power supply, 2 ... Transistor, 3 ... Commutation diode, 4 ... DC current transformer, 5 ... Output AC current transformer circuit,
5a.5b.5c …… AC current transformer, 6 …… Comparison amplifier, 7 …… Frequency limiter, 8a.8b.8c …… Current comparator, 9a.9b.9c ……
Timed capacitor, 10a.10b.10c …… Timed resistor, 11a.11b.1
1c …… Voltage comparator, 12 …… OR element, 13 …… AND element, 20
...... Inverter, 21 …… Open phase calculation circuit, 22 …… Inverter load, S …… Inverter open phase signal.
Claims (1)
流変流器と、該インバータの多相交流出力電流の各相電
流値をそれぞれ検出する複数の交流変流器と、前記直流
変流器の検出電流値を適当な値に減値変成する演算増巾
器と、該演算増巾器の出力値を基準値として前記多相交
流出力電流の各相検出値との大小を判別する複数の電流
比較器と、該比較器出力信号を入力とする複数の時限継
電回路と、該複数の時限継電回路出力信号を入力とする
論理和素子と前記インバータの出力交流周波数が特定値
以上にある場合に出力信号を発する周波数リミッタと、
該リミッタ出力信号と前記論理和素子の出力信号とを入
力とする論理積素子とから成り、前記演算増巾器による
電流基準値よりも前記多相交流出力電流の各相電流検出
値の方が小である期間が前記インバータの最低動作周波
数との関係で決定され且つ前記複数の時限継電回路に共
通の値として設定される設定時間よりも長くなった場合
には前記インバータの出力欠相状態として欠相信号を発
することを特徴とするインバータの欠相検出回路。1. A DC current transformer for detecting a DC input current value of an inverter, a plurality of AC current transformers for detecting each phase current value of a multi-phase AC output current of the inverter, and the DC current transformer. Of the multi-phase alternating current output current and the detected value of the multi-phase AC output current is determined as a reference value, and a plurality of pluralities for discriminating the magnitude between the detected value of each phase of the multi-phase alternating current output current. A current comparator, a plurality of time-relay circuits that receive the comparator output signals, a logical sum element that receives the plurality of time-relay circuit output signals, and the output AC frequency of the inverter are above a specific value. A frequency limiter that emits an output signal in some cases,
The limiter output signal and the output signal of the logical sum element are formed as a logical product element, and the detected current value of each phase of the multiphase alternating current output current is more than the current reference value by the operational amplifier. If the period that is small is determined in relation to the minimum operating frequency of the inverter and is longer than the set time set as a value common to the plurality of time relay circuits, the output phase failure state of the inverter An open-phase detection circuit for an inverter, which outputs an open-phase signal as
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61239750A JPH071978B2 (en) | 1986-10-08 | 1986-10-08 | Inverter open phase detection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61239750A JPH071978B2 (en) | 1986-10-08 | 1986-10-08 | Inverter open phase detection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6395813A JPS6395813A (en) | 1988-04-26 |
JPH071978B2 true JPH071978B2 (en) | 1995-01-11 |
Family
ID=17049370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61239750A Expired - Lifetime JPH071978B2 (en) | 1986-10-08 | 1986-10-08 | Inverter open phase detection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH071978B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004040921A (en) * | 2002-07-04 | 2004-02-05 | Meidensha Corp | Control method for electric vehicle |
JP4697579B2 (en) * | 2004-12-07 | 2011-06-08 | 株式会社安川電機 | Power converter and phase loss detection method |
JP7043352B2 (en) * | 2018-06-14 | 2022-03-29 | キヤノン電子管デバイス株式会社 | Power supply and rotating anode X-ray tube device |
-
1986
- 1986-10-08 JP JP61239750A patent/JPH071978B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6395813A (en) | 1988-04-26 |
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