JPH0581860A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To perform a stable read operation without delaying a read speed even when a power voltage is dropped. CONSTITUTION:The device is provided with a reference potential generating circuit 3 for generating a reference potential interlocking with a change of the power source, and a charge drawing transistor 4 whose gate receives an output of the reference potential generating circuit is connected to a read data line couple RI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which read speed is increased and malfunction is prevented.

[0002]

2. Description of the Related Art FIG. 5 is a diagram schematically showing a structure of a main part of a conventional semiconductor memory device having a read data line and a write data line separated from each other. In the figure, a pair of write data line pair WI, / WI and a pair of bit line BL, / BL for transmitting only signals from the memory cell MC, the sense amplifier S / A, and the data write circuit are provided on the bit lines BL, / BL. The n-channel transistors Q7 and Q8 of the drive unit 1 of the current mirror differential amplifier which receives the minute potential difference generated at the gate and amplifies it are connected. Further, apart from the write data line pair WI, / WI, a pair of read data line pair RI, / RI for transmitting only read data is provided, and the RI, / RI is provided with an equalizing means (not shown). ing. The current mirror differential amplifier has the n-channel transistors Q5 to Q5.
A driving section 1 made up of Q8 and a p-channel transistor Q for detecting and amplifying a signal potential on the bit line pair BL, / BL.
1 to Q4, the n-channel transistors Q5 and Q6 receive a signal from a column decoder (not shown) at their gates, and the current mirror differential amplifier is activated by this signal. .. And
The potential difference between the bit line pair BL, / BL is amplified by the current mirror differential amplifier and output nodes NO1, NO2.
After further outputting, it is input to the amplifying means (not shown) in the next stage.

Next, the read operation of the semiconductor memory device shown in FIG. 5 will be described with reference to the signal waveform diagram of FIG. Before time t ₁ , the read data line pair RI, / RI, that is, the output nodes NO1, NO2 are stable at a predetermined precharge potential. _Assuming that the power supply voltage V _CC and the threshold voltage of the p-channel transistor are V _thp , the precharge potential is higher than V _CC by the threshold voltage V of the p-channel transistor.
_The potential becomes V _CC − | V _thp | which is lower by the absolute value of _thp . Then, in this state, in response to an address signal from the outside, 1
The word line WL of the book is selected, the information of the memory cell MC is read to the bit line BL, and a minute potential difference is generated between the bit lines BL and / BL.

Next, at time t ₁ , the column selection signal Yi changes from "L" level to "H" in response to the external address.
When the voltage rises to the level, the n-channel transistors Q5 and Q6 are turned on to activate the current mirror differential amplifier including the transistors Q1 to Q8, the read data line / RI is discharged toward the ground potential, and the read data line RI is It is pulled toward the power supply voltage V _CC . Then, the potentials of the read data line pair RI, / RI are transmitted to the input section of the amplifying means of the next stage via the respective output nodes NO2, NO1. Next, at time t ₃ , the column selection signal Y
When i changes from the "H" level to the "L" level, the current mirror differential amplifier becomes inactive, and the read data line pair RI, / RI, that is, the nodes NO1, NO.
2 is equalized and has a predetermined precharge potential V _CC
− | V _thp | is restored.

[0005] Then, the above one cycle (cycle 1) is finished, when moved to the next cycle (cycle 2), i.e., at time t _4, the power supply voltage drops to V _CC 'from V _CC, The precharge potential is the read data line pair RI,
/ RI, that is, the potentials of the nodes NO1 and NO2 do not have a path for extracting the accumulated charge, so V _CC − | V _thp |
From V _CC ′ − | V _thp | to V _CC − | V _thp
| Remains unchanged Then, before time t ₅ , the word line rises from the “L” level to the “H” level, the information of the memory cell MC is read to the bit line BL, and a minute potential difference occurs between the bit line pair BL, / BL. Then, at time t ₅ , the column selection signal Yi rises to the “H” level, the n-channel transistors Q5 and Q6 are turned on, and the current mirror differential amplifier is activated, the minute potential difference between the bit lines BL and / BL becomes small. Nodes NO2 and NO
It is amplified to 1 and transmitted to the amplifying means of the next stage as in the case of cycle 1. Then, at time t ₇ , the column selection signal Yi falls from the “H” level to the “L” level, the transistors Q5 and Q6 are turned off, and the current mirror differential amplifier shifts to the inactive state.
The read data line pair RI, / RI is restored to a predetermined precharge level while being equalized.

Here, assuming that the "L" level of the node NO1 at which the sensitivity of the amplifying means is sufficiently good is, for example, 1/2 of the power supply voltage, in the cycle 1 before the power supply voltage drop, in the current mirror differential amplifier. Is activated (time t ₁ ), the potential of the node NO 1 is stable potential V _CC − | V _thp.
| From 1 / 2V reached _{the CC} (time t ₂₎ time to take [Delta] T, in the above cycle 2 after the power supply voltage drops to V _CC 'from V _CC, similarly activated by the current mirror differential amplifier It takes ΔT ′ from (time t ₅ ) until the potential of the node NO1 reaches stable potential V _CC − | V _thp | to _½ V _CC ′ (time t ₆ ). That is, in cycle 2 after the power supply voltage has dropped, ΔV−Δ from cycle 1
If _{V '(= 1/2 (V CC} -V CC')) but not pulled to the ground potential, can not be the next stage amplifying means to obtain a sufficient sensitivity, furthermore, with the drop in the power supply voltage, the current Since the driving force of the mirror differential amplifier declines, the response speed ΔT ′ in cycle 2 becomes slower than the response speed ΔT in cycle 1.

[0007]

As described above, in the conventional semiconductor memory device in which the read data line and the write data line are separately formed, when a negative bump occurs in the power supply voltage, the read data line pair RI, The precharge level of / RI does not drop following it, and a potential level higher than the power supply voltage remains. Therefore, when the current mirror differential amplifier is activated and the potential of the read data line is pulled toward the ground potential, the read data line pair RI, / R
There is a problem that the time required for the potential of I to reach a predetermined potential level for the amplification means in the next stage to exhibit sufficient sensitivity becomes long.

The present invention has been made to solve the above-mentioned problems, and when the power supply voltage drops, the precharge potential of the read data line pair also drops following the drop in the power supply voltage, and the read speed is increased. An object of the present invention is to obtain a semiconductor memory device in which malfunction is prevented.

[0009]

A semiconductor memory device according to the present invention is provided with a reference potential generating circuit for generating a reference potential in association with a change in a power supply voltage, and an output from the reference potential generating circuit is read out to a data line. The gates of a pair of transistors provided above the pair form a path for extracting charges to the read data line pair.

[0010]

In the semiconductor memory device according to the present invention,
When the power supply voltage V _CC drops, an output signal output from the reference potential generating circuit in conjunction with this is read by the gates of the transistors provided on the respective data lines of the data line pair, and as a result, the transistors are turned on. Then, a conduction path is formed on the read data line pair to draw out charges, and the potential of the read data line is lowered to an appropriate precharge potential.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram schematically showing a configuration of a main part of a semiconductor memory device according to an embodiment of the present invention, and the same reference numerals as those in FIG. 5 denote the same or corresponding parts.

Here, the semiconductor memory device of this embodiment is similar to the conventional semiconductor memory device shown in FIG.
L is a bit line pair, and a pair of write data line pair WI, / for transmitting only signals from the memory cell MC, the sense amplifier S / A, and a data write circuit (not shown) to the bit line pair BL, / BL. WI and bit line pair BL, / BL
The n-channel transistors Q7 and Q8 of the drive unit 1 of the current mirror differential amplifier which receives the minute potential difference generated at the gate and amplifies it are connected. Further, in addition to the write data line pair WI, / WI, a pair of read data line pair RI, / RI for transmitting only read data is provided, and not shown on the read data line pair RI, / RI. Equalizing means is provided. The current mirror differential amplifier for detecting and amplifying the signal potential on the bit line pair BL, / BL is a load unit 2 including p-channel transistors Q1 to Q4 and a driving unit 1 including n-channel transistors Q5 to Q8. Composed of and. still,
The n-channel transistors Q5 and Q6 are switching transistors which receive a signal from a column decoder (not shown) at their gates and activate the current mirror differential amplifier. Further, in the current mirror differential amplifier, the bit line pair BL, / After the potential difference of BL is amplified, it is output from the output nodes NO1 and NO2 and is connected to the input of the amplifying means (not shown) in the next stage.

On the other hand, p-channel transistors Q9 and Q1
0, a resistive element R1 having a resistance value r ₁ is configured the reference potential generating circuit 3, the p-channel transistor Q9
Has a source electrode connected to the power supply voltage V _CC terminal, a drain electrode and a gate electrode connected to the node NO3, and the p
The source electrode of the channel transistor Q10 is the node NO
3, the gate electrode and drain electrode are node NO4
And one end of the resistance element R1 is connected to the node NO4.
, And the other end is grounded. Further, the node NO4 is connected to the respective gate electrodes of the p-channel transistors Q11 and Q12 for charge extraction, and the Q
The source electrodes of the p-channel transistors Q11 and Q12 are connected to the read data lines RI and / RI, that is, the nodes NO1 and NO2, respectively, and the drain electrodes are both grounded.

Next, the outline of the operation of the above apparatus will be described.
In the reference potential generation circuit 3, the resistance value r ₁ of the resistance element R1
The transistors Q9, when set to be very large value compared with the ON resistance of Q10, absolute value of only low V _CC of the threshold voltage of the p-channel transistor than the power supply voltage V _CC to the node NO3 (V _thp) A voltage of − | V _thp | is output. The node NO4 only the absolute value of the threshold voltage (V _{th p)} of the p-channel transistor from voltage output to the node NO3 low V _CC -2 | V _thp |
Is output. At this time, if the resistance value r ₁ is made sufficiently large, the current flowing through the reference voltage generating circuit 3 becomes almost zero. When the potentials of the nodes NO1 and NO2 are higher than the potential of the node _{NO4 by} the absolute value of the threshold voltage V _thp of the p-channel transistor, the p-channel transistors Q11 and Q12 are turned on,
There is a current path. That is, when the power supply voltage V _CC drops to V _CC ′ for some reason, the nodes NO1 and N
If the potential of O2 is higher than V _CC ′ − | V _thp |, the p-channel transistors Q11 and Q12 are turned on and the node NO
The potentials of 1 and NO2 are lowered to V _CC ′ − | V _thp |. Then, if the potentials of the nodes NO1 and NO2 _{drop to} the potential of V _CC ′ − | V _thp |, the node Q1
1, 1 and Q12 are turned off, and no more current flows.

The operation of the semiconductor memory device will be described in detail below with reference to the signal waveform diagram of FIG. First, before the time t ₁ , the read data line RI (node NO1),
/ RI (node NO2) is the power supply voltage V
It is stable at a potential V _CC − | V _thp | which is lower than _CC by the absolute value of the threshold voltage V _thp of the p-channel transistor. Then, in this state, one word line is selected in response to an address signal from the outside, the information of the memory cell MC is read to the bit line BL, and the bit line pair BL, / BL.
A minute potential difference occurs between them. After that, in cycle 1 (time t ₃
From t to t ₄ ) the read operation is the same as the conventional one.

Next, the process moves from cycle 1 to cycle 2,
When the power supply voltage drops from V _CC to V _CC ′ at time t ₄ , the node N which is the output of the reference potential generating circuit 3 is interlocked with it.
The potential of O4 also drops, and the potential becomes V _CC ′ −2 | V _thp |. In other words, no matter how the power supply voltage changes, the node NO4 outputs a voltage that is two steps lower than the power supply voltage by the absolute value of the threshold voltage V _thp of the p-channel transistor. At this time, the nodes NO1 and NO2 of the potential before the power supply voltage drops below the power supply voltage V _CC | V _thp | amount corresponding lower V _CC
-| V _thp |, the p-channel transistor Q1
1, the Q12, the gate potential V _CC '-2 | V _thp | respect to the source potential V _CC - | V _thp | is V _CC -V _CC' + | V
_thp |, that is, the source potential is higher than the gate potential by | V _thp | or more, so that the p-channel transistors Q11 and Q12 become conductive, and the nodes NO1 and N1.
The potential level of O2 is lowered to the level of V _CC ′ − | V _thp |.

Next, at time t ₅ , when the voltage rises from the "L" level to the "H" level in response to the column selection signal Yi from the external address, the n-channel transistors Q5 and Q5.
6 is turned on, the current mirror differential amplifier composed of the transistors Q1 to Q8 is activated, and the read data line / RI is activated.
(Node NO2) is pulled toward the ground potential, while
The read data line RI (node NO1) is pulled toward the power supply voltage V _CC ′. Here, since the stable potentials of the output nodes NO1 and NO2 also drop in association with the drop of the power supply voltage, the output node NO1 has a sufficiently good level of sensitivity of the amplifying means at the next stage (for example, as compared with the conventional case). Similarly, time t at which the potential level reaches 1/2 of the power supply voltage)
_The time required to reach ₆ is Δt 'in cycle 1 before the power supply voltage drop.
In this case, the response time Δt becomes equal to the response time Δt, the delay of the response speed due to the drop of the power supply voltage as in the related art is improved, and a stable read operation is realized. Then, at time t ₇ , the column selection signal Yi falls from the “H” level to the “L”, the transistors Q5 and Q6 are turned off, and the read data line pair RI, / RI (that is, the node NO).
1, NO2) returns to a predetermined stable potential V _CC ′ − | V _thp |.

In the semiconductor memory device according to this embodiment, for example, one cycle of the read operation is completed,
When the power supply voltage drops V _CC 'from V _cc, the node NO in conjunction with this is the output of the reference voltage generating circuit 3
4 is the threshold voltage V of the p-channel transistor
V _CC ′ −2 | V _{th p} by descending by two steps of the absolute value of _thp
|, The gate potentials of the p-channel transistors Q11 and Q12 are V _CC ′ −2 | V _thp |, and the source potentials _thereof are V _cc lower than the power source voltage V _cc before the power source voltage drop by V _cc |
− | V _thp |, and as a result, the source potential becomes higher than the gate potential by V _cc −V _CC ′ + | V _thp |, the p-channel transistors Q11 and Q12 become conductive, and the potentials of the nodes NO1 and NO2 are increased. The level is also lowered to the level of V _CC ′ − | V _thp |, whereby the time required to reach the potential level sufficient for the sensitivity of the amplifying means in the next stage is shortened, and the response due to the drop in the power supply voltage is reduced. It is possible to suppress the delay in speed.

FIG. 3 is a diagram schematically showing a structure of a main part of a semiconductor memory device according to a second embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same or corresponding parts,
In the semiconductor memory device of this embodiment, the semiconductor memory device shown in FIG. 1 has a gate for receiving a reference potential (constant voltage) immediately below the output nodes NO1, NO2 on the read data line pair RI, / RI. The n-channel transistors Q13 and Q14 are provided in the read data line pair RI and / RI, and further, with respect to the read data line pair RI and / RI, charge extraction transistors Q20 and Q21 at the time of generation of a negative bump of the power supply voltage and the transistors. Q20, Q21
The reference voltage generating circuit 3'to which the respective gates are connected is provided.

In the semiconductor integrated circuit device according to the present embodiment as described above, the transfer n-channel transistors Q13 and Q14 are provided on the read data lines RI and / RI of the semiconductor memory device shown in FIG. Since the reference voltage generation circuit 3'is connected to the lines RI, / RI via the charge extraction transistors Q20, Q21, the transfer n-channel transistors Q13, Q14 (Vref in the figure is the n-channel transistors Q13, Q14). Threshold voltage) makes the load part 2 of the current mirror differential amplifier lighter, and the output node N
The response speeds of O1 and NO2 are further increased, and the logical amplitudes of the nodes NOA and NOB to which a large capacity is added on the side of the drive unit 1 of the current mirror differential amplifier are limited, so that low power consumption can be realized. ..

FIG. 4 is a diagram showing a circuit configuration of a reference potential generating circuit of a semiconductor memory device according to a third embodiment of the present invention. In FIG. 4, a p-channel transistor Q15, n is provided between a power supply V _CC and ground. Channel transistor Q16, p
Reference potential generating means constituted by connecting in parallel a channel transistor Q17 and a resistance component R ₂ having a resistance value r ₂ ;
An output stage constituted by connecting a p-channel transistor Q18 and an n-channel transistor Q19 in parallel is formed, and the gate of the p-channel transistor Q15 of the reference potential generating means and the n-channel transistor Q1 are formed.
The node to which the gate of 6 is connected is connected to the gate of p-channel transistor Q18 via node NO5 which connects the source of p-channel transistor Q15 and the drain of n-channel transistor Q16, and the gate of p-channel transistor Q17 is p-channel. Transistor Q1
7 is connected to the gate of n-channel transistor Q19 via the node N07 connected to the source and the resistance component R ₂ of the node NO8 connecting the source and drain of the p-channel transistor Q18, n-channel transistor Q19 is not shown Charge extraction transistor Q1
2, connected to the gate of Q13.

In the reference potential generating circuit of the present embodiment, the node _NO5 between the p-channel transistor Q15 and the n-channel transistor Q16 has a potential of V _{CC -│V thp} │ and the n-channel transistor Q16 and the p-channel transistor Q16. The node NO6 with Q17 has V _CC − | V _thp
The potential of | -V _thn is V in the node NO7 between the p-channel transistor Q17 and the resistance component R ₂ having the resistance value r _{2.
CC - | V thp | -V th} n - | V thp | = V CC -2 | V
The potential of _thp │−V _thn is the p-channel transistor Q1.
8 and n-channel transistor node Q19 NO8 the V _CC - | V _thp | the potential of -V _thn are output, as in the above embodiments, completed one cycle of the read operation, the power supply voltage V If it drops from _CC to V _CC ',
The gate potential of the charge extraction transistor is higher than the source potential by V _CC -V _CC '+ | V _thp | to be in the conductive state, and as a result, the delay of the response speed due to the drop of the power supply voltage is suppressed. You can Further, by increasing the size of the n-channel transistor Q16 and the p-channel transistor Q17 forming the output stage and increasing the driving capability, the reference potential with low impedance can be output.

[0023]

As described above, according to the present invention, the reference potential generating circuit whose output voltage changes in accordance with the change of the power supply voltage and the output from the reference potential generating circuit connected to the read data line pair. Since the charge extraction transistor that receives the voltage at the gate is provided, when a negative bump occurs in the power supply voltage, the charge extraction transistor is turned on to form a path for extracting the charge, and the read data line pair is also formed. The power supply voltage drops to an appropriate stable potential, and as a result, there is an effect that the read operation is speeded up and a stable read operation can be performed.

Further, according to the present invention, in addition to the reference potential generating circuit and the charge extracting transistor, the transfer transistor connecting the drive section and the load section of the current mirror differential amplifier on the read data line pair. As described above, the read data line pair drops to an appropriate stable potential after the power supply voltage drop in the same manner as above, and the logical amplitude of the node of the read data line connected to the drive unit of the current mirror differential amplifier is changed. Since the data can be limited, the read operation can be speeded up and the power consumption can be reduced, and as a result, there is an effect that a more stable read operation can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a main part of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing a read operation of the semiconductor memory device according to the embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a main part of a semiconductor memory device according to another embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a reference potential generating circuit of a semiconductor memory device according to another embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a main part of a conventional semiconductor memory device.

FIG. 6 is a signal waveform diagram showing a read operation of a conventional semiconductor memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Current mirror differential amplifier drive unit 2 Current mirror differential amplifier load unit 3 Reference potential generation circuit 3'Reference potential generation circuit 4 Charge extraction transistor group 4'Charge extraction transistor group 5 Transfer transistor group Q1 to Q4 , Q9 to Q12, Q15, Q17, Q18,
Q20, Q21 P-channel transistor Q5-Q8 Q13, Q14, Q19 N-channel transistor NO1, NO2, NO3, NO4, NO5, NO6, N
O7, NO8 node BL, / BL bit line WI, / WI write data line RI, / RI read data line WL word line NOA, NOB node

[Procedure amendment]

[Submission date] January 28, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art FIG. 5 is a diagram schematically showing a structure of a main part of a conventional semiconductor memory device having a read data line and a write data line separated from each other. In Figure, the bit line pair BL, / memory cell MC in the BL, the sense amplifier S / A, and the write data line pair of a pair of transmitting only a signal from the data write circuit WI, / WI and the bit line pair BL, / N of the drive unit 1 of the current mirror differential amplifier which receives a minute potential difference generated in BL at its gate and amplifies it
Channel transistors Q7 and Q8 are connected. Further, apart from the write data line pair WI, / WI, a pair of read data line pair RI, / RI for transmitting only read data is provided, and the RI, / RI is provided with an equalizing means (not shown). ing. The current mirror differential amplifier has the n-channel transistors Q5 to Q5.
A driving section 1 made up of Q8 and a p-channel transistor Q for detecting and amplifying a signal potential on the bit line pair BL, / BL.
1 to Q4, the n-channel transistors Q5 and Q6 receive a signal from a column decoder (not shown) at their gates, and the current mirror differential amplifier is activated by this signal. .. And
The potential difference between the bit line pair BL, / BL is amplified by the current mirror differential amplifier and output nodes NO1, NO2.
After further outputting, it is input to the amplifying means (not shown) in the next stage.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

Here, the semiconductor memory device of this embodiment is similar to the conventional semiconductor memory device shown in FIG.
L is a bit line pair, and a pair of write data line pair WI, / for transmitting only signals from the memory cell MC, the sense amplifier S / A, and a data write circuit (not shown) to the bit line pair BL, / BL. WI and bit line pair BL, / BL
The n-channel transistors Q7 and Q8 of the drive unit 1 of the current mirror differential amplifier which receives the minute potential difference generated at the gate and amplifies it are connected. Further, in addition to the write data line pair WI, / WI, a pair of read data line pair RI, / RI for transmitting only read data is provided, and not shown on the read data line pair RI, / RI. Equalizing means is provided. The current mirror differential amplifier for detecting and amplifying the signal potential on the bit line pair BL, / BL is a load unit 2 including p-channel transistors Q1 to Q4 and a driving unit 1 including n-channel transistors Q5 to Q8. Composed of and. still,
The n-channel transistors Q5 and Q6 are switching transistors which receive a signal from a column decoder (not shown) at their gates and activate the current mirror differential amplifier. Further, in the current mirror differential amplifier, the bit line pair BL, / After the potential difference of BL is amplified, it is output from the output nodes NO 2 and NO 1 and is connected to the input of the amplifying means (not shown) in the next stage.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

On the other hand, p-channel transistors Q9 and Q1
0, a resistive element R1 having a resistance value r ₁ is configured the reference potential generating circuit 3, the p-channel transistor Q9
Has a source electrode connected to the power supply voltage V _CC terminal, a drain electrode and a gate electrode connected to the node NO3, and the p
The source electrode of the channel transistor Q10 is the node NO
3, the gate electrode and drain electrode are node NO4
And one end of the resistance element R1 is connected to the node NO4.
, And the other end is grounded. And further, the node NO4 is connected to the gate electrode of the p-channel transistors Q11, Q12 of the charge withdrawal, the p
The source electrodes of the channel transistors Q11 and Q12 are respectively connected to the read data lines RI and / RI, that is, the node N.
They are connected to O1 and NO2, respectively, and their drain electrodes are both grounded.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

The operation of the semiconductor memory device will be described in more detail below with reference to the signal waveform diagram of FIG. First, time t
Before ₁ , read data line RI (node NO1), /
RI (node NO2) is the same as the conventional power supply voltage V _CC.
It is stable at the potential V _CC − | V _thp | which is lower by the absolute value of the threshold voltage V _thp of the p-channel transistor.
Then, in this state, one word line is selected in response to an external address signal, the information of the memory cell MC is read to the bit line BL, and a minute potential difference is generated between the bit line pair BL, / BL. .. After that, the read operation in cycle 1 (from time t ₃ to t ₄ ) is the same as the conventional one.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0019

[Correction method] Change

[Correction content]

FIG. 3 is a diagram schematically showing a structure of a main part of a semiconductor memory device according to a second embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same or corresponding parts,
In the semiconductor memory device of this embodiment, the semiconductor memory device shown in FIG. 1 has a gate for receiving a reference potential (constant voltage) immediately below the output nodes NO1, NO2 on the read data line pair RI, / RI. n, channel transistors Q13, reads Q14 data line pairs RI, provided / RI, further, the read data line pair RI, relative / RI,
A transistor Q20, Q21 for extracting electric charge when a negative bump of the power supply voltage is generated and a reference voltage generating circuit 3'connected to the respective gates of the transistors Q20, Q21 are provided.

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

[0020] In the semiconductor integrated circuit device according to the present embodiment, the read data line RI of the semiconductor memory device shown in FIG. 1, / on the RI, along with providing the n for transfer, channel transistors Q13, Q14, said read data lines RI, / RI in through the charge pull transistors Q20, Q21 for connecting the reference voltage generating circuit 3 ', the transfer for n, channel transistor Q
13, Q14 (Vref is a certain intermediate potential ) makes the load section 2 of the current mirror differential amplifier lighter, the response of the output nodes NO1 and NO2 is made faster, and the current mirror differential amplifier has a large drive section 1 side. The logic amplitude of the nodes NOA and NOB to which the capacitance is added is limited, and low power consumption can be realized.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

In the reference potential generating circuit of the present embodiment, the node _NO5 between the p-channel transistor Q15 and the n-channel transistor Q16 has a potential of V _{CC -│V thp} │ and the n-channel transistor Q16 and the p-channel transistor Q16. The node NO6 with Q17 has V _CC − | V _thp
The potential of | -V _thn is V in the node NO7 between the p-channel transistor Q17 and the resistance component R ₂ having the resistance value r _{2.
CC - | V thp | -V th} n - | V thp | = V CC -2 | V
The potential of _thp │−V _thn is the p-channel transistor Q1.
8 and the node NO8 of the n-channel transistor Q19 output the potential of V _{CC −2} | V _thp | , respectively.
Similar to the above embodiment, one cycle is completed read operation, the power supply voltage V _CC from V _CC 'if you drop, V _CC over V _CC gate potential than the source potential of the charge pull transistor' + It becomes conductive by increasing by | V _thp |, and as a result, it is possible to suppress the delay of the response speed due to the drop of the power supply voltage. In addition, if the size of the n-channel transistor Q16 and the p-channel transistor Q17 forming the output stage is increased to improve the driving capability,
It is possible to output the reference potential with low impedance.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

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[Description of Reference Signs] 1 current mirror differential amplifier drive section 2 current mirror differential amplifier load section 3 reference potential generation circuit 3'reference potential generation circuit 4 charge extraction transistor group 4'charge extraction transistor group 5 for transfer Transistor groups Q1 to Q4, Q9 to Q12, Q15, Q17, Q18,
Q20, Q21 P, channel transistor Q5~Q8 Q13, Q14, Q19 N, channel transistor NO1, NO2, NO3, NO4, NO5, NO6, N
O7, NO8 node BL, / BL bit line WI, / WI write data line RI, / RI read data line WL word line NOA, NOB node

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Claims (2)

[Claims] 1. A plurality of memory cells, a plurality of bit line pairs provided so that one of the memory cells is connected to the memory cell, and a plurality of bit line pairs corresponding to the bit line pairs. A plurality of sense amplifiers that are provided as a set, a write data line pair that transmits write data to the bit line pair selected when writing data, and a read data line pair that transmits read data to the bit line pair selected when reading data. And a current mirror differential amplifier provided corresponding to the read data line pair and the bit line pair and differentially amplifying the potential of the bit line pair as an input signal, A reference potential generating circuit that outputs a reference potential having a voltage value lower than the voltage value of the power source voltage in conjunction with the power source voltage, and a drain that is grounded Subjected to a force to the gate, the semiconductor memory device is characterized by providing a pair of charge pull transistor whose source respectively to the read data line pair is connected. 2. The semiconductor memory device according to claim 1, wherein a transfer transistor that receives at its gate an intermediate potential on a read data line pair connecting the load section and the drive section of the current mirror differential amplifier is used as the read data. A semiconductor memory device provided in line pairs.