JP2869226B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a reading speed is increased and a malfunction is prevented.

[0002]

2. Description of the Related Art FIG. 5 schematically shows a structure of a main part of a conventional semiconductor memory device having a structure in which a read data line and a write data line are separated. In Figure, the bit line pair BL, / memory cell MC in the BL, the sense amplifier S / A, and the write data line pair of a pair of transmitting only a signal from the data write circuit WI, / WI and the bit line pair BL, / The gate of the current mirror differential amplifier amplifies the small potential difference generated in BL at the gate, and amplifies it.
Channel transistors Q7 and Q8 are connected. Further, apart from the write data line pair WI, / WI, a pair of read data line RI, / RI for transmitting only read data is provided, and the RI, / RI is provided with an equalizing means (not shown). ing. The current mirror differential amplifier is connected to the n-channel transistors Q5 to Q5.
A drive unit 1 comprising a transistor Q8 and a p-channel transistor Q for detecting and amplifying a signal potential on a pair of bit lines BL and / BL.
The n-channel transistors Q5 and Q6 receive at their gates a signal from a column decoder (not shown), and the current mirror differential amplifier is activated by this signal. . And
The potential difference between the pair of bit lines BL and / BL is amplified by the current mirror differential amplifier and output nodes NO1 and NO2.
After that, it is input to the amplification means (not shown) at the next stage.

Next, a read operation of the semiconductor memory device shown in FIG. 5 will be described with reference to a signal waveform diagram of FIG. Time t ₁ before the read data line pair RI, / RI, i.e., the output nodes NO1, NO2 is stable at a predetermined precharge potential. _Assuming that the power supply voltage V _CC and the threshold voltage of the p-channel transistor are V _thp , this precharge potential is higher than V _CC by the threshold voltage V p of the p-channel transistor.
_The potential V _CC − | V _thp | becomes lower by the absolute value of _thp . Then, in this state, 1 responds to an external address signal.
One word line WL is selected, the information of the memory cell MC is read out to the bit line BL, and a small potential difference occurs between the bit lines BL and / BL.

[0004] Next, at time t _1, the column selection signal Yi in response to an external address "L" level to "H"
When it rises to the level, n-channel transistors Q5 and Q6 are turned on, the current mirror differential amplifier including transistors Q1 to Q8 is activated, read data line / RI is discharged toward the ground potential, and read data line RI is It is pulled toward the power supply voltage V _CC . Then, the potential of the read data line pair RI, / RI is transmitted to the input section of the next stage amplifying means via the respective output nodes NO2, NO1. Then, the column selection signal Y at time t ₃
When i changes from "H" level to "L" level, the current mirror differential amplifier becomes inactive and the read data line pair RI, / RI, that is, nodes NO1 and NO
2 is a predetermined precharge potential V _CC while being equalized
-| V _thp |

[0005] Then, the above one cycle (cycle 1) is finished, when moved to the next cycle (cycle 2), i.e., at time t _4, the power supply voltage drops to V _CC 'from V _CC, The precharge potential is equal to the read data line pair RI,
/ RI, that is, the potentials of the nodes NO1 and NO2 have no path for extracting the accumulated charge, and therefore, V _CC − | V _thp |
V _CC 'from - | V _thp | to does not drop, V _CC - | V _thp
| Does not change. Then, the time t ₅ before the word line rises to "H" level from the "L" level, data of the memory cell MC is read out to the bit line BL, and the bit line pair BL, small potential difference is generated between the / BL. Then, rising the column selection signal Yi is at the "H" level at time t _5, n-channel transistors Q5, Q6 is turned on, the current mirror differential amplifier is activated, the bit line BL, and the small potential difference between / BL Nodes NO2 and NO
1 and transmitted to the next stage amplifying means in the same manner as in the cycle 1. Then, at time t _7, by falls to the "L" level from the column selection signal Yi is at the "H" level, transistors Q5, Q6 are turned off, the current mirror differential amplifier is shifted to the inactive state,
The read data line pair RI, / RI returns to a predetermined precharge level while being equalized.

Here, assuming that the "L" level of the node NO1 at which the sensitivity of the amplifying means is sufficiently good is, for example, 1/2 of the power supply voltage, in the cycle 1 before the power supply voltage drops, the current mirror differential amplifier is used. Is activated (time t ₁ ), the potential of node NO1 becomes stable potential V _CC − | V _thp
| From 1 / 2V reached _{the CC} (time t ₂₎ time to take [Delta] T, in the above cycle 2 after the power supply voltage drops to V _CC 'from V _CC, similarly activated by the current mirror differential amplifier It takes ΔT ′ from (at time t ₅ ) until the potential of the node NO1 reaches 1/2 V _CC ′ from the stable potential V _CC − | V _thp | (at time t ₆ ). That is, in cycle 2 after the power supply voltage drops, ΔV−Δ
If _{V '(= 1/2 (V CC} -V CC')) but not pulled to the ground potential, can not be the next stage amplifying means to obtain a sufficient sensitivity, furthermore, with the drop in the power supply voltage, the current Since the driving force of the Miller differential amplifier decreases, the response speed ΔT ′ in cycle 2 becomes slower than the response speed ΔT in cycle 1.

[0007]

As described above, in the conventional semiconductor memory device in which the read data line and the write data line are formed separately, when a negative bump occurs in the power supply voltage, the read data line pair RI, The precharge level of / RI does not drop following it, and a potential level higher than the power supply voltage remains. For this reason, when the current mirror differential amplifier is activated and the potential of the read data line is pulled toward the ground potential, the read data line pair RI, / R
There is a problem in that the time required for the potential of I to reach a predetermined potential level for the amplification means at the next stage to exhibit sufficient sensitivity becomes long.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. When the power supply voltage drops, the precharge potential of the read data line pair also drops following the drop of the power supply voltage, thereby increasing the read speed. It is another object of the present invention to obtain a semiconductor memory device in which malfunction is prevented.

[0009]

A semiconductor memory device according to the present invention has a plurality of memory cells and a memory cell for each memory cell.
One of which is connected to the memory cell.
A pair of bit lines and a pair of bit lines of the plurality of bit line pairs.
Multiple sense amplifiers and data write
The write data to the selected bit line pair
Write data line pair selected during data read
Read data that transmits read data from the bit line pair
Data line pair, load section and drive section
Provided corresponding to the data line pair and the bit line pair,
Differentially amplify the potential of the bit line pair as an input signal
Semiconductor memory device with current mirror differential amplifier
Lower than the voltage value of the power supply voltage in conjunction with the power supply voltage.
A reference potential generating circuit for outputting a reference potential having a
Rain grounds and gates the output of the reference potential generator
And the source is connected to each of the read data line pairs.
A pair of charge extraction transistors connected
The current mirror differential amplifier
On the read data line pair that connects the
Transfer receiving a potential corresponding to the intermediate potential at the gate
And a transistor for use .

[0010]

In the semiconductor memory device according to the present invention,
When the power supply voltage V _CC drops, an output signal output from the reference potential generating circuit in conjunction with the read is received by the gates of the transistors provided on the respective data lines of the read data line pair, and as a result, the transistor is turned on. And a path is formed to conduct the charges on the read data line pair, thereby lowering the potential of the read data line to an appropriate precharge potential.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram schematically showing a configuration of a main part of a semiconductor memory device according to one embodiment of the present invention, and the same reference numerals as those in FIG. 5 indicate the same or corresponding parts.

Here, the semiconductor memory device of this embodiment has BL, / B like the conventional semiconductor memory device shown in FIG.
L denotes a bit line pair, and a pair of write data line pairs WI, // which transmit only signals from a memory cell MC, a sense amplifier S / A, and a data write circuit (not shown) to the bit line pairs BL and / BL. WI and bit line pair BL, / BL
The n-channel transistors Q7 and Q8 of the drive unit 1 of the current mirror differential amplifier that receives the small potential difference generated at the gate by the gate and amplifies it are connected. Further, apart from the write data line pair WI, / WI, there is provided a pair of read data line pairs RI, / RI for transmitting only read data, not shown on the read data line pair RI, / RI. Equalizing means is provided. The current mirror differential amplifier for detecting and amplifying the signal potential on the bit line pair BL, / BL includes a load unit 2 including p-channel transistors Q1 to Q4 and a driving unit 1 including n-channel transistors Q5 to Q8. It is composed of still,
The n-channel transistors Q5 and Q6 are switching transistors that receive a signal from a column decoder (not shown) at their gates and activate the current mirror differential amplifier. In the current mirror differential amplifier, the bit line pair BL, / After the potential difference of BL is amplified, it is output from output nodes NO 2 and NO 1 and is connected to the input of an amplifying means (not shown) at the next stage.

On the other hand, p-channel transistors Q9, Q1
0, a resistive element R1 having a resistance value r ₁ is configured the reference potential generating circuit 3, the p-channel transistor Q9
The source electrode is connected to the supply voltage V _CC terminal, a drain electrode and a gate electrode connected to the node NO3, also, the p
The source electrode of channel transistor Q10 is at node NO.
3 and the gate and drain electrodes are connected to node NO4
And one end of the resistance element R1 is connected to a node NO4.
And the other end is grounded. And further, the node NO4 is connected to the gate electrode of the p-channel transistors Q11, Q12 of the charge withdrawal, the p
The source electrodes of the channel transistors Q11 and Q12 are connected to the read data lines RI and / RI, that is, the node N
O1 and NO2 are connected to each other, and the drain electrodes are both grounded.

Next, an outline of the operation of the above device will be described.
The resistance value r ₁ of the resistance element R1 in the reference potential generation circuit 3
The transistors Q9, when set to be very large value compared with the ON resistance of Q10, absolute value of only low V _CC of the threshold voltage of the p-channel transistor than the power supply voltage V _CC to the node NO3 (V _thp) − | V _thp | is output. The node NO4 only the absolute value of the threshold voltage (V _{th p)} of the p-channel transistor from voltage output to the node NO3 low V _CC -2 | V _thp |
Is output. At this time, if the value of the resistance value r ₁ is sufficiently increased, the current flowing in the reference voltage generating circuit 3 becomes almost zero. When the potentials of nodes NO1 and NO2 are higher than the potential of node _{NO4 by} the absolute value of threshold voltage V _thp of the p-channel transistor, p-channel transistors Q11 and Q12 are turned on,
There is a current path. That is, when the power supply voltage V _CC falls to V _CC 'for some reason, the nodes NO1 and N
If the potential of O2 is higher than V _CC '-| V _thp |, p-channel transistors Q11 and Q12 turn on, and node NO
1, the potential of NO2 is reduced to V _CC '-| V _thp |. Then, the node NO1, the potential of NO2 is V _CC '- | V _thp | if Sagare to the potential, the node Q1
1, Q12 is turned off, and no more current flows.

Hereinafter, the operation of the semiconductor memory device will be described in more detail with reference to the signal waveform diagram of FIG. First, time t
_{1 or} earlier, the read data line RI (node NO1),
RI (node NO2) is equal to power supply voltage V _CC as in the prior art.
It is stable at a potential V _CC − | V _thp | lower than the absolute value of the threshold voltage V _thp of the p-channel transistor.
Then, in this state, one word line is selected in response to an externally applied address signal, information of the memory cell MC is read out to the bit line BL, and a minute potential difference is generated between the pair of bit lines BL and / BL. . Thereafter, the read operation cycle 1 (from time t ₃ to t ₄₎ is the same as the conventional.

Next, a transition is made from cycle 1 to cycle 2,
When the power supply voltage drops from V _CC to V _CC 'at time t ₄ , the output of node N
The potential of O4 also drops, and the potential becomes V _CC '-2 | V _thp |. That is, no matter how the power supply voltage changes, a voltage two steps lower than the power supply voltage in absolute value of the threshold voltage V _thp of the p-channel transistor is output to the node NO4. At this time, the nodes NO1 and NO2 of the potential before the power supply voltage drops below the power supply voltage V _CC | V _thp | amount corresponding lower V _CC
− | V _thp |, the p-channel transistor Q1
1, the Q12, the gate potential V _CC '-2 | V _thp | respect to the source potential V _CC - | V _thp | is V _CC -V _CC' + | V
_thp |, that is, the source potential becomes higher than the gate potential by | V _thp | or more, so that the p-channel transistors Q11 and Q12 are turned on, and the nodes NO1 and N1
The O2 potential level of V _CC '- | will be lowered to the level of | V _thp.

[0017] Then, the time t ₅ in response to a column selection signal Yi from the external address rises to "H" level from the "L" level, n-channel transistors Q5, Q
6 is turned on to activate the current mirror differential amplifier including the transistors Q1 to Q8, and the read data line / RI
(Node NO2) is pulled towards ground potential, while
Read data line RI (node NO1) is pulled toward power supply voltage V _CC '. Here, the stable potentials of the output nodes NO1 and NO2 also drop in conjunction with the drop of the power supply voltage, so that the output node NO1 has a sufficiently high level of sensitivity of the amplifying means of the next stage (for example, the conventional one). Similarly, the time t when the voltage reaches the half of the power supply voltage)
The required time Δt 'up to ₆ is cycle 1 before the power supply voltage drops.
, The response time delay due to a drop in power supply voltage as in the prior art is improved, and a stable read operation is realized. By falls to "L" from the column selection signal Yi is at the "H" level at time t _7, transistors Q5, Q6 shifts to the OFF state, the read data line pair RI, / RI (i.e. node NO
1, NO2) is predetermined stable potential V _CC '- | return to | V _thp.

In the semiconductor memory device according to the present embodiment, for example, one cycle of the read operation is completed.
When the power supply voltage drops from V _cc to V _cc ′, the node NO, which is the output of the reference potential generating circuit 3, is interlocked with this.
4 is the threshold voltage V of the p-channel transistor
drop by two steps of the absolute value of _thp and V _CC '-2 | V _{th p}
| Becomes the gate potential of the p-channel transistors Q11, Q12 is V _CC '-2 |, the source potential before the power supply voltage drops below the supply voltage _{V cc | | V thp V thp} | only low V _cc
- | V _thp | becomes, as a result, V source potential than the gate potential _{cc -V CC '+ | V thp} | becomes as high, the p-channel transistors Q11, Q12 is conductive, node NO1, NO2 potential level V _CC '- | V _thp | will be pulled down to the level of, thereby, the time required to reach a sufficient potential level to the sensitivity of the next-stage amplifying means is shortened, response by drop of the power supply voltage Speed delay can be suppressed.

FIG. 3 is a diagram schematically showing a configuration of a main part of a semiconductor memory device according to a second embodiment of the present invention, wherein the same reference numerals as in FIG. 1 denote the same or corresponding parts.
In the semiconductor memory device of this embodiment, a reference potential (constant voltage = V) immediately below the output nodes NO1 and NO2 on the read data line pair RI and / RI is added to the semiconductor memory device shown in FIG.
_ref ) to the gate of the transfer data line pair RI, /
In addition, the transistors Q20 and Q21 and the transistors Q20 and Q21 for extracting charges when a negative bump of the power supply voltage occurs are provided to the output nodes NO1 and NO2 .
Is provided with a reference voltage generating circuit 3 'connected to the respective gates.

[0020] In the semiconductor integrated circuit device according to the present embodiment, the read data line RI of the semiconductor memory device shown in FIG. 1, / on the RI, along with providing the n for transfer, channel transistors Q13, Q14, said read data lines RI, / RI in through the charge pull transistors Q20, Q21 for connecting the reference voltage generating circuit 3 ', the transfer for n, channel transistor Q
13, Q14 (Vref is a certain intermediate potential in the figure), the load 2 of the current mirror differential amplifier is lightened, the response of the output nodes NO1 and NO2 is further speeded up, and the drive unit 1 side of the current mirror differential amplifier is large. The logic amplitude of the nodes NOA and NOB to which the capacitance is added is limited, and low power consumption can be realized.

FIG. 4 is a diagram showing a circuit configuration of a reference potential generating circuit of a semiconductor memory device according to a third embodiment of the present invention. In FIG. 4, p-channel transistors Q15 and n are connected between a power supply _Vcc and ground. Channel transistor Q16, p
And a reference potential onset raw stage resistive component R ₂ having a channel transistors Q17 resistance value r ₂ is constructed by series connection, n
Channel transistor Q18, p is a channel transistor Q19 is formed with series connected is configured by an output stage, respectively, to connect the gates of the n-channel transistor Q16 of the p-channel transistor Q15 of the reference potential onset raw stage The node is a p-channel transistor Q
15 is connected to the gate of n- channel transistor Q18 via node NO5 connecting the drain of n-channel transistor Q16 to the gate of p-channel transistor Q17.
The drain and through the resistance component R ₂ and node N O 7 connected to is connected to the gate of the p-channel transistor Q19, the charge node NO8 connecting the source of the n-channel transistor Q18, p-channel transistor Q19 is not shown pull transistor Q1 1, Q1 2
Connected to the gate.

[0022] In the reference voltage generating circuit to the present embodiment, p-channel transistor Q15 and the node NO5 the n-channel transistor Q16 V _CC - | V _thp | potentials, n-channel transistor Q16 and a p-channel transistor V _CC − | V _thp is connected to node NO6 with Q17.
| Potential of -V _thn is, the node NO7 the resistance component R ₂ having the p-channel transistor Q17 and the resistance value r ₂ V
_CC − | V _thp | −V _thn − | V _thp | = V _CC −2 | V
_thp | _-Vthn is applied to the n- channel transistor Q1.
8 and p-channel transistor Q19 node NO8 V _CC -2 to | because the potential is outputted, | V _thp
Similar to the above embodiment, one cycle is completed read operation, the power supply voltage V _CC from V _CC 'if you drop, V _CC over V _CC gate potential than the source potential of the charge pull transistor' + _Becomes higher by | V _thp |, and as a result, it is possible to suppress a delay in response speed due to a drop in power supply voltage. Further, when the size of the n-channel transistor Q16 and the p-channel transistor Q17 constituting the output stage is increased to increase the driving capability,
A reference potential with low impedance can be output.

[0023]

As described above, the semiconductor memory according to the present invention is described.
According to the storage device, a plurality of memory cells and each memory cell
On the other hand, a complex provided so that one is connected to the memory cell
Bit line pairs and each bit line pair of the plurality of bit line pairs
Multiple sense amplifiers and data
Write data is transmitted to the selected bit line pair during programming.
Select the write data line pair to reach and when reading data
To transfer read data from the selected bit line pair
The data line pair, the load section and the drive section read
Output data line pairs and bit line pairs
And the potential of the bit line pair is differentially increased as an input signal.
Semiconductor memory with wide current mirror differential amplifier
In the device, the voltage value of the power supply voltage in conjunction with the supply voltage
A reference potential generation circuit for outputting a reference potential having a lower voltage value, and a drain grounded, and an output of the reference potential generation circuit
A gate receiving, saw respectively to the read data line pair
A pair of charge pull transistor which scan is connected,
The current mirror is provided for the read data line pair.
-Read data that connects the load and drive of the differential amplifier
A gate receiving a potential corresponding to the intermediate potential on the line pair at the gate
Since a transfer transistor is provided , when a negative bump occurs in the power supply voltage, the charge extraction transistor is turned on to form a path for extracting electric charge, and the read data line pair is also properly connected after the power supply voltage drops. It drops to a stable potential, as a result, the read operation is faster, it is possible to perform stable read operation, the current
The read data connected to the mirror differential amplifier driver
Since the logic amplitude of the node of the data line can be limited,
High-speed read operation and low power consumption can be achieved.
As a result, a more stable read operation can be performed.
There is an effect that can be done .

[0024]

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a main part of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing a read operation of the semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a main part of a semiconductor memory device according to another embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a reference potential generating circuit of a semiconductor memory device according to another embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a main part of a conventional semiconductor memory device.

FIG. 6 is a signal waveform diagram showing a read operation of a conventional semiconductor memory device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 drive unit of current mirror differential amplifier 2 load unit of current mirror differential amplifier 3 reference potential generation circuit 3 ′ reference potential generation circuit 4 charge extraction transistor group 4 ′ charge extraction transistor group 5 transfer transistor group Q 1 to Q 4 , Q9~Q12, Q15, Q17, Q1 9,
Q20, Q21 P-channel transistor Q5~Q8 Q13, Q14, Q1 8 N-channel transistor NO1, NO2, NO3, NO4, NO5, NO6, N
O7, NO8 Node BL, / BL Bit line WI, / WI Write data line RI, / RI Read data line WL Word line NOA, NOB node

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/407

Claims (1)

(57) [Claims] A plurality of memory cells; a plurality of bit line pairs provided so that one of the memory cells is connected to the memory cell; and a plurality of bit line pairs corresponding to the plurality of bit line pairs. A plurality of sense amplifiers, a write data line pair for transmitting write data to a selected bit line pair during data writing, and a read data line pair for transmitting read data from the selected bit line pair during data read And a current mirror differential amplifier in which a load unit and a drive unit are provided corresponding to the read data line pair and the bit line pair, respectively, and differentially amplify the potential of the bit line pair as an input signal. A reference potential generating circuit for outputting a reference potential having a voltage value lower than the voltage value of the power supply voltage in conjunction with the power supply voltage; And, receiving the output of the reference potential generating circuit to the gate, a pair of charge pull transistor whose source respectively to the read data line pair is connected, is provided on the read data line pair, said current mirror
-Read data that connects the load and drive of the differential amplifier
A gate receiving a potential corresponding to the intermediate potential on the line pair at the gate
And a transfer transistor .