JPH0571950U - Periodic memory inspection device - Google Patents

Abstract

(57) [Abstract] [Purpose] Realizing a fixed-cycle memory inspection device that can determine whether or not there is a memory failure in the inspection word by distinguishing between hard errors and soft errors for errors in the result of the fixed-cycle memory inspection. It is to be. [Structure] A memory 1 capable of storing a test result in a fixed-cycle memory test for each word, and a data test circuit 2 for testing read data, outputting SEER of the test result, and correcting a 1-bit error by an EDC function. And a memory inspection instruction circuit 3 that receives the previous inspection result ERRF from the memory 1 and performs data processing by determining whether it is a hard error or a soft error from the relationship with the input SERR.
In the case of a hard error, the register 4 is used to store the address of the inspection word.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a fixed-cycle memory inspection device that inspects a computer memory at a fixed period by using an EDC function, and more particularly to a fixed-cycle memory inspection device that can determine a memory failure.

[0002]

[Prior Art]

 The conventional device that inspects the memory for the computer at a fixed cycle does not have a structure for storing the past inspection result, so that the faulty part of the memory cannot be specified by hardware. That is, the hardware itself does not know the hardware failure.

[0003]

[Problems to be solved by the device]

 As mentioned above, since the hardware does not know the failure, it is wasteful to write the correction data many times. In order to do this by software, it is necessary to store the history of error occurrences, and therefore the data area must be used. In the worst case, half the memory area is required.

The present invention has been made in view of the above points, and an object thereof is to discriminate between a hard error and a soft error with respect to an error as a result of a fixed-cycle memory inspection, thereby detecting a memory failure of an inspection word. It is to realize a fixed-cycle memory inspection device that can determine the presence or absence.

[0005]

[Means for Solving the Problems]

 The present invention, which solves the above-mentioned problems, provides a memory that can store the inspection result of a fixed-cycle memory inspection for each word and an inspection of read data to output the inspection result, and when there is a 1-bit error in the data. The data inspection circuit with the EDC function that corrects the error and the current inspection result from the data inspection circuit at the time of the fixed cycle memory inspection are received, and the previous inspection result is read from the memory to determine whether the error is a hard error or a soft error. In the case of a hard error, a failure detection signal is output, and a memory control signal is sent to the memory to control writing of correction data and writing of the inspection result this time, and a memory inspection instruction circuit, It is composed of a register that stores the address of the memory under inspection when the failure detection signal from the memory inspection instruction circuit is input. It is intended to.

[0006]

[Action]

 The data inspection circuit inspects the data in the memory word by word and outputs a signal of the inspection result to the memory inspection instruction circuit. The memory inspection instruction circuit reads the previous inspection result from the memory, determines whether it is a hard error or a soft error from both the inspection result signal from the data inspection circuit, and sends a failure result signal to the register in the case of a hard error. The memory address is saved and the writing of correction data to the memory is stopped.

When it is determined that the error is not a hard error, the memory inspection instruction circuit sends a memory control signal to the memory, and the correction data or the error signal of the inspection result of this time is stored in the memory depending on the case of the soft error or the unclear judgment. To write to.

[0008]

【Example】

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a memory that undergoes a fixed-cycle memory test, and can store an inspection result (ERRF) during the fixed-cycle memory test for each word.

Reference numeral 2 denotes a data inspection circuit having an EDC function capable of inspecting the data (DATA) read from the memory 1 word by word and correcting if there is a 1-bit error in the data. Can be written on.

Reference numeral 3 is a memory inspection that receives the inspection result (SERR) of the inspection performed this time from the data inspection circuit 2 during the periodic memory inspection, reads the previous inspection result (ERRF) from the memory 1, and processes the inspection result. It is an instruction circuit. The data of the inspection result is an error flag represented by "1" when there is an error and "0" when there is no error. As a result, the memory inspection instruction circuit 3 judges that the error is a hard error if ERRRF = 1 and SERR = 1, that is, if the error occurs twice in succession, the failure detection is performed without rewriting the memory. If a signal (HERR) is output and ERRF = 1 and SERR = 0, it is judged that there is no failure and ERRF = 0 is written to memory 1. If ERRF = 0 and SERR = 1, a new error has occurred. Then, ERRF = 1 is written in the memory 1, and a memory control signal is sent from the data checking circuit 2 to write the corrected data in the memory 1.

A register 4 receives a failure detection signal from the memory inspection instruction circuit 3 and stores the address on the memory of the word having an error during inspection when HERR is 1.

Next, the operation of the apparatus of the embodiment configured as described above will be described with reference to the flowchart of FIG.

Step 1 The data inspection circuit 2 reads data from the memory 1, and the memory inspection instruction circuit 3 reads ERRF from the memory 1.

Step 2 The memory inspection instruction circuit 3 inspects whether the read ERRF is ERRF = 0. If ERRF = 0, go to step 3. If ERRF = 1, proceed to step 5.

Step 3 The data inspection circuit 2 inspects the data read from the memory 1 and sends the inspection result SE RR to the memory inspection instruction circuit 3. The memory inspection instruction circuit 3 checks the SERR. If SERR = 0, there is no failure because ERRF = 0 and SERR = 0, and the inspection of this word ends. If SERR = 1, go to step 4.

Step 4 Since ERRF = 0 and SEER = 1, it is difficult to judge whether the error is a hard error or a soft error. Therefore, the data inspection circuit 2 outputs the corrected data, and the memory inspection instruction circuit 3 issues the ER RF = 1 to the memory inspection instruction. Writing to the memory 1 by the memory control signal of the circuit 3 completes the inspection of this word.

Step 5 The memory check instruction circuit 3 checks the SERR sent from the data check circuit 2, and if SE RR = 0, proceeds to step 6. If SERR = 1, go to step 7.

Step 6 Since ERRF = 1 and SERR = 0, it is determined that there is no hard error, the memory inspection instruction circuit 3 writes ERRF = 0 in the memory 1, and the inspection of this word ends.

Step 7 Since ERRF = 1 and SERR = 1, it is determined that a hard error has occurred in the check bit, and the memory check instruction circuit 3 sends a memory control signal to the memory 1 to send the corrected data from the data check circuit 2. The failure detection signal HEER is output to the register 4 without writing. Register 4 stores the address of the memory under test and the test of this word is complete.

As described above, according to the present embodiment, when a 1-bit error occurs in the memory, it is determined whether the error is due to a memory failure, and if the error is due to the failure, the corrected data is returned. Since the data is not written back, the efficiency of the fixed-cycle memory check is improved, and the faulty memory can be found, and the memory area is used very little and the memory usage efficiency is good.

[0021]

[Effect of the device]

 As described in detail above, according to the present invention, it is possible to discriminate between a hard error and a soft error with respect to the error of the result of the periodic memory inspection, and to judge whether the memory of the inspection word has a failure. It becomes possible, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

2 is a flow chart of the operation of the apparatus of FIG.

[Explanation of symbols]

 1 memory 2 data inspection circuit 3 memory inspection instruction circuit 4 register

Claims (1)

[Scope of utility model registration request] 1. A memory (1) capable of storing a test result at a fixed cycle memory test for each word, and a read data test is performed to output a test result (SERR), and the data has a 1-bit error. A data inspection circuit (2) having an EDC function for correcting the case and a current inspection result (SERR) from the data inspection circuit (2) at the time of the periodic memory inspection are received, and the previous inspection result is received from the memory (1). Load (ERRF),
It is determined whether the error is a hard error or a soft error, and in the case of a hard error, a failure detection signal (HERR) is output, and at the same time, a memory control signal is sent to the memory (1) to write the correction data and the inspection result of this time ( A memory inspection instruction circuit (3) for controlling writing of ERRF) and a failure detection signal (HE) from the memory inspection instruction circuit (3)
A fixed cycle memory inspection device comprising: a register (4) for storing an address of the memory (1) under inspection when RR) is input.