JPH056883A - Method for manufacturing semiconductor substrate - Google Patents
Method for manufacturing semiconductor substrateInfo
- Publication number
- JPH056883A JPH056883A JP27674291A JP27674291A JPH056883A JP H056883 A JPH056883 A JP H056883A JP 27674291 A JP27674291 A JP 27674291A JP 27674291 A JP27674291 A JP 27674291A JP H056883 A JPH056883 A JP H056883A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- manufacturing
- semiconductor
- film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 71
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000013078 crystal Substances 0.000 claims description 16
- 238000005498 polishing Methods 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 37
- 229910052710 silicon Inorganic materials 0.000 abstract description 37
- 239000010703 silicon Substances 0.000 abstract description 37
- 229910004298 SiO 2 Inorganic materials 0.000 description 15
- 238000002955 isolation Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
(57)【要約】
【目的】 結晶性のすぐれたＳＯＩ(Silicon on Insula
tor)基板を形成する方法を提供すること。
【構成】 第１のシリコン基板１上に酸化膜２を、第２
のシリコン基板３上にエピタキシャルシリコン成長膜４
を形成し、双方を酸化膜２側とエピタキシャルシリコン
成長膜４側とで貼り合わせる。貼り合わせた積層基板は
第２のシリコン基板３をエピタキシャルシリコン成長膜
４が露出するまで削り、エピタキシャルシリコン成長膜
４，酸化膜２，第１のシリコン基板１によるＳＯＩ構造
を得る。
(57) [Abstract] [Purpose] Highly crystalline SOI (Silicon on Insula)
tor) providing a method of forming a substrate. [Structure] The oxide film 2 is formed on the first silicon substrate 1
Epitaxial silicon growth film 4 on the silicon substrate 3 of
Are formed, and both are bonded to the oxide film 2 side and the epitaxial silicon growth film 4 side. The laminated substrates bonded together are ground to remove the second silicon substrate 3 until the epitaxial silicon growth film 4 is exposed to obtain an SOI structure with the epitaxial silicon growth film 4, the oxide film 2 and the first silicon substrate 1.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＳＯＩ（Semiconducto
r-On-Insulator) 構造を有する半導体基板の製造方法に
関する。The present invention relates to an SOI (Semiconducto)
The present invention relates to a method for manufacturing a semiconductor substrate having an r-On-Insulator) structure.
【０００２】[0002]
【従来の技術】ＳＯＩ基板は、半導体シリコン基板上に
ＳｉＯ2 等の絶縁層を形成して絶縁基板とし、その上に
更に半導体シリコン層を形成したものである。2. Description of the Related Art An SOI substrate is one in which an insulating layer such as SiO 2 is formed on a semiconductor silicon substrate to form an insulating substrate, and a semiconductor silicon layer is further formed on the insulating substrate.
【０００３】しかしながら、絶縁層上に形成する半導体
シリコン層として、いわゆるバルクシリコンを貼り合わ
せ形成したものは、結晶性がわるく、リーク特性、耐圧
特性等に問題があった。However, the semiconductor silicon layer formed on the insulating layer, which is formed by laminating so-called bulk silicon, has poor crystallinity and has problems such as leak characteristics and withstand voltage characteristics.
【０００４】一方、エピタキシャル成長による単結晶の
半導体シリコン層は、結晶欠陥が少なく、不純物の混入
制御も容易なことから、半導体装置に用いられている
（例えば特開昭６０−１４４９４９号）。また、２枚の
半導体基板の表面を互いに酸化させ、その酸化された面
どうしを貼り合わせる方法が提案されている（例えば特
開昭６３−６５６４８号）。On the other hand, a single-crystal semiconductor silicon layer formed by epitaxial growth has been used in a semiconductor device because it has few crystal defects and the control of impurities is easy (for example, JP-A-60-144949). Further, a method has been proposed in which the surfaces of two semiconductor substrates are mutually oxidized and the oxidized surfaces are bonded to each other (for example, JP-A-63-65648).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、例えば
ＳＯＩを形成すべく、絶縁基板上に直接シリコンエピタ
キシャル層を成長させると、そのシリコン層はアモルフ
ァスか多結晶になるので、これを単結晶化するために、
再結晶の処理が必要であった。また、２枚の半導体基板
を互いに酸化させ、その酸化された面どうしを貼り合わ
せる方法では酸化膜面を両基板の主面に形成しなければ
ならないため、製造工程が増加するという問題がある。However, when a silicon epitaxial layer is grown directly on an insulating substrate in order to form, for example, SOI, the silicon layer becomes amorphous or polycrystalline, so that it is made into a single crystal. To
Recrystallization process was required. Further, in the method of oxidizing two semiconductor substrates to each other and bonding the oxidized surfaces to each other, the oxide film surface has to be formed on the main surfaces of both substrates, which causes a problem that the number of manufacturing steps increases.
【０００６】そこで、本発明は、絶縁基板上に直接単結
晶のシリコンエピタキシャル層を形成することができる
半導体基板の製造方法を提供することを目的としてい
る。[0006] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor substrate in which a single crystal silicon epitaxial layer can be directly formed on an insulating substrate.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記目的を達
成するために、第１面を有する第１の半導体基板の上記
第１面に酸化膜を形成する第１の工程と、第２面及びこ
の第２面の裏面である第３面とを有する第２の半導体基
板の上記第２面に単結晶の半導体層を形成する第２の工
程と、この第２の工程を経て上記第２面に単結晶の半導
体層が形成された上記第２の半導体基板と上記第１の工
程を経て酸化膜が形成された上記第１の半導体基板の上
記第１面とを貼り合わせる第３の工程と、この第３の工
程により貼り合わされた上記第２の半導体基板をその第
３面側から上記単結晶の半導体層が露出するまで研摩す
る第４の工程とを備えて構成した。In order to achieve the above object, the present invention provides a first step of forming an oxide film on the first surface of a first semiconductor substrate having a first surface, and a second step. A second step of forming a single crystal semiconductor layer on the second surface of the second semiconductor substrate having a surface and a third surface which is the back surface of the second surface, and the second step through the second step. A second semiconductor substrate having a single-crystal semiconductor layer formed on its two faces and the first surface of the first semiconductor substrate having an oxide film formed through the first step; And a fourth step of polishing the second semiconductor substrate bonded by the third step from the third surface side thereof until the single crystal semiconductor layer is exposed.
【０００８】[0008]
【作用】本発明は、上記構成により、酸化膜を形成した
第１の半導体基板と単結晶の半導体層を形成した第２の
半導体層とを互いに貼り合わせることによって半導体積
層基板を形成する。そのため、絶縁基板上に直接結晶性
のよい単結晶の半導体層を形成することができ、再結晶
処理が不要となる。According to the present invention, the semiconductor laminated substrate is formed by bonding the first semiconductor substrate having the oxide film and the second semiconductor layer having the single crystal semiconductor layer to each other with the above-described structure. Therefore, a single-crystal semiconductor layer with good crystallinity can be formed directly on the insulating substrate, and recrystallization treatment is unnecessary.
【０００９】また、第２の半導体基板の主面にあらかじ
め所定パターンの酸化膜を形成しておけば、その酸化膜
を素子分離用の酸化膜として用いることができるととも
に、研摩の際のストッパーとして利用することができ
る。If an oxide film having a predetermined pattern is previously formed on the main surface of the second semiconductor substrate, the oxide film can be used as an oxide film for element isolation and also as a stopper for polishing. Can be used.
【００１０】[0010]
【実施例】以下に本発明の実施例を図面を参照して説明
する。図１は本発明の一実施例であるＳＯＩ構造の半導
体基板の製造方法を製造工程順に示す断面図である。Embodiments of the present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views showing a method of manufacturing an SOI structure semiconductor substrate according to an embodiment of the present invention in the order of manufacturing steps.
【００１１】まず、図１（ａ）に示すように、第１の半
導体シリコン基板１の表面上にＣＶＤ法によりＳｉＯ2
膜２を０．５〜２μｍ厚に形成する。この時、例えばＰ
2 Ｏ5 やＢ2 Ｏ3 を用いてリンまたはホウ素を４〜８ｗ
ｔ％混入させると、クラック等が入りにくくなるので好
ましい。また、ＣＶＤ法の他熱酸化法でも所定の膜が形
成されればよいが、この場合は、１μｍ以上のＳｉＯ2
膜形成には長時間の熱処理が必要となるので、ＣＶＤ法
の方が好ましい。First, as shown in FIG. 1A, SiO 2 is formed on the surface of the first semiconductor silicon substrate 1 by the CVD method.
The film 2 is formed to have a thickness of 0.5 to 2 μm. At this time, for example, P
Phosphorus or boron 4 to 8 w using 2 O 5 or B 2 O 3
When t% is mixed, cracks are less likely to occur, which is preferable. A predetermined film may be formed by a thermal oxidation method other than the CVD method. In this case, SiO 2 having a thickness of 1 μm or more is used.
Since the film formation requires a long time heat treatment, the CVD method is preferable.
【００１２】一方、図１（ｂ）に示すように、第２の半
導体シリコン基板３上にシリコンのエピタキシャル膜４
を０．５〜２μｍ厚に成長させる。成長方法は、例えば
１１５０〜１２００℃の高温度下でシラン（ＳｉＨ4 ）
の水素還元法による。On the other hand, as shown in FIG. 1B, a silicon epitaxial film 4 is formed on the second semiconductor silicon substrate 3.
Are grown to a thickness of 0.5 to 2 μm. The growth method is, for example, silane (SiH 4 ) at a high temperature of 1150 to 1200 ° C.
Hydrogen reduction method.
【００１３】次いで、図１（ｃ）に示すように、第１の
半導体シリコン基板１と第２の半導体シリコン基板３と
を向かい合わせて、その主面どうしを貼り合わせ、１０
００〜１２００℃の高温下、水蒸気雰囲気中で熱処理し
て互いに接着する。Then, as shown in FIG. 1C, the first semiconductor silicon substrate 1 and the second semiconductor silicon substrate 3 are opposed to each other, and their principal surfaces are bonded together.
Heat treatment is performed in a steam atmosphere at a high temperature of 00 to 1200 ° C. to bond them to each other.
【００１４】しかる後、第２の半導体シリコン基板３を
その裏面側から機械的に研摩する。そして、第２の半導
体シリコン基板３が１〜２μｍ程度残っている状態で、
機械的研摩を止め、その後は、ＨＦ：ＨＮＯ3 ：ＣＨ3
ＣＯＯＨ ＝ １：３：８の溶液によって溶解研摩す
る。これにより、図１（ｄ）に示すように、シリコンエ
ピタキシャル膜４を露出させる。After that, the second semiconductor silicon substrate 3 is mechanically polished from its back surface side. Then, in a state where the second semiconductor silicon substrate 3 remains about 1 to 2 μm,
After stopping mechanical polishing, HF: HNO 3 : CH 3
Dissolve polish with a solution of COOH = 1: 3: 8. As a result, the silicon epitaxial film 4 is exposed as shown in FIG.
【００１５】以上のように構成することによって、Ｓｉ
Ｏ2 膜２の上に直接単結晶のシリコンエピタキシャル膜
４が形成されたＳＯＩ基板を得ることができる。By configuring as described above, Si
It is possible to obtain an SOI substrate in which the single crystal silicon epitaxial film 4 is directly formed on the O 2 film 2.
【００１６】図２に本発明の第２の実施例を示す。本実
施例においては、図２（ａ）に示すように、第２の半導
体シリコン基板３の周辺部に予め約２ｍｍ幅のＳｉＯ2
膜５を１〜２μｍ厚に形成しておく。このＳｉＯ2 膜５
の膜厚は、後に成長させるシリコンエピタキシャル膜の
膜厚に等しい膜厚とする。FIG. 2 shows a second embodiment of the present invention. In this embodiment, as shown in FIG. 2 (a), SiO 2 having a width of about 2 mm is previously formed on the peripheral portion of the second semiconductor silicon substrate 3.
The film 5 is formed to have a thickness of 1 to 2 μm. This SiO 2 film 5
The film thickness of is equal to the film thickness of the silicon epitaxial film to be grown later.
【００１７】次に、図２（ｂ）に示すように、この第２
の半導体シリコン基板３の上のＳｉＯ2 膜５の部分を除
いた部分にのみ、選択エピタキシャル成長技術を用い
て、シリコンエピタキシャル膜４を成長させる。Next, as shown in FIG.
The silicon epitaxial film 4 is grown only on the portion of the semiconductor silicon substrate 3 excluding the portion of the SiO 2 film 5 by using the selective epitaxial growth technique.
【００１８】しかる後、図２（ｃ）に示すように、上述
した第１の実施例と同様、この第２の半導体シリコン基
板３とＳｉＯ2 膜２を形成した第１の半導体シリコン基
板１とを互いに貼り合わせて、熱処理により接着する。Thereafter, as shown in FIG. 2C, as in the case of the above-described first embodiment, the second semiconductor silicon substrate 3 and the first semiconductor silicon substrate 1 having the SiO 2 film 2 formed thereon are formed. Are bonded to each other and bonded by heat treatment.
【００１９】そして、図２（ｄ）に示すように、第２の
半導体シリコン基板３をその裏面側から研摩してシリコ
ンエピタキシャル膜４を露出させる。この時、ＳｉＯ2
の研摩速度はシリコンに比較して小さいので、ＳｉＯ2
膜５を研摩のストッパーとして利用することができ、従
って、シリコンエピタキシャル膜４の膜厚を精密に制御
することができる。Then, as shown in FIG. 2D, the second semiconductor silicon substrate 3 is polished from the rear surface side to expose the silicon epitaxial film 4. At this time, SiO 2
Since the polishing rate of SiO 2 is smaller than that of silicon, SiO 2
The film 5 can be used as a stopper for polishing, so that the film thickness of the silicon epitaxial film 4 can be precisely controlled.
【００２０】図３に本発明の第３の実施例を示す。本実
施例においては、図３（ａ）に示すように、第２の半導
体シリコン基板３の周辺部に研摩ストッパー用のＳｉＯ
2 膜５を形成する際、予め素子分離用のＳｉＯ2 膜６も
同時にパターン形成しておく。FIG. 3 shows a third embodiment of the present invention. In this embodiment, as shown in FIG. 3A, SiO for a polishing stopper is formed on the peripheral portion of the second semiconductor silicon substrate 3.
When forming the 2 film 5, the SiO 2 film 6 for element isolation is also patterned in advance at the same time.
【００２１】その後、第２の実施例と同様に工程を進め
ていくと、最終的に図３（ｄ）に示すように、シリコン
エピタキシャル膜４に素子分離用のＳｉＯ2 部６が形成
されたＳＯＩ基板を得ることができる。After that, when the steps were carried out in the same manner as in the second embodiment, finally, as shown in FIG. 3D, the SiO 2 portion 6 for element isolation was formed in the silicon epitaxial film 4. An SOI substrate can be obtained.
【００２２】なお、本実施例のように素子分離用のＳｉ
Ｏ2 膜６を形成する場合には、このＳｉＯ2 膜６を研摩
ストッパーとしても用いることができるので、研摩スト
ッパー用のＳｉＯ2 膜５はあえて形成する必要はない。
しかしながら、研摩ストッパーは、第２の半導体シリコ
ン基板３の中央部のみに存在するよりは周辺部にあった
方が作業上有利であるので、ＳｉＯ2 膜５を設ける方が
より好ましい。As in the present embodiment, Si for element isolation is used.
When the O 2 film 6 is formed, the SiO 2 film 6 can also be used as a polishing stopper, so that it is not necessary to form the SiO 2 film 5 for the polishing stopper.
However, it is more advantageous in terms of work to have the polishing stopper in the peripheral portion of the second semiconductor silicon substrate 3 than in the central portion thereof. Therefore, it is more preferable to provide the SiO 2 film 5.
【００２３】[0023]
【発明の効果】以上説明したように本発明によれば、絶
縁基板上に直接結晶性のよい半導体エピタキシャル層を
形成することができるので、簡単且つ確実な方法で、特
性の良い半導体積層基板を製造することができる。As described above, according to the present invention, since a semiconductor epitaxial layer having good crystallinity can be formed directly on an insulating substrate, a semiconductor laminated substrate having excellent characteristics can be obtained by a simple and reliable method. It can be manufactured.
【図１】本発明の第１の実施例を示す半導体基板の製造
方法の工程順概略断面図である。FIG. 1 is a schematic cross-sectional view in order of the steps of a method for manufacturing a semiconductor substrate, which shows a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す半導体基板の製造
方法の工程順概略断面図である。FIG. 2 is a schematic cross-sectional view in order of the steps of a method for manufacturing a semiconductor substrate showing a second embodiment of the present invention.
【図３】本発明の第３の実施例を示す半導体基板の製造
方法の工程順概略断面図である。FIG. 3 is a schematic cross-sectional view in order of the steps of a method for manufacturing a semiconductor substrate showing a third embodiment of the present invention.
１ 第１の半導体基板 ２ 酸化膜 ３ 第２の半導体基板 ４ 単結晶半導体層 ５ 酸化膜 ６ 酸化膜 1 First semiconductor substrate 2 oxide film 3 Second semiconductor substrate 4 Single crystal semiconductor layer 5 Oxide film 6 oxide film
Claims (10)
第１面に酸化膜を形成する第１の工程と、第２面及びこ
の第２面の裏面である第３面とを有する第２の半導体基
板の上記第２面に単結晶の半導体層を形成する第２の工
程と、この第２の工程を経て上記第２面に単結晶の半導
体層が形成された上記第２の半導体基板と上記第１の工
程を経て酸化膜が形成された上記第１の半導体基板の上
記第１面とを貼り合わせる第３の工程と、この第３の工
程により貼り合わされた上記第２の半導体基板をその第
３面側から上記単結晶の半導体層が露出するまで研摩す
る第４の工程と、を有する半導体基板の製造方法。1. A first step of forming an oxide film on the first surface of a first semiconductor substrate having a first surface, a second surface, and a third surface which is a back surface of the second surface. A second step of forming a single crystal semiconductor layer on the second surface of the second semiconductor substrate, and the second step of forming a single crystal semiconductor layer on the second surface through the second step. A third step of bonding the semiconductor substrate and the first surface of the first semiconductor substrate having the oxide film formed through the first step, and the second step of bonding by the third step. And a fourth step of polishing the semiconductor substrate from the third surface side thereof until the single crystal semiconductor layer is exposed.
により単結晶の半導体層を形成することを特徴とする請
求項第１項記載の半導体基板の製造方法。2. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the second step, a single crystal semiconductor layer is formed by an epitaxial growth method.
に形成する単結晶の半導体層はシリコン材料で構成され
ることを特徴とする請求項第１項記載の半導体基板の製
造方法。3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the second semiconductor substrate and the single crystal semiconductor layer formed on the second surface of the second semiconductor substrate are made of a silicon material.
定パターンの酸化膜を形成する第５の工程を上記第２の
工程の前に有する請求項第１項記載の半導体基板の製造
方法。4. The manufacturing of a semiconductor substrate according to claim 1, further comprising a fifth step of forming an oxide film having a predetermined pattern on the second surface of the second semiconductor substrate before the second step. Method.
記第２の半導体基板の上記第２面の酸化膜が形成されて
いない基板表面上に単結晶の半導体層を形成することを
特徴とする請求項第４項記載の半導体基板の製造方法。5. In a second step, after the fifth step, a single-crystal semiconductor layer is formed on the surface of the second semiconductor substrate on which the oxide film of the second surface is not formed. The method of manufacturing a semiconductor substrate according to claim 4, wherein
により単結晶の半導体層を形成することを特徴とする請
求項第５項記載の半導体基板の製造方法。6. The method of manufacturing a semiconductor substrate according to claim 5, wherein in the second step, a single crystal semiconductor layer is formed by an epitaxial growth method.
徴とする請求項第１項記載の半導体基板の製造方法。7. The method of manufacturing a semiconductor substrate according to claim 1, wherein the third step includes heat treatment.
を特徴とする請求項第７項記載の半導体基板の製造方
法。8. The method of manufacturing a semiconductor substrate according to claim 7, wherein the heat treatment is performed in a steam atmosphere.
温度範囲で行うことを特徴とする請求項第７項記載の半
導体基板の製造方法。9. The method of manufacturing a semiconductor substrate according to claim 7, wherein the heat treatment is performed in a temperature range of 1000 to 1200 ° C.
それに続く溶液研摩工程とを含むことを特徴とする請求
項第１項記載の半導体基板の製造方法。10. The fourth step comprises a mechanical polishing step,
The method of manufacturing a semiconductor substrate according to claim 1, further comprising a solution polishing step that follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27674291A JPH056883A (en) | 1990-09-28 | 1991-09-27 | Method for manufacturing semiconductor substrate |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26066990 | 1990-09-28 | ||
| JP2-260669 | 1990-09-28 | ||
| JP27674291A JPH056883A (en) | 1990-09-28 | 1991-09-27 | Method for manufacturing semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH056883A true JPH056883A (en) | 1993-01-14 |
Family
ID=26544699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27674291A Withdrawn JPH056883A (en) | 1990-09-28 | 1991-09-27 | Method for manufacturing semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH056883A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0917193A1 (en) * | 1997-11-10 | 1999-05-19 | Nec Corporation | Laminated SOI substrate and producing method thereof |
| WO2000033045A1 (en) * | 1998-11-27 | 2000-06-08 | Commissariat A L'energie Atomique | Micromachined structure with deformable membrane and method for making same |
| JP2000331899A (en) * | 1999-05-21 | 2000-11-30 | Shin Etsu Handotai Co Ltd | Method for forming soi wafer and soi wafer |
| US6427748B1 (en) | 1998-07-27 | 2002-08-06 | Canon Kabushiki Kaisha | Sample processing apparatus and method |
| US6489654B2 (en) | 1998-04-17 | 2002-12-03 | Nec Corporation | Silicon-on-insulator (SOI) substrate |
-
1991
- 1991-09-27 JP JP27674291A patent/JPH056883A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0917193A1 (en) * | 1997-11-10 | 1999-05-19 | Nec Corporation | Laminated SOI substrate and producing method thereof |
| US6323109B1 (en) | 1997-11-10 | 2001-11-27 | Nec Corporation | Laminated SOI substrate and producing method thereof |
| US6489654B2 (en) | 1998-04-17 | 2002-12-03 | Nec Corporation | Silicon-on-insulator (SOI) substrate |
| US6427748B1 (en) | 1998-07-27 | 2002-08-06 | Canon Kabushiki Kaisha | Sample processing apparatus and method |
| US6609553B2 (en) | 1998-07-27 | 2003-08-26 | Canon Kabushiki Kaisha | Sample processing apparatus and method |
| US6773534B2 (en) | 1998-07-27 | 2004-08-10 | Canon Kabushiki Kaisha | Sample processing apparatus and method |
| WO2000033045A1 (en) * | 1998-11-27 | 2000-06-08 | Commissariat A L'energie Atomique | Micromachined structure with deformable membrane and method for making same |
| JP2000331899A (en) * | 1999-05-21 | 2000-11-30 | Shin Etsu Handotai Co Ltd | Method for forming soi wafer and soi wafer |
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Legal Events
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| A300 | Withdrawal of application because of no request for examination |
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