JPH0567949A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To easily generate a test pattern with a high fault detection rate by providing a test changeover means outputting a data output signal corresponding to a data input signal directly via a prescribed test switching signal on the flip-flop circuit. CONSTITUTION:A test switching signal 103 is kept to be at an H level, and when a clock signal 102 is transited to an H level, a signal 104 goes to an L level and a signal 105 is outputted as an H level signal and they are inputted respectively to transfer gates 6, 7, 11, 12 respectively. The gates 6, 12 are in interrupted state and the gates 7, 11 reach the signal passing state. With the signal 102 set to an L, a data signal 101 fetched in the gate 1 is kept to a level as it is and inputted to a slave latch 30, inverted by an inverter 10 and outputted via a data output terminal 54 as a data signal 106 via the gate 11 and an inverter 13. When the signal 102 inputted from a clock input terminal 52 changes from an L to an H, the data signal 101 just before the point of time is outputted from the output terminal 54.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a flip-flop circuit.

[0002]

2. Description of the Related Art A conventional flip-flop circuit includes inverters 33, 36 and 3 as shown in FIG.
7, a master latch 29 formed by transfer gates 34 and 35 formed of PMOS transistors and NMOS transistors, and an inverter 38,
41 and 42, PMOS transistor and NMO
Slave latch 30 formed by transfer gates 39 and 40 composed of S transistors, and inverters 31 and 32 corresponding to clock input terminal 60.
And is configured.

In FIG. 3, the data signal 115 is input from the data input terminal 59, and the clock signal 116 is input from the clock input terminal 60. Clock signal 1
Corresponding to the input of 16, the clock signal 117 inverted by the inverter 31 is input to the gate of the NMOS transistor of the transfer gate 34, and the clock signal 118 inverted by the inverter 32 is input by the PMOS transistor of the transfer gate 34. Input to the gate. Therefore, the transfer gate 34 is
Clock signal 11 input from the clock input terminal 60
When 6 is at the "L" level, a signal is passed, and the data signal 115 is inverted by the inverter 33 and input to the inverter 36, and further inverted by the inverter 36 and output. That is, the data signal 115 is taken in by the master latch 29 and input to the slave latch 30 when the clock signal 116 is at “L” level. Next, when the clock signal 116 becomes "H" level, the transfer gate 34 becomes the signal cutoff state, and instead the transfer gate 35 becomes the signal passing state, and when the clock signal 116 is at the "L" level, the master latch 29 The data signal 115 taken in is held at the same level.

Inverter 3 of the master latch 29 in the previous stage
The data signal output from 6 is input to the slave latch 30, inverted by the inverter 38, and input to the transfer gate 39. When the clock signal 116 is at the "H" level, the transfer gate 39 is in the signal passing state, The data signal is output via the inverter 41 and the data output terminal 61. Next, when the clock signal 116 becomes "L" level, the transfer gate 39 becomes the signal cutoff state, and instead the transfer gate 40 becomes the signal passing state, and when the clock signal 116 is at the "L" level, the slave latch 30 The data signal 115 taken in is held at the same level and is output via the data output terminal 61.

Therefore, at the time when the clock signal 116 input from the clock input terminal 60 changes from the "L" level to the "H" level, the immediately preceding data signal of the data signal is passed through the sampling action of the clock signal. The value is output from the data output terminal 61 as the data signal 120.

[0006]

In the above-mentioned conventional flip-flop circuit, when forming a system circuit such as a logic circuit in a form of cascade connection with another combinational circuit, the fault detection rate of the system circuit is concerned. In order to increase, the flip-flop circuit has only the function of sampling and outputting the data input signal by the clock signal, so that every time the other combination circuit forming the system circuit is operated, A clock signal must be input to the flip-flop circuit, and in order to operate the combinational circuit connected to the subsequent stage of this flip-flop circuit, the clock signal corresponding to this combinational circuit and the flip-flop circuit itself must be input. Need to work. Therefore, as a test pattern for testing the combinational circuit forming the system circuit, a huge amount of time is required to create the test pattern, and the test pattern length is also enormous. is there.

[0007]

A flip-flop circuit according to the present invention includes a master latch and a slave latch corresponding to a data input signal and is cascade-connected to another combinational circuit to form a predetermined system circuit. In the flip-flop circuit, at least one flip-flop circuit among the flip-flop circuits directly outputs a data output signal corresponding to the data input signal via a predetermined test switching signal without depending on a clock signal. And a test switching means for outputting

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, inverters 5, 8 and 9 and a transfer gate 6 composed of a PMOS transistor and an NMOS transistor are used.
Master latch 1 formed by inverters and 7, inverters 10, 13 and 14, slave latch 2 formed by transfer gates 11 and 12 formed of PMOS transistors and NMOS transistors, clock input terminal 52 and test switching terminal. 53
And NAND circuits 3 and 4 corresponding to.

In FIG. 1, a data signal 101 is input from a data input terminal 51, and a clock signal 102 and a test switching signal 103 are input from a clock input terminal 52 and a test switching terminal 53, respectively. In response to the input of the clock signal 102 and the test switching signal 103, the NAND circuits 17 and 19 output signals 104 and 105 as control signals for the corresponding transfer gates. in this case,
The NAND circuits 3 and 4 both have the same function as the inverter. Therefore, when the test switching signal 103 is at "H" level, the operation of this embodiment is the same as that of the above-mentioned conventional example. The same operation is performed, and the circuit operates as a normal flip-flop circuit.

Therefore, when the test switching signal 103 is set to "H" level and the clock signal 102 is at "L" level, the signal 104 output from the NAND circuit 3 is "H".
The signal 105 output from the level / NAND circuit 4 is output as an “L” level signal and input to the corresponding gates of the transfer gates 6, 7, 11 and 12, respectively. In this case, transfer gates 6 and 12 are in a signal passing state, and transfer gates 7 and 11 are in a signal blocking state. Therefore, the data signal 101 is inverted by the inverter 5, input to the inverter 8, further inverted by the inverter 8, and output from the master latch 1. That is, the data signal 1
01 is taken into the master latch 1 and input to the slave latch 2 when the clock signal 102 is at “L” level and the test switching signal 103 is at “H” level.

Next, when the test switching signal 103 is kept at "H" level and the clock signal 102 shifts to "H" level, the signal 104 is at "L" level and the signal 105 is at "H" level.
Is output as an "H" level signal and input to the corresponding gates of the transfer gates 6, 7, 11 and 12, respectively. In this case, transfer gate 6
And 12 are in the signal cutoff state, and transfer gates 7 and 11 are in the signal passing state. Therefore, the data signal 101 taken in by the master latch 1 when the clock signal 102 is at the "L" level is held at the same level and is input to the slave latch 30,
The data signal 1 is inverted by the inverter 10 and passes through the transfer gate 11 and the inverter 13.
It is output as 06 via the data output terminal 54. Therefore, when the clock signal 102 input from the clock input terminal 52 changes from "L" level to "H" level, the value of the data signal 101 immediately before that is
It is output from the data output terminal 54.

When the test switching signal 103 is at the "L" level, the signals 104 and 105 are both at the "H" level regardless of the level of the clock signal 102, and the slave latch 2 outputs the data output terminal. The data signal 106 output via the data input terminal 51
Is output as a data signal having the same value as the data signal 101 input from. That is, in the present embodiment, by setting the level of the test switching signal 103 to the “L” level, the data signal 101 input from the data input terminal 51 is irrespective of the level of the clock signal 102.
As it is, the data output terminal 54 as the data signal 106.
Will be output.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 2, in the present embodiment, AND circuits 20 and 22, an inverter 21, and a NOR circuit 23.
And a master latch 15 formed by 24 and
OR circuits 25 and 26 and NAND circuits 27 and 2
And a NA corresponding to the clock input terminal 56 and the test switching terminal 57.
It is configured to include an ND circuit 17, an inverter 18, and a NOR circuit 19.

In FIG. 2, the data signal 107 is input from the data input terminal 55, and the clock signal 108 and the test switching signal 109 are input from the clock input terminal 56 and the test switching terminal 57, respectively. In response to the input of the clock signal 108 and the test switching signal 109, the NAND circuit 17 and the NOR circuit 19 output signals 110 and 111 as control signals for the corresponding transfer gates.
When the test switching signal 109 is set to "H" level and the clock signal 108 is set to "L" level, the NAND circuit 17
The signal 110 output from the NOR circuit 19 and the signal 111 output from the NOR circuit 19 are both output as “H” level signals, and are ANDed with the AND circuits 20 and 22, respectively.
Input to circuits 25 and 26. In this case, the data signal 107 input from the data terminal 55
Are AND circuits 20 and 22, an inverter 21, and NO
The NOR circuits 23 and 24 output the inverted data signals 112 and 113 via the R circuits 23 and 24, respectively.
It is input to the OR circuits 25 and 26 included in 6 respectively.

In this case, since the signal 111 output from the NOR circuit 19 is at "H" level, in the slave latch 16, the NAND circuit 27 corresponds to the input of the above data signals 112 and 113. Than the data signal is not output, the data signal is
It is held at the same level. Next, when the level of the clock signal 108 is changed to "H" level while the level of the test switching signal 109 is kept at "H" level, the signals 110 and 111 output from the NAND circuit 17 and the NOR circuit 19 are both " The data signal 107 becomes the L ″ level, the data signal 107 is not taken into the master latch 15, and the data signal whose level is held is output from the NAND circuit 27 via the slave latch 16 and is output as the data signal 114. Terminal 5
8 is output. Therefore, the clock input terminal 56
When the input clock signal 108 changes from the “L” level to the “H” level, the value of the data signal 107 immediately before that is output from the data output terminal 58.

When the test switching signal 109 is at "L" level, the signal 110 is at "H" level and the signal 111 is at "L" regardless of the level of the clock signal 108.
The data signal 114, which becomes the level and is output from the slave latch 16 via the data output terminal 58, is output as a data signal having the same value as the data signal 107 input from the data input terminal 55. That is, in this embodiment, by setting the level of the test switching signal 109 to the “L” level, the data signal 107 input from the data input terminal 55 remains as it is regardless of the level of the clock signal 108. The data signal 114 is output from the data output terminal 58.

When the flip-flop circuits of the above-described first and second embodiments are connected in cascade with another combination circuit to form a system circuit, "L" is applied from the test switching terminal of the flip-flop circuit. By inputting the level test switching signal, the function of the flip-flop circuit is that the input data signal is output as it is from the data output terminal without intervening the sampling operation of the clock signal. For,
For example, when increasing the fault detection rate of the system circuit, it is not necessary to input a clock signal to the flip-flop circuit every time when another combination circuit is operated, and therefore, the clock signal is not necessary for the operation of the entire system circuit. Is unnecessary, the time required to create a test pattern for testing the combinational circuit forming the system circuit is significantly shortened, and the length of the test pattern can be shortened.

[0019]

As described above, according to the present invention, it becomes easy to increase the failure detection rate of the system circuit formed by being cascade-connected to another combination circuit, and the test pattern creation time for that can be increased. There is an effect that the test pattern length can be shortened and the test pattern length can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

1, 15, 29 Master latch 2, 16, 30 Slave latch 3, 4, 17, 27, 28 NAND circuit 5, 8, 9, 10, 13, 14, 18, 21, 31 to 3
3, 36 to 38, 41, 42 Inverter 6, 7, 11, 12, 34, 35, 39, 40 Transfer gate 19, 23, 24 NOR circuit 20, 22 AND circuit 25, 26 OR circuit

Claims (1)

[Claims] 1. A flip-flop circuit, which includes a master latch and a slave latch corresponding to a data input signal and is cascade-connected to another combination circuit to form a predetermined system circuit, wherein:
At least one flip-flop circuit is provided with test switching means for directly outputting a data output signal corresponding to the data input signal via a predetermined test switching signal without depending on a clock signal. Flip-flop circuit.