JPH0564082A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a sufficient output level from an imaging device even if the brightness of an object decreases by mixing plural information charges which occur at each picture element of an imaging device so as to increase the information charge quantity. CONSTITUTION:The cycle of a reset pulse RST2 which discharges information charges at an output part 5 of an image sensor 1 is set to be n times of the cycle of a horizontal transfer clock phiH which transfers and drives a horizontal transfer part 4, and the information charges equal to two picture elements are accumulated at output part 5 so as to take out a voltage value. Then the reset timing of timing reset pulse RST2 is set by shifting it by the amount equal to one cycle of the horizontal transfer clock phiH for each horizontal scanning period and the combination of picture elements which synthesize information charge is shifted by one picture element for each horizontal line at the output part 5. As a result, interlace scanning is also performed in a pseudo manner in the horizontal direction, and so, deterioration of horizontal resolution is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device having a CCD image sensor, and more particularly to improvement of light receiving sensitivity.

[0002]

2. Description of the Related Art In an image pickup device such as a television camera using a CCD image sensor, each scanning timing of the image sensor is set based on a television synchronizing signal according to a predetermined system, and an image corresponding to the television synchronizing signal system is set. A signal is created. For example, in the case of the NTSC system, the vertical scanning period is set to 1/60 seconds, the horizontal scanning period is set to 2/525 of the vertical scanning period, and a video signal in which video information is continuous in units of one horizontal scanning period is output. To be done.

FIG. 6 is a block diagram showing the basic structure of an image pickup apparatus using a CCD image sensor. The frame transfer CCD image sensor 1 includes an image pickup unit 2 that receives an image from a subject and generates information charges, a storage unit 3 that temporarily stores the information charges, and a horizontal transfer unit that horizontally transfers and outputs the information charges. 4, the information charges generated in the image pickup unit 2 are transferred to the storage unit 3 in each vertical scanning period, and are output from the storage unit 3 via the horizontal transfer unit 4 in each horizontal scanning period. On the output side of the horizontal transfer unit 4, an output unit 5 for converting the amount of information charges into a voltage value is provided, and the information charges output from the horizontal transfer unit 4 are accumulated in 1-bit units. this,
A vertical transfer clock generation circuit 6 and a horizontal transfer clock generation circuit 7 are connected to the image sensor 1, and a vertical transfer clock φ _{V of} four phases and a horizontal transfer clock of two phases are connected to the storage unit 3 and the horizontal transfer unit 4 of the image sensor 1, respectively. The transfer clock φ _H is supplied. A timing control circuit 8 for setting a vertical scanning period and a horizontal scanning period is connected to the transfer clock generating circuits 6 and 7, and the scanning timing of the image sensor 1 is associated with a predetermined television system. A reset pulse generation circuit 9 that operates in synchronization with the horizontal transfer clock generation circuit 7 is connected to the output section 5 of the image sensor 1, and a reset pulse RST synchronized with the horizontal transfer clock φ _H is applied. The output section 5 is provided with a diffusion region electrically independent from other regions called floating diffusion, and the information charges accumulated in the diffusion region are discharged to the charge discharging drain according to the reset pulse RST. Is configured. That is, since the output unit 5 accumulates the information charges transferred from the horizontal transfer unit 4 to the output unit 5 in the diffusion region in the output unit 5 and obtains the voltage value from the fluctuation of the potential of the diffusion region, the horizontal transfer is performed. The reset pulse RST is set so that each time the information charge of the section 4 is transferred to the output section 5, the information charge is discharged. Therefore,
An output whose potential fluctuates is obtained at a timing according to the reset pulse RST from the output section 5, and this output is taken into the sample hold circuit 10. The sampling pulse generation circuit 11 that supplies the sampling pulse SPL to the sample hold circuit 10 is synchronized with the horizontal transfer clock generation circuit 7 similarly to the reset pulse generation circuit 9 and samples at a timing slightly earlier than the reset timing of the reset pulse RST. Set the timing. As a result, only the voltage value corresponding to the amount of information charges output from the horizontal transfer unit 4 is extracted from the output voltage of the output unit 5,
It is output to the circuit in the next stage as a video signal.

In the image pickup apparatus as described above, the period in which the information charge for one screen is accumulated in the image pickup unit 2 is, for example, 1 /
Although it is set as 60 seconds, the accumulation period is 1/60 by discharging the information charges of the image pickup unit 2 at a specific timing.
It is possible to set it to less than a second. Therefore, for a bright subject, the information charge accumulation period is set to be short to prevent saturation of the image pickup unit 2 of the image sensor 1. On the contrary, for a dark subject, the accumulation period of the information charges is set to 1 by setting the accumulation period of the information charges over a plurality of vertical scanning periods.
/ 60 seconds or more, and is configured to compensate for the underexposure. In this case, since the information charges are transferred from the imaging unit 2 to the storage unit 3 every one vertical scanning period, the output of the image sensor 1 is obtained every one vertical scanning period. Therefore, the output of the image sensor 1 is subjected to a process of interpolating the signal in units of vertical scanning period. An image pickup apparatus having such an exposure control function is proposed, for example, by the present applicant in Japanese Patent Application No. 63-66330.

[0005]

However, when interpolation is performed on the output of the image sensor 1, a field memory for storing signals for one screen is required, which causes a problem that the circuit scale becomes large. ing. Therefore,
By combining the information charges of two pixels of the image pickup unit 2,
It has been considered to increase the amount of information charges to improve the apparent sensitivity of the image sensor 1. When synthesizing the information charges of two pixels, a method of synthesizing the information charges in the transfer process of the information charges and a method of synthesizing the information charges at the time of conversion into a voltage value at the output unit 5 are used. When the information charges are combined in the transfer process, two pixels in the vertical direction are combined by operating the horizontal transfer unit 4 every other horizontal scanning period, for example. In this case, since the output of the image sensor 1 is obtained every other horizontal scanning period, it is necessary to interpolate the output of the image sensor 1 for each horizontal scanning period. On the other hand, when synthesizing the information charges in the output section 5, the charge discharging operation of the output section 5 is set to a cycle twice as long as the transfer operation of the horizontal transfer section 4, so that the information charges of two pixels are output to the output section 5. It is configured to accumulate and convert to a voltage value.

When an image signal is obtained by combining the information charges of a plurality of pixels as described above, the apparent sensitivity is improved due to an increase in the output level from the image sensor 1, but a mixture of a plurality of pixels is used. Due to the decrease in the amount of information, the resolution decreases. In particular, regarding the resolution in the horizontal direction, it is difficult to compensate for the decrease in resolution by the conventional interlace drive, which is an obstacle to improving the image quality of the playback screen.

Therefore, an object of the present invention is to provide a solid-state image pickup device capable of improving the sensitivity while preventing the deterioration of the resolution.

[0008]

The present invention has been made to solve the above problems, and is characterized in that each output of a plurality of vertical transfer units arranged in parallel to each other is horizontal. A solid-state image sensor that is coupled to each bit of the transfer unit, receives the output of the horizontal transfer unit at the output unit, and outputs a voltage value according to the amount of charge accumulated in the output unit; The information charges are transferred to the horizontal transfer unit for each horizontal line, further transferred from the horizontal transfer unit to the output unit, and then the information charges accumulated in the output unit are synchronized with the transfer operation of the horizontal transfer unit. Drive means for discharging
A detection unit that extracts the voltage value output from the output unit in synchronism with the discharging operation of the driving unit, wherein the driving unit determines the cycle of the discharging operation of the output unit from the transfer operation of the horizontal transfer unit. In addition to being set to an integral multiple of the cycle, the discharge operation timing of the output section is set to be shifted for each horizontal scanning period by one cycle of the transfer operation of the horizontal transfer section.

[0009]

According to the present invention, the discharge operation timing of the output section is set to be shifted for each horizontal scanning period by one cycle of the transfer operation of the horizontal transfer section, whereby the information charges combined in the output section are set. The pixel combination of 1 shifts by 1 pixel in each horizontal line, and the video signal obtained from the element shifts by 1 pixel for each horizontal line. Therefore, when the video signal is reproduced, pseudo interlaced display is performed in the horizontal direction.

[0010]

1 is a block diagram showing an embodiment of a solid-state image pickup device of the present invention. In this figure, the image sensor 1 and its drive circuit (vertical transfer clock generation circuit 6 and horizontal transfer clock generation circuit 7) are the same as in FIG.
The vertical transfer clock φ _V and the horizontal transfer clock φ _H according to the scanning timing set by the timing control circuit 8.
Are supplied to the image sensor 1 to be driven.

The feature of the present invention resides in that the reset pulse RST ₂ having a cycle of n times the horizontal transfer clock φ _H (n is an integer) is applied to the output section 5 of the image sensor 1 so that the horizontal transfer section is The purpose is to accumulate the information charges output from No. 4 in the output unit 5 every n pixels and convert them into voltage values. FIG. 2 is a timing chart showing an operation in the case where the output section 5 combines the information charges of three pixels by setting the cycle of the reset pulse RST ₂ to be three times the horizontal transfer clock φ _H.

The reset pulse RST ₁ having the same cycle as the horizontal transfer clock φ _H is generated by the reset pulse generating circuit 9
Is outputted from the frequency dividing circuit 12, and after being divided by 1/3 by the frequency dividing circuit 12, it is supplied to the output section 5 as a reset pulse RST ₂ having a period three times as long as the horizontal transfer clock φ _H. Therefore, the discharge operation of the output unit 5 has a cycle three times as long as the transfer operation of the horizontal transfer unit 4, and the information charges of three pixels in the horizontal direction are accumulated in the output unit 5.

In the frequency dividing operation of the reset pulse RST _{2 in} the frequency dividing circuit 12, in response to the field discriminating signal inverted every field (every vertical scanning period), in the odd field ODD, every horizontal scanning period. performed in one cycle delayed timing of the horizontal transfer clock phi _H, is performed at the timing advance one cycle of the horizontal transfer clock phi _H for each horizontal scanning period in the even field EVEN.
Therefore, the reset pulse RST supplied to the output unit
_As shown in FIG. 2, ₂ has different phases in the 3nth horizontal scanning period, the (3n + 1) th horizontal scanning period, and the (3n + 2) th horizontal scanning period.
For example, in the case of the odd field ODD, the frequency dividing circuit 12 is reset at the rising edge of the horizontal scanning signal HD in the 3nth horizontal scanning period, and from the rising edge of the horizontal scanning signal HD at the (3n + 1) th horizontal transfer clock φ _H. The frequency dividing circuit 12 is reset with a delay of one cycle of the horizontal transfer clock φ _H , and in the (3n + 2) th horizontal scanning period, the horizontal transfer clock φ starts from the rising edge of the horizontal scanning signal HD.
The frequency dividing circuit 12 is reset with a delay of two cycles of _H. According to such a reset pulse RST ₂ , the information charge discharging operation of the output section 5 is different from the transfer operation of the horizontal transfer section 4 in the horizontal transfer clock φ _H for each horizontal scanning period.
Therefore, the combination of pixels combined in the output unit 5 is shifted by 1 pixel for each horizontal line.

The output from the output section 5 is taken into the sample hold circuit 10. The timing of the sampling operation is set so as to correspond to the discharging operation of the output section 5. Therefore, the sampling pulse SLP ₁ output from the sampling pulse generating circuit 11 is divided into 1/3 by the frequency dividing circuit 13,
It is supplied to the sample hold circuit 10 as a sampling clock SLP ₂ having a cycle three times as long as the horizontal transfer clock φ _H. Further, as in the case of FIG. 6, the sampling timing needs to be slightly earlier than the timing of discharging the information charges of the output section 5, so that the sampling clock SLP ₁ is slightly different from the reset pulse RST ₁ . The advanced phase is set.

By combination with interlaced scanning, as shown in FIG. 3, in the odd field, the pixel O of the odd line is represented by the same data for every three pixels surrounded by the broken line, and in the even field, the even line. The pixel E of 3 is represented by the same data for every 3 pixels surrounded by the broken line. Therefore,
Since the interlaced scanning is performed in the vertical direction and the pseudo interlaced scanning is also performed in the horizontal direction, the deterioration of the resolution in the horizontal direction is suppressed even though the information charges of three pixels are combined in the horizontal direction. It

FIG. 4 is a diagram showing a combined state of information charges when the information charges of two pixels are combined, and FIG. 5 is an operation timing in that case. In this case, the frequency dividing circuit 12
The frequency dividing operation of the reset pulse RST ₁ is set to be shifted by one cycle of the horizontal transfer clock φ _H for each horizontal scanning period. That is, in the odd-numbered horizontal scanning period, the frequency dividing circuit 12 is reset at the rising of the horizontal scanning signal HD,
In the even-numbered horizontal scanning period, the reset circuit R is reset by resetting the frequency dividing circuit 12 with a delay of one cycle of the horizontal transfer clock φ _H from the rising of the horizontal scanning signal HD.
As shown in FIG. 5, the reset timing of ST ₂ is set to be offset from each other by one cycle of the reset pulse RST ₁ in each horizontal scanning period. At this time, the sampling pulse S
Similarly to the reset pulse RST ₂ , the frequency dividing operation of the frequency dividing circuit 13 is set so that the sampling timing of LP ₂ is shifted by one period of the horizontal transfer clock φ _H for each horizontal scanning period. In this way, when synthesizing the information charges of two pixels, the reset pulse RST ₂ of the resolution must be the same when the reset pulse RST ₂ is delayed by one cycle of the horizontal transfer clock φ _H and when it is advanced in the opposite direction. Therefore, the reset pulse RST ₂ of the odd field ODD and the even field EVEN are the same.

In the above embodiments, the case where the information charges of 3 or 2 pixels are combined has been exemplified, but it is also possible to combine the information charges of 4 pixels or more. In that case, the reproduction screen becomes considerably rough, but the roughness of the reproduction screen becomes less noticeable by the high-resolution image pickup device having a fine pixel pitch.

[0018]

As described above, according to the present invention, it is possible to realize an image pickup device having high sensitivity and high resolution by increasing the sensitivity of the image pickup device and suppressing the deterioration of the resolution due to the improvement of the sensitivity. Further, since the image pickup element itself having the same structure as that of the conventional one can be adopted, the sensitivity can be easily improved by changing the scanning timing of the drive circuit, so that the cost increase can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a solid-state imaging device of the present invention.

FIG. 2 is a timing chart showing a first operation of the solid-state imaging device of the present invention.

FIG. 3 is a schematic diagram showing a combined state of first pixels.

FIG. 4 is a schematic diagram showing a combined state of second pixels.

FIG. 5 is a timing chart showing a second operation of the solid-state imaging device of the present invention.

FIG. 6 is a block diagram showing a conventional solid-state imaging device.

[Explanation of symbols]

 1 image sensor 2 image pickup unit 3 storage unit 4 horizontal transfer unit 5 output unit 6 vertical transfer clock generation circuit 7 horizontal transfer clock generation circuit 8 timing control circuit 9 reset pulse generation circuit 10 sample hold circuit 11 sampling pulse generation circuit 12, 13 minutes Circuit

Claims (2)

[Claims] 1. Outputs of a plurality of vertical transfer units arranged in parallel to each other are coupled to respective bits of a horizontal transfer unit, and outputs of the horizontal transfer unit are received by an output unit and stored in the output unit. A solid-state imaging device that outputs a voltage value according to the amount of electric charge, and the information charges in the vertical transfer unit are transferred to the horizontal transfer unit for each horizontal line, and further transferred from the horizontal transfer unit to the output unit. Driving means for discharging the information charges accumulated in the output portion in synchronization with the transfer operation of the horizontal transfer portion, and detection for extracting the voltage value output from the output portion in synchronization with the discharge operation of the driving means The driving means sets the cycle of the discharging operation of the output section to an integral multiple of the cycle of the transfer operation of the horizontal transfer section, and sets the timing of the discharging operation of the output section for each horizontal scanning period. Of the above horizontal transfer section A solid-state imaging device, which is set by shifting the transfer operation for one cycle. 2. The timing of the discharging operation of the output section
Delay every odd horizontal scanning period in the vertical scanning period,
The solid-state imaging device according to claim 1, wherein the even-numbered vertical scanning period is set to advance every horizontal scanning period.