JP2642807B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device provided with a CCD image sensor, and more particularly to improvement of light receiving sensitivity.

[0002]

2. Description of the Related Art In an image pickup apparatus such as a television camera using a CCD image sensor, each scanning timing of the image sensor is set based on a television synchronization signal according to a predetermined method, and an image corresponding to the television synchronization signal method is set. A signal is created. For example, in the case of the NTSC system, the vertical scanning period is set to 1/60 second, the horizontal scanning period is set to 2/525 of the vertical scanning period, and a video signal in which video information is continuous in one horizontal scanning period is output. Is done.

FIG. 7 is a block diagram showing a basic configuration of an image pickup apparatus using a CCD image sensor. A frame transfer type CCD image sensor 1 includes an imaging unit 2 that receives information from a subject and generates information charges, a storage unit 3 that temporarily stores information charges, and a horizontal transfer unit that transfers and outputs information charges in the horizontal direction. The information charges generated in the imaging unit 2 are transferred to the storage unit 3 in each vertical scanning period, and output from the storage unit 3 via the horizontal transfer unit 4 every horizontal scanning period. On the output side of the horizontal transfer unit 4, an output unit 5 for converting the amount of information charges into a voltage value is provided, and the information charges output from the horizontal transfer unit 4 are accumulated in 1-bit units. this,
A vertical transfer clock generation circuit 6 and a horizontal transfer clock generation circuit 7 are connected to the image sensor 1, and a four-phase vertical transfer clock φ _V and a two-phase horizontal transfer clock are respectively supplied to the storage unit 3 and the horizontal transfer unit 4 of the image sensor 1. The transfer clock φ _H is supplied. A timing control circuit 8 for setting a vertical scanning period and a horizontal scanning period is connected to the transfer clock generation circuits 6 and 7, and the scanning timing of the image sensor 1 is associated with a predetermined television system. Further, the output unit 5 of the image sensor 1 is connected to the reset pulse generating circuit 9 which operates in synchronization with a horizontal transfer clock generating circuit 7, a reset pulse RST in synchronization with the horizontal transfer clock phi _H is applied. The output section 5 is provided with a diffusion region which is electrically independent of another region called a floating diffusion, and information charges accumulated in this diffusion region are discharged to a charge discharging drain in accordance with a reset pulse RST. It is configured to be. That is, the output unit 5 accumulates the information charges transferred from the horizontal transfer unit 4 to the output unit 5 in the diffusion region in the output unit 5 and obtains the voltage value from the fluctuation in the potential of the diffusion region. The reset pulse RST is set so that each time the information charges of the section 4 are transferred to the output section 5, the information charges are discharged. Therefore,
An output whose potential fluctuates at a timing corresponding to the reset pulse RST is obtained from the output unit 5, and this output is taken into the sample and hold circuit 10. The sampling pulse generation circuit 11 that supplies the sampling pulse SPL to the sample and hold circuit 10 synchronizes with the horizontal transfer clock generation circuit 7 like the reset pulse generation circuit 9 and performs sampling at a timing slightly earlier than the reset timing of the reset pulse RST. Set the timing. Thereby, only the voltage value corresponding to the information charge amount output from the horizontal transfer unit 4 out of the output voltage of the output unit 5 is extracted,
The video signal is output to the next circuit.

In the above-described image pickup apparatus, the period for accumulating information charges for one screen in the image pickup section 2 is, for example, 1 /
The storage period is set to 60 seconds, and the accumulation period is reduced to 1/60 by discharging the information charges of the imaging unit 2 at a specific timing.
It can be set to seconds or less. Therefore, for a bright subject, the accumulation period of the information charge is set to be short to prevent the imaging unit 2 of the image sensor 1 from being saturated. Conversely, for a dark subject, the accumulation period of the information charges is set over a plurality of vertical scanning periods, so that the accumulation period is set to one.
/ 60 seconds or more to compensate for the lack of exposure. In this case, since the transfer of the information charges from the imaging unit 2 to the storage unit 3 is performed every other vertical scanning period, the output of the image sensor 1 is obtained every other vertical scanning period. Therefore, the output of the image sensor 1 is subjected to a signal interpolation process in units of the vertical scanning period. An imaging device having such an exposure control function is proposed by the present applicant in Japanese Patent Application No. 63-66330, for example.

[0005]

However, when interpolation is performed on the output of the image sensor 1, a field memory for storing a signal for one screen is required, and there is a problem that the circuit scale becomes large. ing. Therefore,
By combining information charges for two pixels of the imaging unit 2,
It has been considered that the apparent sensitivity of the image sensor 1 is improved by increasing the information charge amount. When combining information charges for two pixels, a method of combining information charges in a transfer process or a method of combining information charges at the time of conversion into a voltage value in the output unit 5 is used. When information charges are combined in the transfer process, two pixels in the vertical direction are combined, for example, by operating the horizontal transfer unit 4 every other horizontal scanning period. In this case, since the output of the image sensor 1 is obtained every other horizontal scanning period, it is necessary to interpolate the output of the image sensor 1 every horizontal scanning period. On the other hand, when information charges are synthesized by the output unit 5, by setting the discharge operation of the output unit 5 to twice the period of the transfer operation of the horizontal transfer unit 4, the information charges of two pixels are output to the output unit 5. It is configured to accumulate and convert to a voltage value.

As described above, when a video signal is obtained by synthesizing information charges of a plurality of pixels, the apparent sensitivity is improved by an increase in the output level from the image sensor 1. , The resolution decreases due to the decrease in the amount of information. In particular, with respect to the resolution in the horizontal direction, it is difficult to compensate for the decrease in resolution by the conventional interlace driving, and this is an obstacle to improving the image quality of the reproduced screen.

Accordingly, an object of the present invention is to provide a solid-state imaging device capable of improving sensitivity while preventing a decrease in resolution.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that each output of a plurality of vertical transfer units arranged in parallel to each other is horizontally transferred. A solid-state image sensor that receives an output of the horizontal transfer unit at an output unit and outputs a voltage value corresponding to the amount of electric charge stored in the output unit, and outputs the voltage value from the output unit. A sample-and-hold circuit for sequentially extracting voltage values from the vertical transfer unit, transferring the information charges in the vertical transfer unit to the horizontal transfer unit for each horizontal line in a first cycle, and further outputting the output from the horizontal transfer unit in a second cycle. A transfer clock generation circuit for transferring the transfer pulse to the transfer clock generation circuit, a reset pulse generation circuit for generating a reset pulse in synchronization with a second cycle of the transfer clock generation circuit, and a sampling pulse in synchronization with the reset pulse. A sampling pulse generating circuit, and a frequency dividing circuit that divides the reset pulse and the sampling pulse by そ れ ぞ れ and supplies the frequency to the output section and the sample and hold circuit, respectively. The timing of the circumference may be shifted by a certain period every vertical scanning period or every horizontal scanning period.

[0009]

According to the present invention, the timing of the discharging operation of the output unit is shifted from the timing of the output operation in the odd field and the even field by one period of the transfer operation of the horizontal transfer unit, so that the output unit synthesizes the data. Since the combination of the pixels of the information charge is inverted for each field, the video signal obtained from the element is shifted by a half pixel (substantially one pixel) in the horizontal direction between the odd field and the even field, and the horizontal The race is scanned.

[0010]

FIG. 1 is a block diagram showing an embodiment of a solid-state imaging device according to the present invention, and FIG. 2 is an operation timing diagram thereof. In this figure, the image sensor 1 and its driving circuits (vertical transfer clock generation circuit 6 and horizontal transfer clock generation circuit 7) are the same as those in FIG. 7, and the vertical transfer is performed according to the scanning timing set by the timing control circuit 8. The clock φ _V and the horizontal transfer clock φ _H are supplied to the image sensor 1 for driving.

A feature of the present invention is that a reset pulse RST ₂ having a period twice as long as the horizontal transfer clock φ _H.
Is applied to the output unit 5 of the image sensor 1,
The information charge output from the horizontal transfer unit 4 is stored in the output unit 5 every two pixels and converted into a voltage value. Reset pulse RST ₁ having the same cycle as horizontal transfer clock φ _H
Is output from the reset pulse generating circuit 9, and after being divided by に よ り by the frequency dividing circuit 12, the horizontal transfer clock φ
It is supplied to the output section 5 as a reset pulse RST ₂ having twice the period of _H. Therefore, the discharge operation of the output unit 5 has a cycle twice as long as the transfer operation of the horizontal transfer unit 4, and the output unit 5 accumulates information charges for two pixels in the horizontal direction.
Furthermore, the dividing operation of the reset pulse RST ₂ in dividing circuit 12, in response to a field identification signal FLD is inverted every field (vertical scanning), shifted by one cycle of the horizontal transfer clock phi _H in each field Set to timing. For example, in the odd field (ODD), resets the divider circuit 12 at the rising edge of the horizontal scanning signal HD, the even field (EVEN), delayed by one cycle of the horizontal transfer clock phi _H from the rise of the horizontal scanning signal HD by minute The circuit 12 is configured to be reset. Therefore, the reset pulse RST ₂ supplied to the output unit 5 is
As shown in FIG. 2, it is set offset period of one cycle of the reset pulse RST ₁ together with the odd and even fields. According to such a reset pulse RST _2, since the discharge operation of the information charges of the output section 5 is shifted by one period of the horizontal transfer clock phi _H in each field to the transfer operation of the horizontal transfer section 4, the output unit 5 The combination of pixels to be combined is inverted for each field.
That is, in the odd field, the voltage value is extracted after the information charge of the next bit is mixed with the information charge of the bit of the odd column, and in the even field, the information charge of the bit of the even column is combined with the information charge of the next bit. After the mixing, a voltage value corresponding to the information charges for two pixels is output from the output unit 5. The output from the output unit 5 is taken into the sample and hold circuit 10, and the timing of this sampling operation is set so as to correspond to the discharge operation of the output unit 5. Therefore, the sampling pulse SLP output from the sampling pulse generation circuit 11
₁ is 1/2 divided by frequency divider 13, is supplied to the sample hold circuit 10 as a sampling clock SLP ₂ having twice the period of the horizontal transfer clock phi _H. The timing of sampling is shown in FIG.
As in the case of, since it is necessary to slightly earlier than discharge timing of the information charges of the output section 5, the sampling clock SLP ₁ is set to a slightly advanced phase with respect to the reset pulse RST _1.

In combination with interlaced scanning, as shown in FIG. 3, in an odd field, an odd line pixel O is represented by the same data every two pixels surrounded by a broken line, and in an even field, an odd field pixel O is displayed. In the state shifted by one pixel in the horizontal direction, the pixel E on the even-numbered line is represented by the same data every two pixels surrounded by a broken line. Accordingly, the interlaced scanning is performed in the vertical direction and the interlaced scanning is performed in the horizontal direction at the same time, so that the resolution in the horizontal direction is reduced despite the information charges of two pixels being combined in the horizontal direction. Be suppressed.

Incidentally, the cycle of inverting the combination of pixels synthesized in the output unit 5 can be performed in units of horizontal scanning periods in addition to the unit of vertical scanning periods. In this case, the reset pulse R in the frequency dividing circuit 12
Dividing operation of the ST ₁ is set offset for each horizontal scanning period by one period of the horizontal transfer clock phi _H. That is, the odd-numbered horizontal scanning period, to reset the divider circuit 12 at the rising edge of the horizontal scanning signal HD, the even-numbered horizontal scanning period, 1 period of the horizontal transfer clock phi _H from the rise of the horizontal scanning signal HD by resetting the minute delay dividing circuit 12, the reset timing of the reset pulse RST ₂ is, as shown in FIG. 3, is set shifted by one period of the reset pulse RST ₁ together with every horizontal scanning period. At this time, drawing on even sampling pulse SLP _2, dividing operation of the reset pulse RST ₂ sampling timing for each horizontal scanning period in the same manner as the horizontal transfer clock phi _H for one period shifted as frequency divider 13 is set FIG. 2 is a block diagram showing another embodiment of the present invention.

In FIG. 1, an image sensor 1, a vertical transfer clock generation circuit 6, and a horizontal transfer clock generation circuit 7
The timing control circuit 8 is the same as that of FIG. 1, and the same parts are denoted by the same reference numerals. Here, the feature is that the information charges are synthesized in the output unit 5 of the image sensor 1 in accordance with the exposure state of the image sensor 1.

That is, an exposure judgment circuit 14 for judging the exposure state of the image sensor 1 from the output level of the sample hold circuit 10 is provided, and a reset pulse RST ₁ and a sampling pulse SLP ₁ are provided in accordance with the judgment result of the exposure judgment circuit 14. Is configured to vary the frequency division ratio of frequency dividing circuits 15 and 16 for dividing the frequency. The exposure determining circuit 14 integrates, for example, the output of the sample-and-hold circuit 10 on a screen-by-screen basis, and when the integrated value becomes lower than a predetermined reference value, determines that the easy sensor 1 is underexposed.
The division ratios of 5 and 16 are changed from 1 to 1/2. As a result, when the brightness of the subject is reduced and the image sensor 1 is underexposed, the frequency division ratios of the frequency dividing circuits 15 and 16 are set to 1/2, and the information charges for two pixels are synthesized by the output unit 5. Will be. The operation of each unit when the discharge operation of the information charges in the output unit 5 is set to a half cycle of the transfer operation of the horizontal transfer unit 4 is the same as that in FIG. 1 and the description is omitted.

Accordingly, the sensitivity of the image sensor 1 is automatically increased in response to the decrease in the brightness of the subject, so that the operability of the imaging device is improved and the dynamic range of the imaging device is expanded.

[0017]

According to the present invention, a high-sensitivity and high-resolution imaging apparatus can be realized by increasing the sensitivity of the imaging apparatus and suppressing the decrease in resolution due to the improvement in sensitivity. In addition, since the image sensor itself can have the same structure as the conventional one, the sensitivity can be easily improved by changing the scanning timing of the drive circuit, so that an increase in cost can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart showing a first operation of FIG. 1;

FIG. 3 is a schematic diagram showing a pixel combination state.

FIG. 4 is a timing chart showing a second operation of FIG. 1;

FIG. 5 is a schematic diagram illustrating a pixel combination state.

FIG. 6 is a circuit diagram showing another embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional solid-state imaging device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image sensor 2 Image pick-up part 3 Storage part 4 Horizontal transfer part 5 Output part 6 Vertical transfer clock generation circuit 7 Horizontal transfer clock generation circuit 8 Timing control circuit 9 Reset pulse generation circuit 10 Sampling pulse generation circuit 11 Sample hold circuits 12, 13, 15, 16 frequency divider circuit 14 Exposure judgment circuit

Claims (1)

(57) [Claims] An output of a plurality of vertical transfer units arranged in parallel with each other is coupled to each bit of a horizontal transfer unit, an output of the horizontal transfer unit is received by an output unit, and the output of the horizontal transfer unit is stored in the output unit. A solid-state imaging device that outputs a voltage value corresponding to the amount of electric charge, and a voltage value output from the output unit.
Sample and hold circuit and the information
The load is transferred to the horizontal transfer unit for each horizontal line in the first cycle.
And the output from the horizontal transfer unit in a second cycle.
Transfer clock generation circuit for transferring data to the
A reset pulse is issued in synchronization with the second cycle of the clock generation circuit.
Reset pulse generation circuit and reset pulse
Sampling that generates a sampling pulse in synchronization with
A pulse generation circuit, the reset pulse and the sump,
Each of the ring pulses is frequency-divided at a predetermined ratio, and
And a frequency divider circuit for supplying the sample and hold circuit,
And the timing of the frequency division of the frequency dividing circuit is set in the vertical scanning period.
A solid-state imaging device characterized in that a certain period is shifted every interval or every horizontal scanning period .