JPH0560185B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic disk device, and more particularly to a write clock circuit that generates a write clock signal used during recording.

[Conventional technology]

Conventionally, this type of magnetic disk device has been able to control the writing and reading of recorded data only at a specific write clock frequency proportional to the servo clock written in advance, and the connected system side has to select the write clock frequency. Alternatively, it was not possible to select the data storage capacity per track.

[Problem that the invention seeks to solve]

An object of the present invention is to output a write clock signal having an arbitrary divided or multiplied frequency with respect to a servo clock signal unique to the device, and to enable flexible track storage capacity and data transfer speed. The object of the present invention is to provide a magnetic disk device with the following features.

[Means for solving problems]

According to the present invention, there is provided a first clock frequency dividing circuit which inputs a servo clock based on a servo surface signal and is capable of performing arbitrary binary value frequency division, and a second clock frequency dividing circuit which enables arbitrary binary value frequency division of a self-oscillating clock. It has a write clock circuit consisting of two clock frequency dividers, a phase comparison circuit that compares the output signals from these two clock frequency dividers, and a variable frequency oscillation circuit whose output is used as an oscillation frequency control input. A magnetic disk device having the following characteristics is obtained.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, the embodiment of the present invention includes a magnetic disk assembly 1 composed of a plurality of magnetic disks, a spindle motor 2 fixed to the rotating shaft of the magnetic disk, and each data surface of the magnetic disk assembly 1. , has a data head assembly 3 and a servo head 4 disposed in the servo plane and secured together on a positioner 5. A motor drive circuit 10 is connected to the spindle motor 2 and performs rotational driving. The positioner drive circuit 20 receives a position sense signal from the servo head 4 and drives the positioner 5 to position it.
The write/read circuit 30 is connected to the data head assembly 3 and preamplifies the write signal, amplifies the read signal, and converts it into a pulse signal. The data modulation/demodulation circuit 40 is located between the write/read circuit 30 and the interface circuit 50 and modulates write data and demodulates read data. The interface circuit 50 is located between the positioner drive circuit 20, the data modulation circuit 40, the logic signal gate circuit 80, and the host control device 100, and is connected via the interface I. The write clock circuit 60 inputs the servo clock signal S from the positioner drive circuit 20 and the clock control signal group C _o from the logic signal gate circuit 80, and outputs the write clock signal W to the data modulation circuit 40 and the read clock circuit 70. . Read clock circuit 70 receives input signals from write/read circuit 30, write clock circuit 60, and logic signal gate circuit 80, and sends an output signal to data modulation/demodulation circuit 40. The logic signal gate circuit 80 receives control signals from the interface circuit 50 and the manual switch circuit 90,
Either one of the control signals is sent to the motor drive circuit 10,
Positioner drive circuit 20, write clock circuit 60
and sends it to read clock circuit 70.

Next, a more detailed configuration of the write clock circuit 60, which can vary the output clock frequency, will be explained with reference to FIGS. 2 and 3.

Referring to FIG. 2, the write clock circuit 60 includes a variable frequency oscillation circuit 61 which outputs a write clock signal W, and a frequency-divided clock signal W which receives the write clock signal W and a clock control signal group C _o as inputs. a _clock frequency divider circuit 62a that outputs a frequency-divided clock signal Sd, and a clock frequency divider circuit 6 that receives a servo clock signal S and a clock control signal group _Co as input and outputs a frequency-divided clock signal _Sd .
2b, and a phase comparator circuit 63 which receives the divided clock signals W _d and S _d from the clock frequency dividers 62 a and 62 b and sends the error signal d to the variable frequency oscillation circuit 61 as an output.

Further referring to FIG. 3, each of the two clock frequency divider circuits 62a and 62b is a counter register that receives the write clock signal W or the servo clock signal S and outputs the divided clock signals _Wd and _Sd , respectively. circuits 65a and 65b, clock control signal group C _o and counter register circuit 6
A decoder circuit 66a receives the count output b of counter register circuits 65a and 65b as an input signal and sends out a preset signal P of counter register circuits 65a and 65b.
and 66b.

In addition, in Fig. 1, Fig. 2, and Fig. 3,
Although the clock control signal group _Co is shown as a simple connection, the control signal lines may be assigned differently for each functional block.

Next, an example of clock frequency conversion of the write clock circuit 60 shown in FIG. 2 will be explained with reference to FIG.

In the clock conversion example shown in FIG. 4, the input clock time ts given by the servo clock signal S is 1.5
Output clock time multiplied (frequency 2/3)
The case where the write clock signal W of tw is output is shown.

For the clock conversion operation shown in FIG.
As the clock control signal group C _o of the decoder circuits 66a and 66b of the clock frequency divider circuits 62a and 62b shown in the figure, the divided clock signal of the frequency divider circuit 62b of the servo clock signal S is used.
S _d is a hexadecimal count signal, and the frequency division clock signal of the frequency division circuit 62a of the write clock signal W is used.
A control logic level is set for W _d so that a quaternary count signal is obtained.

The frequency conversion selection control of the write clock circuit 60 described above is performed by a combination of a logic signal gate circuit 80 and a manual switch 90, as shown in FIG. This is possible using any control signal from the higher-level control device 100 via the circuit 50.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which the write clock frequency can be changed by the host controller or a manual switch, so that the host controller can determine the optimal per-track storage capacity or data transfer rate for each system. This has the effect of allowing you to choose.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a block circuit diagram of the write clock circuit shown in Figure 1, Figure 3 is a block circuit diagram of the clock frequency divider circuit shown in Figure 2, and Figure 4 is based on the functional configuration of Figure 2. 3 is a timing chart showing an example of clock conversion. 1...Magnetic disk assembly, 2...Spindle motor, 3...Data head assembly, 4...Servo head, 5...Positioner, 10...Motor drive circuit, 20...Positioner drive circuit, 30...Writing Readout circuit, 40...Data modulation/demodulation circuit, 50
...Interface circuit, 60...Write clock circuit, 61...Variable frequency oscillation circuit, 62a, 6
2b...Clock frequency divider circuit, 63...Phase comparison circuit, 65a, 65b...Counter register circuit,
66a, 66b...Decoder circuit, 70...Read clock circuit, 80...Logic signal gate circuit, 9
0...Manual switch circuit, 100...Upper control device, I...Tonface signal line, S...Servo clock signal, W...Write clock signal, _Co ...
...Clock control signal group.

Claims (1)

[Scope of Claims] 1. In a magnetic disk device having a servo signal read head and a data write/read head positioned on the surface of a magnetic disk and supported by a positioner, a servo clock of a constant cycle from the servo signal read head is input. a first clock frequency divider circuit which performs frequency division by an arbitrary binary value specified by the clock control signal; and a second clock frequency divider circuit which receives a self-generated clock and performs frequency division by an arbitrary binary value specified by the clock control signal. a second clock frequency divider circuit; a phase comparison circuit that compares the phase difference between the output signals from the first and second clock frequency divider circuits; a write clock circuit comprising a variable frequency oscillator circuit that generates a write clock signal whose timing is controlled by a write clock; and a write clock circuit that modulates write data using the write clock signal as a write clock, and A magnetic disk device comprising: a data modulation/demodulation circuit for providing data to a head;