JPH0556511B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to an integrated circuit for driving a dot matrix display device, and particularly to an integrated circuit for driving a dot matrix display device to which display information can be applied serially or in parallel. Concerning integrated circuits.

(B) Prior Art Generally, when displaying characters or figures on a dot matrix display device using liquid crystal, for example, a large number of X-axis electrodes are sequentially selectively driven based on a well-known liquid crystal dynamic driving method. , in the selected state, drive signals for selection or non-selection are applied to a large number of Y-axis electrodes. Here, the signals for driving the large number of Y-axis electrodes are created based on display information indicating lighting and non-lighting of the large number of dots connected to the X-axis electrode selected at that time.
A memory circuit is provided for supplying display information to the circuit driving the Y-axis electrode.

Conventionally, memory circuits for storing display information were
As shown in Japanese Patent Application No. 59-11916, a latch circuit or a parallel output shift register having a bit output equal to the number of Y-axis electrodes is used, and the contents of the memory circuit are read every time the selection state of the X-axis electrodes changes. For rewriting, a shift register is provided to receive and store new display information from the outside until the next X-axis electrode is selected. Then, the Y-axis electrode drive circuit, the memory circuit that stores display information, the shift register that stores display information for rewriting, etc. are integrated into an integrated circuit, and an IC dedicated to driving the Y-axis electrode of the dot matrix display device is created. It has been realized.

(c) Problems to be solved by the invention When driving a dot matrix display device using the aforementioned IC dedicated to driving the Y-axis electrode, display information is serially applied from one side and displayed using a synchronizing signal. Information was being shifted sequentially.

However, when applying display information serially, the number of IC terminals may be small, but there is a drawback that the shift operation to transfer the display information increases the power consumed by the shift register.
This has the disadvantage that it takes more time to shift all the displayed information.

On the other hand, when display information is applied in parallel, the display information transfer time is shortened, but there is a disadvantage that the number of terminals increases.

Furthermore, we have developed an IC for driving dot matrix display devices that can apply display information either serially or in parallel.
had not been realized.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and includes a drive circuit that creates m×n drive signals for driving dots of a dot matrix display device. ,
A display information storage circuit that supplies display information indicating lighting and non-lighting of dots to the drive circuit, and a display information storage circuit that sequentially accumulates display information applied from the outside and stores the display information in the display information storage circuit when all display information has been accumulated. In a dot display driving integrated circuit having a storage circuit that applies m bits of display information serially applied from the outside based on a synchronization signal,
A serial-to-parallel conversion circuit performs the operation of transferring this m-bit display information to the storage circuit, or inputs the m-bit display information in parallel and transfers the display information to the storage circuit, and the serial or m-bit A control circuit that controls the operation of the storage circuit based on a synchronization signal that is synchronized with the display information that is applied in parallel, and a serial-to-parallel conversion process that applies the display information serially and m bits in parallel. By providing a serial-parallel switching terminal for switching the operation of the circuit and control circuit, display information can be input in either serial or parallel mode.

(E) Effect According to the present invention, when a predetermined signal is applied to the serial-parallel switching terminal, the operation of the serial-parallel conversion circuit and the control circuit becomes a serial input operation, and the display information is transferred to the serial-parallel conversion circuit. When m-bit display information is input serially, the display information is transferred to the storage circuit. Also, when another signal is applied to the serial-parallel switching terminal, the operation of the serial-parallel conversion circuit and control circuit becomes parallel input operation,
The display information is input in m-bit parallel to the serial-parallel conversion circuit, and the input display information is transferred to the storage circuit. This allows serial input or parallel input.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, which is an integrated circuit for driving a liquid crystal dot matrix display device. In FIG. 1, a liquid crystal drive circuit 1 has outputs Y ₁ to Y ₈₀ capable of driving 80 Y-axis electrodes of a display device, and four types of externally applied voltages V ₁ and V. ₂ , V ₃ and V ₄ in memory circuit 2
Select based on 80 pieces of display information applied from
Send to outputs Y ₁ to _{Y 80} . The memory circuit 2 has each output
Display information indicating lighting and non-lighting of dots corresponding to _Y1 to _Y80 is stored and supplied to the liquid crystal drive circuit 1, and is composed of, for example, 80 latch circuits. The storage operation of the storage circuit 2 is controlled by the control signal LOAD applied to the external terminal 3, and the 80 pieces of display information stored in the storage circuit 4 are input at once at the falling edge of the control signal LOAD. Remember. The storage circuit 4 sequentially stores the 4-bit output of the serial-parallel conversion circuit 5 in units of 4 bits, for example, _L1 to _L80 .
Consists of 80 latch circuits. Furthermore, the latch operations of the latch circuits L ₁ to _{L 80} are controlled by the latch clocks φ ₁ to _{φ 20} output from the control circuit 6.
Latch circuits L ₁ to _{L 4} are controlled by latch clock φ ₁ , latch circuits L ₅ to _{L 8} are controlled by latch clock φ ₂ , latch circuits L ₇₇ to _{L 80} are controlled by latch clock φ ₂₀ , and so on every 4 bits. . The serial-to-parallel converter circuit 5 is composed of a 4-bit shift register that can be preset, the inputs of each bit are connected to input terminals 7, 8, 9, and 10, and the 4-bit output is applied to the storage circuit 4. Input terminals 7, 8,
Reference numerals 9 and 10 are parallel input terminals for 4-bit display information, and input terminal 7 is used as a serial input terminal for display information. The display information input and shift operation of the serial-parallel conversion circuit 5 is performed using the clock pulse CLK output from the control circuit 6.
The serial input operation and the parallel input operation are switched by a switching signal S/P applied to the serial-parallel switching terminal 11.
In the control circuit 6, the control signal LOAD is connected to the set terminal S.
is applied to the enable flip-flop 12, which memorizes the operable state by the rising edge of the enable flip-flop 12.
(hereinafter referred to as E-FF) and the output Q of E-FF12
is controlled by the AND gate 13, which outputs the synchronizing signal CP applied to the external terminal 24 in synchronization with the display information when the E-FF 12 is set, as a clock pulse CLK, and is reset by the control signal LOAD. , a quaternary counter 14 for counting clock pulses CLK, and an AND gate 15,
16, an OR gate 17, and an inverter 18, and the quaternary counter 14 is
a switching gate 19 that switches and outputs the output of the clock pulse CLK and a clock pulse CLK, a 20-decimal counter 20 that is reset by the control signal LOAD and counts the pulses output from the switching gate 19;
Decoder 2 receives an output of 0 and creates latch clocks φ ₁ to _{φ 20} based on the clock pulse CLK.
It consists of 1. In this control circuit 6, when the switching signal S/P is "0" and serial input is selected, the 20-decimal counter 20 counts the output of the quaternary counter 14, so four synchronizing signals CP are applied. When the 4-bit display information is shifted to the serial-parallel conversion circuit 5, the decoder 21 outputs one of the latch clocks φ ₁ to φ ₂₀ . Furthermore, when the parallel input is selected by the switching signal S/P being "1", the 20-decimal counter 20 counts the synchronizing signal CP, so one synchronizing signal CP is applied and the 4-bit parallel display information is serially displayed. When preset in the parallel conversion circuit 5,
The decoder 21 outputs one of the latch clocks φ ₁ to φ ₂₀ . Also, the 20 decimal counter 20 is 20
When the number of pulses is counted, the carry CAR is applied to the reset R of the E-FF 12 and the AND gate 22. The E-FF12 reset by the carry CAR receives a synchronization signal at the AND gate 13.
The CP is shut off, and the operations of the quaternary counter 14 and the 20-decimal counter 20 are stopped. Also, Cary
The AND gate 22 to which CAR is applied is the synchronization signal CP
is output from external terminal CPOUT23. This external terminal CPOUT23 becomes a terminal for supplying a synchronizing signal CP to the next stage when the dot display driving ICs shown in FIG. 1 are used in cascade connection.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.

FIG. 2 shows that when the switching signal S/P applied to the serial-parallel switching terminal 11 is set to "0",
That is, the case of serial input is shown. In this case, display information is serially applied to the input terminal 7, and a synchronization signal CP synchronized with the display information is applied to the external terminal 24. Since the switching signal S/P is "0", the serial-parallel conversion circuit 5 operates as a shift register that sequentially shifts the display information applied to the input terminal 7 for each pulse of the clock pulse CLK. 19 selects the output of the quaternary counter 14.
Therefore, first, control signal LOAD is applied to external terminal 3.
(pulse of "1"), the E-FF 12 is set, and the quaternary counter 14 receives the synchronizing signal CP,
That is, counting of clock pulses CLK is started.
When four clock pulses CLK are counted, the display information DATA1 to DATA4 for outputting the outputs _Y1 to _Y4 is shifted to the serial-parallel conversion circuit 5, while the 20-decimal counter 20 shifts the display information DATA1 to DATA4 to output the outputs Y1 to Y4. Count the output. As a result, decoder 2
1 outputs the latch clock _φ1 , and the 4-bit display information shifted to the serial-to-parallel converter circuit ₅ is output by the latch clock φ1.
DATA1 to DATA4 are latch circuits of storage circuit 4
Transferred to _L1 to _L4 and stored. Next, when four clock pulses CLK are counted, a clock pulse _φ2 is output, and the display information DATA5-DATA8 shifted to the serial-parallel conversion circuit 5 is transferred to the latch circuits _L5 - _L8 . By repeating the same operation, the display information is sequentially stored in the storage circuit 4, and when the display information DATA77 to DATA80 is transferred to the latch circuits _L77 to _L80 by the latch clock _φ20 , the output CAR of the 2decimal counter 20 E-
The FF 12 is reset and the operation of the control circuit 6 is stopped. From then on, the applied display information DATA81 is the synchronization signal output from the external terminal 23.
CPOUT is input to the next stage dot display driving IC. When the display information transfer is completed in this manner, the display information stored in the storage circuit 4 is stored in the storage circuit 2 by applying the control signal LOAD again.

FIG. 3 shows that when the switching signal S/P applied to the serial-parallel switching terminal 11 is set to "1",
That is, this is a case of parallel input. In this case, display information is applied in parallel to each of the input terminals 7, 8, 9, and 10, and a signal CP synchronized with the display information is applied to the external terminal 24. Since the switching signal S/P is "1", the serial-to-parallel conversion circuit 5 inputs the display information applied to the input terminals 7, 8, 9, and 10 at once, while the switching gate 19 receives the clock pulse CLK. is selected. Therefore, first, a control signal is sent to external terminal 3.
When LOAD (pulse of “1”) is applied, E-F
12 is set, and the synchronizing signal CP is output as the clock pulse CLK. The 20-decimal counter 20 is
Start counting this clock pulse CLK. 1
When the synchronous signal CP is applied, a clock pulse CLK is output, and the display information DATA1 to DATA4 applied to the input terminals 7, 8, 9, and 10 are preset in parallel to the serial-parallel conversion circuit 5. Ru. On the other hand, the clock pulse CLK is
It is counted by the 20-decimal counter 20, and the decoder 21 outputs a latch clock _φ1 . The display information DATA1-DATA4 preset in the serial-parallel conversion circuit 5 by the latch clock _φ1 is transferred to the latch circuits _L1 - _L4 of the storage circuit 4 and stored therein. Next, when the display information DATA5 to DATA8 and the synchronization signal CP are applied, the same operation is performed.
Display information output from latch clock _φ2 and preset to serial-parallel converter circuit 5
DATA5 to DATA8 are transferred to latch circuits _L5 to _L8 . Repeat the above steps to display the information
When DATA77 to DATA80 are transferred to the latch circuits _{L77 to L80} , the operation of the control circuit 6 is stopped by the output CAR of the 20-decimal counter 20. Thereafter, the applied display information DATA81 is inputted to the next stage dot display driving IC by means of the synchronizing signal CPOUT outputted from the external terminal 23. Then, when the display information transfer is completed, the display information stored in the storage circuit 4 is stored in the storage circuit 2 by applying the control signal LOAD again.

As is clear from FIGS. 2 and 3, the switching signal S/P applied to the serial-parallel switching terminal 11 switches between the serial input and the parallel input of the dot display driving IC.

(G) Effects of the Invention As described above, according to the present invention, serial input and parallel input of display information can be switched without significantly increasing the number of external terminals. It can support both input and parallel input, and has the advantage of improved functionality.
A high value dot display driving IC can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams showing the operation of the embodiment shown in FIG. Explanation of main drawing numbers, 1...Liquid crystal drive circuit, 2...
Memory circuit, 3, 23, 24... External terminal, 4...
Storage circuit, 5... serial-parallel conversion circuit,
6... Control circuit, 7, 8, 9, 10... Input terminal, 11... Serial-parallel switching terminal.

Claims (1)

[Claims] 1 A drive circuit that creates and outputs m×n drive signals to drive the dots of a dot matrix display device, and a drive circuit that generates and outputs m×n drive signals to drive the dots of a dot matrix display device, and a drive circuit that generates and outputs m×n drive signals to drive the dots of a dot matrix display device, and a drive circuit that generates and outputs m
A display information storage circuit that stores ×n pieces of display information and supplies it to the drive circuit, an accumulation circuit that sequentially stores display information applied from the outside in units of m bits, and a display information storage circuit that stores display information serially applied from the outside or in m bits. a serial-to-parallel conversion circuit which inputs display information applied in parallel and supplies display information to the storage circuit in units of m bits; and a synchronization signal synchronized with the display information applied serially or in parallel in m bits. a control circuit that controls the storage operation of the storage circuit based on the data, and a serial control circuit that switches the operation of the serial-to-parallel conversion circuit and the control circuit depending on whether the display information is applied serially or m bits in parallel. - An integrated circuit for driving a dot display, characterized in that it is equipped with a parallel switching terminal.