JPH0544039B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a Japanese-shaped segment liquid crystal display element used as a display section of electronic equipment such as calculators, personal computers, and various measuring instruments. Background technology Driving a liquid crystal display device (hereinafter referred to as LCD)
A multiplex system has conventionally been adopted as an effective system for performing this without increasing the number of drive signal lines as much as possible. This method requires the correct setting of the effective values Von and Voff of the applied voltage at the selection point (liquid crystal active part) and half-selection point (deactivation part) in order to obtain good display quality. There is a method of applying bias voltage, in this case 3
A voltage of at least one value is required (in addition to the on/off levels of the power supply voltage, the intermediate level is one or more values). For example, when adopting the above drive method for a battery-powered calculator, a 1/3 duty/1/3
It is driven by bias or 1/4 duty/1/3 bias, and solar battery powered calculators use the power supply voltage from the solar cell, this power supply voltage doubled by a booster circuit, and 3 values (intermediate level). It was driven with a voltage of 1/3 duty and 1/2 bias. By the way, in the case of the above-mentioned battery-powered calculator, although there is a problem that the current consumption increases because the intermediate voltage is obtained by dividing it by the bleeder resistor.
The circuit load of the bleeder resistor itself in the large-scale integrated circuit (hereinafter referred to as LSI) that constitutes the LCD drive circuit is negligible. On the other hand, in the case of a solar battery-powered calculator, the set current is less than 1/2 to 1/3 of the bleeder current in the case of a battery-powered calculator, so an intermediate level voltage is obtained by the bleeder resistor. method cannot be adopted. Therefore, in solar-powered calculators, two capacitors were mounted outside the LSI to form a boost circuit, which formed the power supply. Therefore, without using a booster circuit like the above-mentioned drive method that requires a bias voltage, the LCD
Conventionally, a so-called pulse control method has been developed as a method for duty-driving with a binary value (that is, a single power source). This method is shown in Figure 12 for the case of 1/2 duty drive.
~ The waveforms shown in Figure 12 5, and those shown in the case of 1/3 duty drive are shown in Figures 13 1 ~ 13.
This is the waveform of FIG. In the 1/2 duty drive shown in Fig. 12, the applied voltages H1 and H2 to the two common electrodes are
2. Given the waveforms shown in FIG. 1 and FIG. 12,
In the waveform of applied voltage H1, section h1 is the selected section, section
While h2 is a half-selected section, in the waveform of the applied voltage H2, conversely, the section h2 is given as a selected section and the section h1 is given as a half-selected section. Applied voltage Seg to the segment electrode in each selected section
When (01) (the waveform of which is shown in FIG. 12, 3) becomes a waveform that can activate the liquid crystal, the applied voltage between the segment electrode and the common electrode (the waveform of which is shown in FIG.
and its waveform is shown in FIG. - The voltage applied between the common electrodes takes an effective value Voff. Similarly, in FIG. 13 showing the waveform of 1/3 duty drive, section h1 is a selected section of the waveform of the common electrode applied voltage H1, section h2 is a selected section of the waveform of the common electrode applied voltage H2, and section h3
indicates the selected section of the waveform of the common electrode applied voltage H3. The operating margin α, that is, Von/Voff, which represents the display quality in this method, is α from 1/2 duty drive, when drive E = 1.5V, Von = 3/4E → 1.3V Voff = 1/4E → 0.75V. =Von/Voff=√3≒1.73, and in the case of 1/3 duty drive, Von=4/6E→1.22V Voff=2/6E→0.87V, so α=Von/Voff=√2≒1.41. There is. Similarly, a waveform for 1/4 duty driving can be created, but the operating margin α in this case is as small as 1.29. LCD
The contrast, that is, the display quality, is better as the operating margin α is larger, and in calculators, usually α=
Those with a value of 1.73 or higher are adopted. On the other hand, in LCD duty driving, the larger the value of the duty denominator, for example 1/3 than 1/2, and 1/4 than 1/3, the less signal is required to drive the same LCD display element. Therefore, if the same display quality can be obtained, it is desirable to use duty drive with a denominator value as large as possible. Problems to be Solved by the Invention However, as mentioned above, when using the conventional pulse control method in a calculator, the value of the operating margin α is limited from the viewpoint of display quality (contrast), so the 1/2 duty is limited. Due to limitations, 1/3 duty could not be adopted. On the other hand, solar-powered calculators use the 1/3 duty/1/2 bias method, which is commonly used in the past.
LCD driving requires a total of 27 drive signal lines to drive an 8-digit LCD, but if you try to do this with 1/2 duty drive using the conventional pulse control method described above, the drive signal lines will be 36 or more are required, which increases the chip size of the LSI constituting the drive circuit and the number of pins of the package, leading to an increase in cost. Especially film carrier (TAB; Tape Auto−mated)
When making an LSI package by bonding), the cost of glass epoxy resin film is reduced.
Since film accounts for a large proportion of LSI manufacturing costs, there is a desire to keep the amount of film used as small as possible. The film used in this film carrier LSI has various terminals 1a and 1 obtained by etching copper foil as shown in FIG.
b, 1c, and 1d are formed on the surface, while each section L1 of the film 2 corresponding to one LSI is formed.
An opening 3 is formed through which the LSI chip is exposed.
Further, along with each of the terminals 1a, 1b, 1c, and 1d, a copper foil connection line connected to these terminals and extending beyond the periphery of the opening 3 is formed at the same time.
Then, as shown in FIG. 15, the LSI is installed in the opening 3.
The film 2 is stretched over the substrate 5 with the chimp 4 facing, and each connection line 6 extending beyond the periphery of the opening 3 is connected to the LSI by wire bonding.
By connecting to chip 4, an LSI package is formed. In the arrangement example of a conventional film carrier LSI as shown in FIG. 14, the terminals 1a, .
(Actually, the length is determined as the number of sprocket pitch holes 2a). If the terminal pitch that can be arranged within one pitch section of the pitch hole 2a is, for example, 0.9 mm, then the LCD
To arrange 31 terminals as drive signal line terminals,
A film length of 27.9 mm (6 pit holes 2a) is required, and this length corresponds to one LSI. In other words, an increase in the number of terminals increases the pitch size of the LSI. Therefore, the applicant has developed a new pulse control method, which will be described later, which can solve the above problems. However, with the conventional pulse control method, the Japanese-shaped segment liquid crystal display element 7 as shown in FIG.
In the electrode connection configuration shown in the same figure, which is applied when duty driving is attempted,
In order to display each display pattern shown in Table 1, the drive signals ai and bi for the two groups of segment electrodes S1 to S8 must be in the combination patterns shown in Table 1. In the same table, the x mark means that either 0 or 1 may be used. That is, the total number of types of patterns of the segment electrode drive signals ai and bi is 11 types as shown in Table 2.

【table】

[Table] On the other hand, in the case of the new pulse control method developed by the applicant, as will be described later, segment drive signals ai, which have patterns that are not included in Table 2 above,
There is a problem in that bi is given, and the Japanese-shaped segment liquid crystal display element 7 having the electrode connection configuration described above cannot be used as it is as a new pulse control type display element. An object of the present invention is to solve the problems associated with liquid crystal display elements when adopting the above-mentioned new pulse control method, and to provide a sun-shaped segment liquid crystal display element that can correctly display a predetermined character using the new pulse control method. It is to be. Means for Solving the Problems The present invention provides that one frame period is evenly divided into five timing sections, one of which is used as a correction section, and four types of common signals are generated at the same timing, and the common signal is divided into five timing sections. If there is a waveform voltage that is different from the waveform voltage in the remaining three timing periods only in one timing period of the frame period excluding the period corresponding to the correction period of the common signal, A segment signal consisting of 11 types having correction waveforms; A second segment electrode extends vertically downward from the right end of the first segment electrode, a third segment electrode extends vertically downward from the lower end of the second segment electrode, and a fourth segment electrode extends horizontally to the left from the lower end of the third segment electrode. a segment electrode; a fifth segment electrode extending vertically downward from the left end of the first segment electrode; a sixth segment electrode extending downward from the lower end of the fifth segment electrode; a seventh segment electrode extending laterally across the lower end;
Furthermore, a first common electrode facing the first segment electrode and the second segment electrode, a second common electrode facing the third segment electrode and the fifth segment electrode, and a third common electrode facing the seventh segment electrode. a fourth common electrode facing the fourth segment electrode and the sixth segment electrode, a liquid crystal is interposed between the first to seventh segment electrodes and the first to fourth common electrodes; The segment electrode, the third segment electrode, and the fourth segment electrode are commonly connected, and the first segment electrode, the fifth segment electrode, the sixth segment electrode, and the seventh segment electrode are commonly connected. It is a sun-shaped segment liquid crystal display element. Operation In the 1/4 duty/binary voltage drive of the new pulse control method, the common drive signal with the waveform shown in Figure 6 is applied to the common electrode and the segment drive signal with the waveform shown in Figure 7 is applied to the segment electrodes. In the Japanese-shaped segment liquid crystal display element having the electrode connection configuration, all the patterns shown in FIG. 3 are displayed, and no meaningless patterns are generated. Embodiment FIG. 1 shows a circuit diagram of a liquid crystal driving device used for driving the sun-shaped segment liquid crystal display element of the present invention, and FIG. 2 shows an electrode connection diagram of the sun-shaped segment liquid crystal display element. . In this embodiment, the sun-shaped segment liquid crystal display element 10 shown in FIG. 2 is driven at 1/4 duty with a binary voltage.
A configuration example for displaying each display pattern in FIG. 10 is shown. In the liquid crystal display element 10, the first segment electrode S1 extends in the horizontal direction above the display area.
The first common electrode C1 is arranged to face the second segment electrode S2 extending downward from the right end of the first segment electrode S1. Also, the second
The third electrode extends downward from the lower end of the segment electrode S2.
Segment electrode S3 and first segment electrode S1
A fifth segment electrode S5 extending downward from the left end of
A second common electrode C2 is arranged opposite to. In addition, the lower end of the second segment electrode S2 and the fifth
A third common electrode C is provided opposite to a seventh segment electrode S7 extending leftward across the lower end of the segment electrode S5 and a dot segment electrode S8.
3 is arranged, and further faces a sixth segment electrode S6 extending downward from the lower end of the fifth segment electrode S5 and a fourth segment electrode S4 extending in the left lateral direction from the lower end of the third segment electrode S3. is located. Moreover, the second segment electrode S2, the third segment electrode S3, the dot segment electrode S8, and the fourth segment electrode S4 are connected in common and given one segment drive signal ai, while the first segment electrode S1, The fifth segment electrode S5 and the sixth segment electrode S6 are also separately connected in common and configured to be supplied with another segment drive signal bi. By combining the common drive signals H1 to H4, which will be described later, and the segment drive signals ai and bi described above, which are applied to the common electrodes C1 to C4,
The third segment in the sun-shaped segment liquid crystal display element 10
It is configured to display each display pattern shown in FIGS. 1 to 3 and 10. Figure 3 1 to Figure 3 10
Segment drive signal corresponding to each display pattern of
Table 3 shows the combination patterns of ai and bi. In the same display, the x mark means that either 0 or 1 may be used.

[Table] In the circuit shown in FIG. 1, a ring counter 1 outputs timing signals h1 to h5 for obtaining drive signals for the sun-shaped segment liquid crystal display element 10.
1 consists of five stages of flip-flops 12 ₁ to 12 ₅ , and the clock signal φf obtained from the frequency divider 13 b of the oscillation circuit section 13 is used as the shift pulse. The oscillation circuit section 13 is composed of a clock generator 13a that outputs clock signals φ1 and φ2 of the original oscillation frequency, and a frequency divider 13b that receives the clock signal φ2 and divides it into a clock signal φf of a predetermined frequency. has been done. Timing signal output from the first stage of the ring counter 11
h1 is received by a T flip-flop 14, and the inverted output FR of the T flip-flop 14 is received by a common driver 15 at the next stage. The common driver 15 is a circuit for applying common drive signals H1 to H4 to the respective common electrodes C1 to C4 of the liquid crystal display element 10 shown in FIG.
It has four EX-OR gates 16 ₁ to 16 ₄ each receiving timing signals h2 to h5 outputted from the second and subsequent stages of the ring counter 11 at one input terminal, respectively, and these gates 16 ₁ ~
The inverted output FR of the T flip-flop 14 described above is inputted to the other input terminal of ₁₆₄ , and the respective outputs are used as the drive signal H1 of each common electrode C1 to C4.
It is configured to be obtained as ~H4. The inverted output FR of the above T flip-flop 14 is:
The EX-OR gate 18 performs an exclusive OR with the output from the memory section 17 that generates the signal Q corresponding to each display pattern created by the liquid crystal display element 10.
The output of the gate 18 is configured to be input to the next stage segment shift register 19. The memory section 17 includes a display data register 2
5-bit display data sent from 0 (DP, X4 ~
a data address decoder 17a which receives the data (X1) and outputs an address signal corresponding to the data;
The main ROM 17b receives h5 and outputs a display pattern signal Q corresponding to the address signal. The segment shift register 19 has a capacity of 17 bits, and is configured to operate by receiving the clock signal φ1 outputted from the clock generator 13a as a shift pulse. A segment latch circuit 21 is connected to this segment shift register 19, and receives the stored contents as a parallel signal.
The content held in the latch circuit 21, that is, the segment drive signal, is outputted by the next-stage segment driver 22 and applied to each segment electrode group of the liquid crystal display element 10 shown in FIG. Next, the operation of this device will be explained in Figures 4 and 5.
This will be explained using the time chart shown in the figure. The two clock signals φ1 and φ2 of the original oscillation frequency output from the clock generator 13a are the fifth clock signals φ1 and φ2.
As shown in FIGS. 1 and 5, they are out of phase with each other by 180 degrees, and the frequency divider 13b outputs the clock signal φf shown in FIG. is output. Therefore, the outputs of each stage of the ring counter 11 which receives this clock signal φf as a shift pulse, that is, the timing signals h1 to h5 (the waveforms of which are shown in FIGS. 42 to 46) and the timing signals h1 to h5 The common drive signals H1 to H4 (the waveforms of which are shown in FIGS. 48 to 11) generated based on the clock signal φf are also synchronized with the clock signal φf.
The output F of the T flip-flop 14 is repeatedly inverted at the time the timing signal h1 falls, as shown in FIG. 4, and provides timing for an interval corresponding to one frame. The waveforms of the drive signals H1 to H4 applied to the respective common electrodes C1 to C4 are exclusive of the outputs of the second and subsequent stages of the ring counter 11, that is, the timing signals h2 to h5, and the inverted output FR of the T flip-flop 14. It is given as a logical sum signal. On the other hand, in the memory section 17 for display pattern generation, data is input from the display data register 20 to the data address decoder 17a as shown in the truth table shown in Table 4 below (Bnk in the table means blank). 5bit data (DP, X4~X1) and main
Data accessed using 6-bit data (ai/bi, h1 to h5) directly input to the ROM 17b as an address signal is stored.

[Table] For example, if the input data Xin from the display data register 20 to the data address decoder 17a relates to the numerical display of "64512.8", the time in FIG. 5 showing each output waveform in the interval of the timing signal h1 at this time In chat, ai/bi
= "1" (that is, the ai side of the truth table is accessed), the first digit liquid crystal display element 10
The drive signal given to one segment electrode group of
ai is sampled by the segment shift register 19 in synchronization with the shift pulse φw (synchronized with the clock signal φ1). For example, if the display pattern of the first digit is "8", according to Table 4,
Xin = 8, DP (signal regarding the presence or absence of dots) =
Since the value of "0" and a1-h1 is "0", "0" is obtained as the output Q from the memory section 17. If the inverted output FR of the T flip-flop 14 is "0" in this period of the timing signal h1, "0" is input to the first stage of the segment shift register 19. In the next interval where ai/bi = “0” (that is, the bi side of the truth table is accessed), Xin = 8, DP = “0”, and the timing signal is h1
Therefore, from Table 4, "1" is accessed, and "1" is input to the first stage of the segment shift register 19 at the timing of the next shift pulse φw.
The next memory content is shifted 1 bit to the left. The second digit (a2, b2) that is input next from the display data register 20 to the data address decoder 17a
Assuming that the content of the display pattern is "2.",
Similarly, from the main ROM 17b, in Table 4, ai/bi = "1" (ai side), Xin = 2, DP =
"1", "0" corresponding to h1, then ai/bi=
“0” (bi side), Xin = 2, DP = “1”, “0” corresponding to h1 is accessed, and in the same way, a3,
b3...b7, a8, b8, S and 8 digits and symbol digit S
All of the shift registers 19 are accessed sequentially until
17 bits are filled. On the other hand, the contents of the shift register 19 are transferred to the latch circuit 21 as a parallel signal by a pulse signal φ1 (the waveform of which is shown in FIG. 5) synchronized with the rise of the timing signals h1 to h5.
The transferred segment drive signals are transmitted through each buffer 23 of the segment driver 22 to a1, b1,
..., a8, b8, and S terminals, and applied to the corresponding segment electrode group of the liquid crystal display element 10. That is, the display contents accumulated in the shift register 19 during the timing signal h1 are transferred to the segment electrode driver 2 during the next timing signal h2.
It will be output from 2. The timing deviation caused by the shift register 19 and latch circuit 21 is corrected by the common driver 15. That is, the common drive signal H1 is used in the interval of the timing signal h2, the drive signal H2 is used in the interval of the timing signal h3, the drive signal H3 is used in the interval of the timing signal h4, and the drive signal is used in the interval of the timing signal h5.
It is corrected by creating H4. Similarly to the above, in the period of the timing signal h2, data is sent to the data address decoder 17a.
Input ai/to Xin, DP and main ROM17b
Access is performed according to bi, h2, and the corresponding data in Table 4 is sequentially input from the memory section 17 to the shift register 19, and the timing signal h2
The display contents are transferred to the latch circuit 21 and displayed by the pulse signal φ7 synchronized with the falling edge of . Thereafter, similar operations are performed up to the timing signal h5, and the process returns to the period of the timing signal h1 again.
After this, the operation is the same as the previous one up to the point where a predetermined output Q is obtained from the memory section 17.
During the frame, the inverted output FR of the T flip-flop 14 is "1", so the output Q from the memory section 17 is inverted by the EX-OR gate 18 at the next stage and input to the shift register 19. On the other hand, in this one frame, common driver 1
Since the waveforms of the common drive signals H1 to H4 obtained from 5 are also inverted, the relationship between the applied voltages applied to the liquid crystal by the segment drive signal and the common drive signal is the same as in the previous frame. 61 to 64 are respective waveform diagrams of the common drive signals H1 to H4 obtained by the above circuit, and FIGS. 71 to 12 are waveform diagrams of the common drive signals H1 to H4 obtained by the above circuit.
Shows the waveforms of 12 sets of segment drive signals ai and bi to obtain each display pattern using H4.
The relationship between the waveform and the common drive signals H1 to H4 is as shown in Table 5.

[Table] Of these segment drive signals ai and bi, the 11 types shown in Table 6 below correspond to each display pattern in FIG.

[Table] Due to the combination of the common drive signals H1 to H4 and the segment drive signals ai and bi, the effective values of the voltages applied to the liquid crystal are as shown by diagonal lines in FIGS. 81 to 8, for example. In the figure, the solid line shows the waveform of the common drive signal, and the broken line shows the waveform of the segment drive signal. In this example, a waveform (0011) in FIG. 7 is shown as the segment drive signal. The effective value of the applied voltage at this time is the 8th
In the figure, if E=1.5V, Von=3/5・E→1.16V Voff=1/5・E→0.67V, so the operating margin α is Von/Voff=√3≒1.73, and Fig. 16 A value equivalent to the conventional example of 1/2 duty drive shown in is obtained. On the other hand, the effective value of the applied voltage is about 10% lower than in the conventional example shown in FIG. 16, but this can be compensated for by appropriately selecting the threshold value of the LCD. The waveforms of Xin and DP in FIG. 5 and 9 represent the timing of data switching, and are synchronized with the clock signal φ2 of the original oscillation frequency of the clock generator 13a. The terminal S shown in FIG. 1 is used to drive characters such as symbol digits other than the sun-shaped segment, and
It can be used within the range of segment drive signal waveform combinations shown in the figure. For this drive method, common drive signals H1 to H4
In the waveform shown in FIG. 15, there are no timing sections such as a selection section and a half-selection section as seen in the conventional waveforms shown in FIGS. 15 and 16, but the effective value of the voltage applied to the liquid crystal is , it can be divided into Von corresponding to the activated part and Voff corresponding to the non-activated part.
Also, despite the 1/4 duty drive, it is now possible to obtain timing for 5 bits, and the 6th
In the figure, the presence of sequential pulse-free sections T for each common electrode functions as a section for adjusting the above-mentioned effective value to an effective value. In addition, with this drive method, 1/4
Even if the duty is set, a sufficient operating margin α can be obtained, so when used for a calculator with an 8-digit display, for example, the number of drive signal lines is 21, which is 1/2
Compared to the duty drive case, the number is reduced by 15 (6
below) can be done. This reduces the number of pads on the LSI chip and also reduces the chip size. Furthermore, the number of pins on the package can be reduced, leading to lower LSI costs and the ability to downsize electronic devices. In particular, when making an LSI package using a film carrier, the following terminal arrangement can be improved, which reduces the amount of film used and contributes to lower material costs. That is, in this drive method, in the case of the above-mentioned 8-digit display, the number of terminals of the entire LSI including the drive signal line is 26, so the terminals are arranged on the 35mm film 2 shown in FIG. 17 explained in the conventional example. If the pitch of terminal 1a is 0.9 mm, the film length required for one LSI is 23.4 mm, and in the case of the conventional example mentioned above (film length L1 for one LSI is 27.9 mm).
However, since the effective length W of the film 2 in the width direction is 25.4 mm, the above terminal 1
a... can be arranged in the width direction of the film 2 as shown in FIG. For this reason, the power terminals 1b and 1c normally arranged in the width direction of the film 2
By adopting the above terminal arrangement method, the length L2 for one LSI can be reduced to the number of holes 2a for two or three LSIs (9.5 to 14.25 mm), even considering the number of holes for pitch holes 2a. Can be shortened. As a result, the number of pitch holes in the film 2 can be reduced by half compared to the conventional example, resulting in significant savings in materials and cost reduction. In addition, in this drive method, FIGS. 7 1 to 7
As can be seen from the segment drive signal shown in 2,
All patterns (16 patterns) of combinations with the common drive signals H1 to H4 in Figs. There are only 12 patterns, excluding the 4 patterns where one is off. On the other hand, the first
0 to 9 (including dots) in the conventional Japanese-shaped segment liquid crystal display element 7 of the electrode connection method shown in Figure 0.
As mentioned earlier in Table 2, there are only 11 types of segment drive signals when displaying each pattern, and the patterns in Table 2 above include (1000) patterns that are not shown in Figure 7. Therefore, the liquid crystal display element 7 based on this conventional wiring method cannot be used as is in the driving method. Therefore, in this embodiment, a liquid crystal display element 10 of the wiring type shown in FIG. 2 is adopted as a device that can be adapted to this driving method. The details of the connection are as described above. Although the liquid crystal display element 10 having a sun-shaped segment is shown here as an example, the present invention can be similarly applied to displays of other characters. Effects of the Invention As described above, according to the Japanese-shaped segment liquid crystal display device of the present invention, pulses having a waveform of one level are sequentially applied to each group of the common electrode in each frame, and all By applying a new 1/4 duty binary voltage drive to the segment electrodes of the common electrode group in each frame, a waveform is given to each group of segment electrodes corresponding to the common electrode to obtain a predetermined character. It is possible to display all numerical patterns from 0 to 9, without generating meaningless patterns, and to be compatible with new drive systems.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a device used to drive the sun-shaped segment liquid crystal display element of the present invention, Fig. 2 is an electrode connection diagram of the liquid crystal display element, and Fig. 3 is each display pattern of the liquid crystal display element. 4 and 5 are time charts of the above circuit, respectively.
FIG. 6 is a waveform diagram of the common drive signal of the embodiment, and FIG.
The figure is a waveform diagram of the segment drive signal in the example.
9 is a waveform diagram showing an example of applied voltage in the embodiment, FIG. 9 is an explanatory diagram showing an example of terminal arrangement of a film carrier LSI to which the present invention is applied, and FIG.
The figure shows the electrode connection method of a sun-shaped segment liquid crystal display element used when performing 1/4 duty drive in the conventional method, Figure 11 is a diagram of each display pattern by the liquid crystal display element, and Figure 12 is a waveform diagram showing the effective values of the drive signal and applied voltage when performing 1/2 duty drive using the conventional method, and Figure 13 shows the drive signal and effective values of the applied voltage when performing 1/3 duty drive using the conventional method. Waveform diagram showing effective values,
Figure 14 is an explanatory diagram showing an example of the terminal arrangement of a film carrier LSI when the conventional method is applied;
The figure is a vertical cross-sectional view schematically showing the implementation of a film carrier LSI. 10... Japanese-shaped segment liquid crystal display element, S
1-S8...Segment electrode, C1-C4...Common electrode.

Claims (1)

[Claims] 1. One frame period is equally divided into five timing sections, one of which is used as a correction section and corresponds to four types of common signals at the same timing and the correction section of the common signal. If there is a waveform voltage that is different from the waveform voltage in the remaining three timing periods only in one timing section of the frame period excluding the section where A 1/4 duty, binary voltage driven sun-shaped segment liquid crystal display element comprising: a first segment electrode extending horizontally in the upper part of the display area; a second segment electrode extending vertically downward from the right end; a third segment electrode extending vertically downward from the lower end of the second segment electrode; a fourth segment electrode extending horizontally to the left from the lower end of the third segment electrode; A fifth segment electrode extending vertically downward from the left end of the first segment electrode, a sixth segment electrode extending downward from the lower end of the fifth segment electrode, and a space between the lower end of the second segment electrode and the lower end of the fifth segment electrode. a seventh segment electrode extending laterally across;
Furthermore, a first common electrode facing the first segment electrode and the second segment electrode, a second common electrode facing the third segment electrode and the fifth segment electrode, and a third common electrode facing the seventh segment electrode. a fourth common electrode facing the fourth segment electrode and the sixth segment electrode, a liquid crystal is interposed between the first to seventh segment electrodes and the first to fourth common electrodes; The segment electrode, the third segment electrode, and the fourth segment electrode are commonly connected, and the first segment electrode, the fifth segment electrode, the sixth segment electrode, and the seventh segment electrode are commonly connected. A sun-shaped segment liquid crystal display element.