JPH0548116A - Nonvolatile storage device - Google Patents

Abstract

PURPOSE:To improve the degree of integration of a semiconductor storage device by constituting an LSI circuit using a trap type semiconductor memory of MNOS, etc., in a one-transistor/one-cell structure. CONSTITUTION:After a channel area 13 is formed by forming a drain 9 and source 11 in a p-type silicon well 15, a thin silicon oxide film 7, SiN film 5, and polysilicon film 3 are successively formed on the area 13. This nonvolatile semiconductor memory cell 2 thus formed is characterized in a p-type high- concentration area 17 formed by implanting ions of a p-type impurity into the surface of the channel area 13. As electrons are trapped in the SiN film 5 when a programming voltage is applied across the polysilicon film 3 and channel area 13, information is recorded in this memory cell 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an LSI for a nonvolatile semiconductor memory device.
Concerning the improvement of the integration degree of the structure.

[0002]

2. Description of the Related Art FIG. 8 shows a schematic sectional view of a memory cell 1 of a conventional nonvolatile semiconductor memory device. An n ⁻ -type drain layer 9a and an n ⁺ -type drain layer 9b are provided in the P-type silicon well layer 15.
And an n ^{− type} source layer 11a and an n ^{+ type} source layer 11b. The drain 9 is formed by the drain layers 9a and 9b. Further, the source 11 is formed by the source layers 11a and 11b. A channel region 13 is formed by the drain 9 and the source 11. A thin silicon oxide film 7 (about 2 nm thick) is formed on the upper surface of the channel region 13, and a thicker silicon oxide film 7a is formed on the surface other than the channel region 13. A SiN film 5 having a thickness of about 50 nm is formed on the silicon oxide film 7. SiN film 5
A polysilicon film 3 is formed on top.

The memory cell 1 as described above is in a state in which information "0" is stored (state in which electrons are trapped in the SiN film 5).
And a state in which information "1" is stored (a state in which electrons are not trapped in the SiN film 5).

These two states will be described based on the hysteresis loop of the memory cell 1 shown in FIG. The horizontal axis of FIG. 9 represents the gate voltage Vg, and the vertical axis represents the threshold voltage Vth.
The gate voltage Vg is a voltage applied to the gate electrode of the memory cell. The threshold voltage Vth is a gate voltage when a current flows between the source and the drain at a constant drain voltage when the voltage applied to the gate electrode is increased. The threshold voltage Vth is given by the following formula.

[0005]

[Equation 1]

In the initial state P1 in which electrons are not trapped in the SiN film 5 of the memory cell 1, the threshold voltage of the memory cell 1 is almost 0V as shown in the figure.

When information "0" is written in the memory cell 1,
A voltage of about 20 V is applied to the gate electrode 3 of the memory cell 1. At this time, the electric field generated between the gate electrode 3 and the channel region 13 causes the electrons in the channel region 13 to have high energy, and some of the electrons tunnel through the silicon oxide film 7 to cause some electrons in the SiN film 5. Go into and be trapped. Due to such a change, the threshold voltage rises to about 2V (see Q1 in FIG. 9). That is, the memory cell 1 operates as an enhancement type transistor having a threshold voltage of 2V. That is, this state is the state in which the information "0" is written in the memory cell 1. In addition,
Even if the gate voltage is cut off, the threshold voltage remains unchanged (see R1 in FIG. 9).

Next, in order to erase the information "0", it is necessary to return the trapped electrons to the channel region 13. Therefore, a voltage of about 25 V is applied to the channel region 13 to generate an electric field in the direction opposite to that at the time of writing information, and the electrons are returned to the channel region 13. With such a change, the threshold voltage of about 2V changes to about -2V (FIG. 9).
See S1). That is, the memory cell 1 has a threshold voltage of −2.
It works as a V depletion type transistor. This state in which the information "0" is erased means that the memory cell 1 stores the information "1". The threshold voltage remains the same even when the gate voltage is cut off (see T1 in FIG. 9).

In reading information, the memory cell 1
Whether information "1" is stored or information "0" is stored is determined by whether or not a current flows through the channel region 13 when a voltage of about 5 V is applied between the source 11 and the drain 9 of .. That is, when the information "1" is stored, the threshold voltage of the memory cell 1 is a negative value as described above. Therefore, since the memory cell 1 is a depletion type transistor, the channel region 13 is in a conducting state. Therefore, a current flows through the channel region 13. On the other hand, when the information “0” is stored, the threshold voltage of the memory cell 1 is a positive value. Therefore, the memory cell 1
Is an enhancement type transistor, the channel region 13 is not energized. Therefore, the channel area
No current flows through 13.

Next, an example in which a memory circuit is constructed by using the above memory cell 1 will be shown.

First, the principle of operation when writing information will be described. FIG. 10 is a conceptual diagram showing the configuration of a 1024-bit memory LSI.

The memory cell array A includes a memory cell 1
However, a total of 1024 pieces (1 K bits) of 32 (rows) × 32 (columns) are arranged in a matrix. The drain of the select transistor 4 is connected to the source 11 of each memory cell 1. From the row decoder 8, the word line W connected to the gate electrode of each selection transistor 4 is connected.
L is wired. The control gate line CGL is connected to the gate electrode 3 of each memory cell 1. Further, a data line DL connected to the drain 9 of each memory cell 1 is wired from the column decoder 6. A well line Well is connected to the p-type silicon well 15.

For example, consider a case where information is written in the memory cells 1m, n. Control gate line CGL
The programming voltage Vpp is applied only to n. At this time, decoders 6 are provided on lines other than the data line DLm.
The programming inhibit voltage Vi is applied by.
Further, a ground voltage having the same potential as the substrate is applied to the word line WLn. Therefore, among the memory cells 1 connected at their gates to the control gate line CGLn to which the programming voltage Vpp is applied, the potentials of the drain, source and well are all 0 because the data line to which the programming inhibit voltage Vi is not applied is Only memory cells 1m, n connected to DLm. That is, the memory cell 1
The electric field effect by the programming voltage Vpp acts only on m and n, and the electrons in the channel region are trapped in the trap of the SiN film 5. As described above, the information "0" is written only in the memory cell 1m, n.

Next, the principle of operation for reading information from the memory cells 1m, n will be described with reference to FIG.

The configuration of FIG. 11 is the same as that of FIG. The row decoder 8 applies the voltage Vdd to only the word line WLn. Further, the voltage Vdd is applied to all the data lines DL. At this time, since the channel region 13 of the memory cell 1 in which the information "0" is stored is not in the conducting state as described above, the current flowing through each data line DL is directly input to the column decoder 6.

On the other hand, the channel region 13 of the memory cell 1 in which the information "1" is stored is in the energized state. further,
When the selection transistor 4 is in the ON state (the voltage Vdd is applied to the gate electrode of the selection transistor 4), the current flowing through each data line DL is the memory cell 1,
It falls to the ground potential through the selection transistor 4. Therefore, no current is input to the column decoder 6.

At this time, the column decoder 6 is supposed to output only the current from the data line DLm. This output is amplified by the sense amplifier 10,
Read out. From the above, only the information from the memory cell 1m, n is read.

Next, the above-mentioned 1024-bit memory LS
The principle of operation in the case of collectively erasing the information stored in I
It will be described with reference to FIG. The configuration of FIG. 12 is the same as that of FIG. After grounding each control gate CG line, the programming voltage Vpp is applied to the p-type silicon well 15 of each memory cell 1 through the well line Well.
At this time, the trapped electrons return to the channel region 13 due to the electric field effect. That is, the information that is written
0 "is all erased, and all memory cells 1 have information" 1 ".
Will be in the state of memorizing.

[0019]

In order to improve the degree of integration of the memory LSI, a method of removing the selection transistor 4 in the conventional memory LSI configuration can be considered.

It is assumed that a 1-transistor / 1-cell memory LSI as shown in FIG. 13 is constructed without using the selection transistor 4 in the conventional memory LSI structure. In addition,
The source 11 of the memory cell 1 is grounded.

Consider a case where information is read from the memory cell 1m, n. Similarly to the above, the voltage Vdd is applied to the data line DL. At this time, when there is a memory cell 1 that stores information "1" (in an erased state), the channel is formed because the memory cell 1 is a depletion type transistor. That is, it is in the energized state. Therefore, the current flowing through the data line DL leaks to the energized memory cell 1 and falls to the ground potential.

For example, when the current flowing through the data line DLm leaks to the memory cell 1m, n + 1, the memory cell 1
This means that the information of the memory cell 1m, n + 1 is read without reading the information of m, n.

Therefore, the conventional memory LSI structure requires the selection transistor 4 for shutting off the memory cell 1 in the energized state in order to prevent such erroneous reading. Therefore, there is a problem that the degree of integration cannot be improved.

Therefore, an object of the present invention is to provide a non-volatile memory device which does not cause erroneous reading despite the 1-transistor / 1-cell structure.

[0025]

A nonvolatile memory device according to the present invention includes a semiconductor region of a first conductivity type, at least a pair of diffusion regions of a second conductivity type formed in the semiconductor region, and the semiconductor. In a semiconductor memory device including a plurality of insulating films formed on a substrate and a control electrode formed on the insulating film, at least a surface between a pair of diffusion regions is formed in a first conductivity type high concentration region. It is characterized by

[0026]

The nonvolatile memory device according to the present invention is characterized in that at least the surface between the pair of diffusion regions is formed in the high concentration region of the first conductivity type.

Therefore, the hysteresis loop of the memory cell is shifted in the positive direction of the threshold voltage so that the threshold voltage takes a positive value (acts as a depletion type transistor) even when the memory cell is in the erased state.

[0028]

1 is a schematic cross-sectional view of a memory cell 2 of a nonvolatile memory device according to an embodiment of the present invention.

The manufacturing process of the memory cell 2 having the above structure will be described below with reference to FIGS.

Ion implantation is performed on the n-type silicon substrate 14 to form a P-well layer 15 which is a semiconductor region of the first conductivity type (FIG. 1A). Next, a silicon oxide film 7a which is an insulating film is formed on the upper surface by thermal oxidation, and a low pressure SiN film 5a which is an insulating film is further deposited on the upper surface by a low pressure CVD method (FIG. 1B). Next, by etching using a resist, the reduced pressure SiN film 5a is left only above the region 13 which is a channel between the pair of diffusion regions (FIG. 1).
C). Next, thermal oxidation is performed again, and the n ⁻ -type layers 9a and 11a that are diffusion regions are formed by ion implantation and thermal diffusion (FIG. 1D). Next, the low pressure SiN film 5a and the silicon oxide film 7a on the bottom surface thereof are removed by immersing in a wet etching solution and etching (FIG. 1).
E). Next, using the resist as a mask, a p-type impurity which is a first conductivity type impurity is implanted into the region 13 which will be a channel (FIG. 2F). Next, the ultra-thin
An oxide (UTO) 7 is formed by thermal oxidation, a low pressure SiN film 5 which is an insulating film is deposited on the upper surface of the oxide 7 by a low pressure CVD method, and a polysilicon film 3 which is a control electrode is grown and formed by the CVD method (FIG. 2G). Next, the polysilicon film 3 and the low-pressure SiN film 5 are cut by etching using the resist as a mask (FIG. 2H). Next, n ⁺ layers 9b and 11b which are diffusion regions are formed by ion implantation and thermal diffusion (FIG. 1). The drain layers 9a and 9b form the n-type drain 9, which is one of the diffusion regions of the second conductivity type. In addition, the source layers 11a and 11
b forms an n-type source 11 which is a diffusion region forming a pair of the second conductivity type. A channel region 13 is formed by the drain 9 and the source 11.

The hysteresis loop of the memory cell 2 is shown in FIG.
Shown in. In the initial state P2 where electrons are not trapped in the SiN film 5 of the memory cell 2, the threshold voltage of the memory cell 2 is about 2.5V as shown in the figure.

When information "0" is written in the memory cell 2,
A voltage of about 20 V is applied to the control electrode 3 of the memory cell 2. At this time, the electric field generated between the control electrode 3 and the channel region 13 causes the electrons in the channel region 13 to have high energy, and some electrons tunnel through the silicon oxide film 7 to cause the electrons in the SiN film 5 to tunnel. Go into and be trapped. Due to such a change, the threshold voltage rises to about 4,5V (see Q2 in FIG. 4). That is, the memory cell 2 comes to function as an enhancement type transistor having a threshold voltage of 4.5V. This state is memory cell 2
The information "0" has been written in. Even if the gate voltage is cut off, the threshold voltage remains unchanged (FIG. 9).
See R2).

Next, in order to erase the information "0", it is necessary to return the trapped electrons to the channel region 13. Therefore, a voltage of about 25 V is applied to the channel region 13 to generate an electric field in the direction opposite to that at the time of writing information, and the electrons are returned to the channel region 13. Due to such changes, the threshold voltage of about 4.5V changes to about 0.5V (S in FIG. 9).
2). That is, the memory cell 2 operates as an enhancement type transistor having a threshold voltage of 0.5V. This state in which the information "0" has been erased is the memory cell 2
Means that the information "1" is stored. Even if the gate voltage is cut off, the threshold voltage remains unchanged (see T2 in FIG. 9).

In reading information, the memory cell 2
A voltage of about 2 V is applied to the control electrode 3 of the
Whether or not information "1" is stored or information "0" is stored is determined by whether or not a current flows through the channel region 13 when a voltage of about 5 V is applied between the drain 9 and the drain 9. That is, when the information “1” is stored,
As described above, since the memory cell 2 is an enhancement type transistor having a threshold voltage of about 0.5V, the channel region
13 is not energized. However, when a voltage of about 2 V is applied to the control electrode 3, the channel region 13 is in a conducting state. Therefore, a current flows through the channel region 13.
On the other hand, when the information "0" is stored, the memory cell 1 is an enhancement type transistor having a threshold voltage of about 4.5V, and therefore the channel region 13 is energized even if a voltage of about 2V is applied to the control electrode 3. Not in a state. Therefore, no current flows in the channel region 13.

As described above, compared with the conventional memory cell 1, the hysteresis loop of the memory cell 2 has a positive threshold voltage even when the memory cell is in the erased state (acts as a depletion type transistor). like)
The threshold voltage is shifted in the positive direction.

Next, a memory circuit is constructed by using the memory cell 2 described above. Fig. 5 shows a 1024-bit memory L
1 shows a schematic configuration diagram of SI.

The memory cell array A includes memory cells 2
However, a total of 1024 pieces (1 K bits) of 32 (rows) × 32 (columns) are arranged in a matrix. A source line SL is connected to the source of each memory cell 2. A drain line DL connected to the drain of each memory cell 2 is wired from the column decoder 6. A sense amplifier 10 is connected to the column decoder 6. Furthermore, from the decoder 8, a word line WL connected to the control electrode 3 of each memory cell 2 is wired. A well line Well is connected to the P-type silicon well 15.

First, the principle of writing information will be described.
For example, consider a case where information is written in the memory cell 2m, n. Nth word line WL by the decoder 8
The programming voltage Vpp is applied only to n. At this time, the m-th source line SLm and the drain line DL
The programming inhibit voltage Vi is applied to lines other than m by a decoder (not shown). Therefore, the word line WLn to which the programming voltage Vpp is applied
In the memory cell 2 connected by the gate and the gate, the drain, the source, and the p-type silicon well all have the potential 0 because the programming inhibit voltage Vi is applied to the source and the drain.
Is only applied to the memory cells 2m, n. In other words, the electric field effect by the programming voltage Vpp acts only on the memory cell 2m, n, and the electrons in the channel region are transferred to the SiN film 1
Trapped in trap 7. That is, the memory cell 2
Information "0" is written only in m and n.

Next, the principle of operation for reading information from the memory cell 2m, n will be described with reference to FIG.

The configuration of FIG. 6 is the same as that of FIG. The decoder 8 allows the voltage Vs (2
V) is applied. Also, all drain lines DL
Is applied with a voltage Vdd of about 5V.

At this time, the word line WLn and the control electrode 3
When the memory cell 2 connected by means of storing information “0” (trapping electrons), since the memory cell 2 is an enhancement type transistor having a threshold voltage of about 4.5V, a voltage Vs of about 2V is applied to the control electrode. When applied to 3, no channel is formed. Therefore, the drain line DL
The current flowing through is not leaked to the memory cell 2 storing the information "0", and is directly input to the column decoder 6.

On the other hand, when the information "1" is stored (electrons are not trapped), the memory cell 2 is an enhancement type transistor having a threshold voltage of about 0.5V, so that a voltage Vs of about 2V is applied to the control electrode. When applied to 3, a channel is formed. Therefore, the drain line DL
The current flowing through is the information that is connected to the word line WLn.
It flows through the channel region 13 of the memory cell 2 storing 1 "and falls to the ground potential via the source line SL. That is, no current is input to the column decoder 6.

The voltage Vs is applied only to the word line WLn, and the column decoder 6 is supposed to output only the current from the data line DLm. This output is amplified and read by the sense amplifier 10. That is, only the information from the memory cell 2m, n has been read.

Next, the above-mentioned 1024-bit memory LS
The principle of operation in the case of collectively erasing the information stored in I
Description will be given based on FIG. 7.

The configuration of FIG. 7 is the same as that of FIG. After grounding each word line WL, the programming voltage Vpp is applied to the p-type silicon well 15 of each memory cell 2 through the well line Well. At this time, the trapped electrons return to the channel region 13 due to the electric field effect. That is, all the written information "0" is erased, and all the memory cells 2 store the information "1".

As described above, information can be written, read, and erased by the one-transistor / one-cell nonvolatile memory device.

Although the first conductivity type is p-type and the second conductivity type is n-type in the above embodiment, the first conductivity type may be n-type and the second conductivity type may be p-type.

[0048]

Since the nonvolatile memory device according to the present invention is characterized in that the surface between at least a pair of diffusion regions is formed in the high concentration region of the first conductivity type, even when the memory cell is in the erased state. The hysteresis loop of the memory cell is shifted in the positive direction of the threshold voltage so that the threshold voltage takes a positive value (acting as a depletion type transistor).

Therefore, even in the state where the information "1" is stored (erased state), the memory cell can be made to function as an enhancement type transistor. Therefore, it is not necessary to provide a selection transistor for cutting off the depletion type transistor, and one cell can be composed of one transistor.

Therefore, the constitutional area of one cell can be reduced. That is, the degree of integration of the nonvolatile memory device can be improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional configuration diagram of a memory cell 2 according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the memory cell 2.

FIG. 3 is a diagram showing a manufacturing process of the memory cell 2.

FIG. 4 is a diagram showing a hysteresis loop of a memory cell 2.

FIG. 5 is a conceptual diagram of the configuration of a memory LSI for explaining the principle of writing information in a memory cell according to an embodiment of the present invention.

FIG. 6 is a conceptual diagram showing a configuration of a memory LSI for explaining a principle of reading information from a memory cell according to an embodiment of the present invention.

FIG. 7 is a conceptual diagram showing a configuration of a memory LSI for explaining a principle of erasing information stored in a memory cell according to an embodiment of the present invention.

FIG. 8 is a schematic cross-sectional configuration diagram of a conventional memory cell 1.

9 is a diagram showing a hysteresis loop of the memory cell 1. FIG.

FIG. 10 is a conceptual diagram showing a configuration of a memory LSI for explaining the principle of writing information in a conventional memory cell.

FIG. 11 is a conceptual diagram of the configuration of a memory LSI for explaining the principle of reading information from a conventional memory cell.

FIG. 12 is a conceptual diagram of a configuration of a memory LSI for explaining a principle of erasing information stored in a conventional memory cell.

FIG. 13 is a diagram showing a problem of a memory LSI having a 1-transistor / 1-cell structure using the memory cell 1.

[Explanation of symbols]

 15 ... p-type silicon well 9 ... n-type drain 11 ... n-type source 13 ... channel region 7 ... silicon oxide film 5 ... SiN film 3 ... polysilicon film 17 ... ..P-type high-concentration region

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 19, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

By ion implantation into the n-type silicon substrate 14,
To form the P-well layer 15 which is the first conductivity type semiconductor region.
To (figureTwoA). Next, an insulating film is formed on the upper surface by thermal oxidation.
A silicon oxide film 7a is formed on the upper surface of the
Deposit low-pressure SiN film 5a, which is an insulating film, by low-pressure CVD method
Let (figureTwoB). Then etch with resist
The channel that is between the pair of diffusion regions by
The decompressed SiN film 5a is left only above the region 13 (see FIG.Two
C). Next, thermal oxidation is performed again, and ion implantation and
And n, which is a diffusion region due to thermal diffusion^-Shape layers 9a and 11a
(FigureTwoD). Next, soak in a wet etching solution.
Then, the low pressure SiN film 5a and the
The silicon oxide film 7a on the bottom surface is removed (see FIG.Two
E). Next, using the resist as a mask,
P-type impurity which is the first conductivity type impurity is implanted into the region 13
(FigureThreeF). Next, the ultra-thin
Oxide (UTO) 7 is formed by thermal oxidation and
A low pressure SiN film 5 which is an insulating film is formed on the surface by the low pressure CVD method.
Deposited, and then using the CVD method, the
The recon film 3 is grown and formed (Fig.ThreeG). Next, Regis
By using the mask as a mask
The film 3 and the reduced pressure SiN film 5 are cut (Fig.ThreeH). Next
The diffusion area by ion implantation and thermal diffusion
n⁺Form layers 9b, 11b (FIG. 1). The drain
One of the diffusion regions of the second conductivity type is formed by the layers 9a and 9b.
An n-type drain 9 is formed. In addition, the source layers 11a and 11
n is a diffusion region forming a pair of the second conductivity type by b.
A base 11 is formed. By drain 9 and source 11
As a result, the channel region 13 is formed.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

When information "0" is written in the memory cell 2,
A voltage of about 20 V is applied to the control electrode 3 of the memory cell 2. At this time, the electric field generated between the control electrode 3 and the channel region 13 causes the electrons in the channel region 13 to have high energy, and some electrons tunnel through the silicon oxide film 7 to cause the electrons in the SiN film 5 to tunnel. Go into and be trapped. Due to such a change, the threshold voltage rises to about 4,5V (see Q2 in FIG. 4). That is, the memory cell 2 comes to function as an enhancement type transistor having a threshold voltage of 4.5V. This state is memory cell 2
The information "0" has been written in. Even if the gate voltage is cut off, the threshold voltage remains unchanged (FIG. 4 ).
See R2).

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0033

[Correction method] Change

[Correction content]

Next, in order to erase the information "0", it is necessary to return the trapped electrons to the channel region 13. Therefore, a voltage of about 25 V is applied to the channel region 13 to generate an electric field in the direction opposite to that at the time of writing information, and the electrons are returned to the channel region 13. Due to such changes, the threshold voltage of about 4.5V changes to about 0.5V (S in FIG. 4 ).
2). That is, the memory cell 2 operates as an enhancement type transistor having a threshold voltage of 0.5V. This state in which the information "0" has been erased is the memory cell 2
Means that the information "1" is stored. Even if the gate voltage is cut off, the threshold voltage remains unchanged (Fig.
4 T2).

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

First, the principle of writing information will be described.
For example, consider a case where information is written in the memory cell 2m, n. Nth word line WL by the decoder 8
The programming voltage Vpp is applied only to n. At this time, the m-th source line SLm and the drain line DL
The programming inhibit voltage Vi is applied to lines other than m by a decoder (not shown). Therefore, the word line WLn to which the programming voltage Vpp is applied
In the memory cell 2 connected by the gate and the gate, the drain, the source, and the p-type silicon well all have the potential 0 because the programming inhibit voltage Vi is applied to the source and the drain.
Is only applied to the memory cells 2m, n. In other words, the electric field effect due to the programming voltage Vpp acts only on the memory cell 2m, n, and the electrons in the channel region become SiN film.
5 traps. That is, the memory cell 2
Information "0" is written only in m and n.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

[0043] The voltage Vs is applied are only the word line WLn, and the column decoder 6, drain
Are supposed to only the current from the in-line DLm is output. This output is amplified and read by the sense amplifier 10. That is, only the information from the memory cell 2m, n has been read.

[Procedure Amendment 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] Means for solving the problem

[Correction method] Change

[Correction content]

A nonvolatile memory device according to the present invention includes a semiconductor region of a first conductivity type, at least a pair of diffusion regions of a second conductivity type formed in the semiconductor region, and the semiconductor. In a semiconductor memory device including a plurality of insulating films formed on a region and a control electrode formed on the insulating film, at least a surface between a pair of diffusion regions is formed in a first conductivity type high concentration region. It is characterized by

Claims (1)

[Claims] 1. A semiconductor region of a first conductivity type, at least a pair of diffusion regions of a second conductivity type formed in the semiconductor region, a plurality of insulating films formed on the semiconductor substrate, and the insulating film. A semiconductor memory device comprising: a control electrode formed on a film; and a non-volatile memory device, wherein at least a surface between a pair of diffusion regions is formed in a high concentration region of a first conductivity type.