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JPH0543485Y2 - - Google Patents

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Publication number
JPH0543485Y2
JPH0543485Y2 JP1987059805U JP5980587U JPH0543485Y2 JP H0543485 Y2 JPH0543485 Y2 JP H0543485Y2 JP 1987059805 U JP1987059805 U JP 1987059805U JP 5980587 U JP5980587 U JP 5980587U JP H0543485 Y2 JPH0543485 Y2 JP H0543485Y2
Authority
JP
Japan
Prior art keywords
wiring board
flip chip
bumps
conductor
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987059805U
Other languages
Japanese (ja)
Other versions
JPS63165855U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987059805U priority Critical patent/JPH0543485Y2/ja
Publication of JPS63165855U publication Critical patent/JPS63165855U/ja
Application granted granted Critical
Publication of JPH0543485Y2 publication Critical patent/JPH0543485Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は外部回路との接続用バンプを備えたフ
リツプチツプを配線基板に実装する構造に関す
る。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a structure for mounting a flip chip provided with bumps for connection with an external circuit on a wiring board.

〔従来の技術〕[Conventional technology]

集積回路等の半導体装置の進歩に伴い、1個の
半導体装置内に収納される回路要素数が急増して
それを配線基板上に実装するに当たり、多数のボ
ンデイング線を接続する作業が複雑化するととも
に、接続線のためにかなりの面積を半導体装置の
まわりに取つてやらなければならなくなつて来て
いる。一方、電子装置を小形化するには配線基板
をまず小形化しなければならず、半導体装置の実
装密度を極力上げてやる必要がある。公知のよう
にフリツプチツプはバンプと称される外部回路と
の接続用の突起導体を備えており、フリツプチツ
プの実装に当たつてはこのバンプを配線基板の導
体に直接に接合すればよいので、ボンデイング線
が不要になり、かつ半導体装置のまわりに接続の
ための面積を設けなくても、半導体装置の配線基
板への搭載に必要な面積内で外部回路との接続が
可能である。第2図から第4図は従来技術による
このフリツプチツプの実装の要領を示すものであ
る。
With the advancement of semiconductor devices such as integrated circuits, the number of circuit elements housed in one semiconductor device has rapidly increased, and when mounting them on a wiring board, the work of connecting a large number of bonding wires has become complicated. At the same time, it has become necessary to allocate a considerable amount of area around the semiconductor device for connection lines. On the other hand, in order to miniaturize electronic devices, it is first necessary to miniaturize the wiring board, and it is necessary to increase the packaging density of semiconductor devices as much as possible. As is well known, flip chips are equipped with protruding conductors called bumps for connection with external circuits, and when mounting a flip chip, these bumps can be directly bonded to the conductors of the wiring board, so bonding is not necessary. Connection with an external circuit is possible within the area required for mounting the semiconductor device on the wiring board, without the need for wires and providing an area around the semiconductor device for connection. FIGS. 2 to 4 show the implementation of this flip chip according to the prior art.

フリツプチツプは例えば集積回路であつて、第
2図に示すようにふつうは方形の板状体であり、
その片面、図ではその下面に半田や金からなるバ
ンプが数十個程度設けられる。バンプはフリツプ
チツプのもつ方形の対向する2辺に沿つて、ある
いは図示のようにその4辺に沿つて配列される。
第3図はこのフリツプチツプ1をセラミツク配線
基板10上に実装した状態を示し、この場合のバ
ンプにはふつう半田が用いられ、フリツプチツプ
は配線基板10の面上の導体11と半田バンプ2
aによつて半田付けされ、これによつてフリツプ
チツプが複数の導体11に接続されるとともに該
半田接続によつて配線基板10に取り付けられ
る。配線基板が通常のガラスエポキシ板を用いる
いわゆるプリント配線基板である場合、配線基板
とフリツプチツプを構成するシリコンと熱膨張係
数がかなり違うので、フリツプチツプをプリント
配線基板に直接実装することは不可で、一旦フリ
ツプチツプをセラミツク配線基板上に実装した上
でプリント配線基板に実装してやらなければなら
なくなる。しかし、これではセラミツク配線基板
上の導体とプリント配線基板上の導体とをボンデ
イング線によつて接続しなければならないので、
実装に手間がかかりかつ実装密度が下がつてしま
うことになる。このため、第4図に示すような一
種の仲介接続導体を用いる実装構造が知られてい
る。この仲介接続導体21は数十μmの厚みの薄
い多数条の銅箔が可撓性のポリイミド等の絶縁フ
イルム22に担持されており、各仲介接続導体の
一端がフリツプチツプ1のバンプと接続され他端
がプリント配線基板10の導体11と半田付け等
により接続される。この場合のバンプとしてはふ
つう金バンプ2bが用いられ、薄く錫めつきされ
た仲介接続導体21と専用の工具を用いて450℃
程度の加温加圧下で接合される。この仲介接続導
体21も絶縁フイルム22もともに可撓性でフリ
ツプチツプ1に掛かりやすい熱応力を吸収するか
ら、第4図の実装構造でフリツプチツプをふつう
のプリント配線基板に実装することができ、セラ
ミツク配線基板を介して実装するよりは接続に手
間を要せず、かつ実装に必要な面積を縮小でき
る。
A flip chip is an integrated circuit, for example, and is usually a rectangular plate-like body, as shown in FIG.
On one side, in the figure, on the bottom side, there are about a dozen bumps made of solder or gold. The bumps are arranged along two opposite sides of the flip chip's rectangle, or along four sides as shown.
FIG. 3 shows a state in which this flip chip 1 is mounted on a ceramic wiring board 10. In this case, solder is usually used for the bumps, and the flip chip is connected to the conductor 11 on the surface of the wiring board 10 and the solder bumps 2.
a, thereby connecting the flip chip to the plurality of conductors 11 and attaching it to the wiring board 10 by the solder connection. If the wiring board is a so-called printed wiring board that uses an ordinary glass epoxy board, it is impossible to directly mount the flip chip on the printed wiring board because the thermal expansion coefficients of the wiring board and the silicon that make up the flip chip are quite different. The flip chip must be mounted on a ceramic wiring board and then mounted on a printed wiring board. However, this requires connecting the conductor on the ceramic wiring board and the conductor on the printed wiring board with a bonding wire.
Mounting takes time and the mounting density decreases. For this reason, a mounting structure using a type of intermediary connection conductor as shown in FIG. 4 is known. This intermediate connection conductor 21 is made up of a large number of thin copper foil strips with a thickness of several tens of μm supported on an insulating film 22 made of flexible polyimide, etc., and one end of each intermediate connection conductor is connected to a bump of the flip chip 1. The end is connected to the conductor 11 of the printed wiring board 10 by soldering or the like. In this case, gold bumps 2b are usually used as the bumps, and they are heated at 450°C using a thinly tinned intermediary connection conductor 21 and a special tool.
They are joined under moderate heat and pressure. Since both the intermediary connection conductor 21 and the insulating film 22 are flexible and absorb the thermal stress that is likely to be applied to the flip chip 1, the flip chip can be mounted on an ordinary printed wiring board with the mounting structure shown in FIG. Compared to mounting via a board, connection requires less effort and the area required for mounting can be reduced.

〔考案が解決しようとする問題点〕[Problem that the invention attempts to solve]

しかし、半導体装置の集積度がますます高まり
複雑なまたは多数の回路を小面積内に集積化でき
るようになると、外部回路との接続に必要なバン
プの数が増えてフリツプチツプの周縁に並べ切れ
なくなつて来る。もちろんバンプ自体の寸法を小
にしあるいはその間隔を詰めることは可能である
が、バンプがあまり小さくなると接続の信頼度が
低下するし、またバンプ間隔を小にすると配線基
板側の導体や仲介接続導体の配列間隔をこれに応
じて小さくしてやらねばならないので、むしろこ
の方に下限がありかつ接続作業時に線間が短絡さ
れてしまうおそれがある。このように、バンプの
寸法やその相互間隔におのずから限界があるので
回路をフリツプチツプ内に高集積化できてもバン
プを周縁に配列するためにフリツプチツプの寸法
を余分に大きくしてやらねばならなくなる。もち
ろん、ボンデイング線により接続する場合も接続
パツドをチツプの周縁に配列しなければならない
のでこの事情は同様である。
However, as the degree of integration of semiconductor devices increases and it becomes possible to integrate complex or large numbers of circuits into a small area, the number of bumps required for connection with external circuits increases, making it difficult to arrange them all around the periphery of a flip chip. It's getting old. Of course, it is possible to reduce the size of the bumps themselves or reduce the spacing between them, but if the bumps become too small, the reliability of the connection will decrease, and if the bump spacing is made small, the conductor on the wiring board side or the intermediary connection conductor Since the spacing between the wires must be reduced accordingly, there is a lower limit to this, and there is a risk that the wires may be short-circuited during connection work. As described above, there are inherent limits to the size of bumps and their mutual spacing, so even if circuits can be highly integrated within a flip chip, the size of the flip chip must be made extra large in order to arrange the bumps around the periphery. Of course, this situation is similar when connecting by bonding wires, since the connecting pads must be arranged around the periphery of the chip.

本考案はかかる難点を緩和して、フリツプチツ
プを合理的に構成でき配線基板へのその実装密度
を向上できるフリツプチツプの実装構造を得るこ
とを目的とする。
The object of the present invention is to alleviate such difficulties and provide a flip chip mounting structure that can rationally configure flip chips and improve the mounting density on a wiring board.

〔問題点を解決するための手段〕[Means for solving problems]

上述の目的は本考案によれば、それぞれ一面に
複数のパンプ電極を備えた2個の板状フリツプチ
ツプの他面を相互に接着ないし接合した状態で前
記バンプ電極を配線基板の導体に接続し、かつ該
接続を介して前記フリツプチツプが前記配線基板
により支持されることによつて達成される。
According to the present invention, the above-mentioned object is to connect the bump electrodes to a conductor of a wiring board with the other surfaces of two plate-like flip chips each having a plurality of bump electrodes on one surface being adhered or bonded to each other; This is achieved by supporting the flip chip by the wiring board via the connection.

〔作用〕[Effect]

本考案においては、それぞれ片面にバンプ電極
が設けられた2枚のフリツプチツプを背中合わせ
に接着ないしは半田付け等で接合して用いる。こ
の際相互に接合されるフリツプチツプは、それぞ
れ別の回路を集積化したものであつてもよいし、
1個の集積回路を2個のフリツプチツプに分割し
たものであつてもよい。後者の場合、集積回路が
同種回路を複数個集積化したものであるとき簡単
に2個のフリツプチツプに分割できる。また、集
積回路が一続きの回路であるても、多くの場合そ
れぞれ異なる機能をもつ回路の集合であるから、
ふつうは機能別に2個のフリツプチツプに分割す
ることが可能である。かかる分割によつて半導体
装置の見掛けのチツプ面積はほぼ1/2になり、バ
ンプを周縁に配列するために元々寸法を大きくし
ている場合には1/2以下にある。
In the present invention, two flip chips, each having a bump electrode on one side, are used by bonding them back to back by bonding or soldering. At this time, the flip chips that are connected to each other may be integrated with different circuits, or
It may also be one integrated circuit divided into two flip chips. In the latter case, if the integrated circuit is a combination of a plurality of circuits of the same type, it can be easily divided into two flip chips. Furthermore, even if an integrated circuit is a series of circuits, it is often a collection of circuits each with a different function.
Usually, it is possible to divide the flip chip into two flip chips according to function. Due to such division, the apparent chip area of the semiconductor device is approximately halved, and if the size is originally increased to arrange bumps on the periphery, it will be less than halved.

このように2面に振り分けられたバンプ群はそ
れぞれの面倒で従来と同様に直接配線基板の導体
に接続されるなり、前述の仲介接続導体を介して
配線基板の導体に接続されるが、いずれにせよ配
線基板の導体との接続は両面のバンプ群について
別の場所で行なわれるから、各接続点の大きさや
その相互間隔は従来どおりであつてよいことにな
り、バンプの大きさや相互間隔をむりに縮少しな
いでも同じ面積のフリツプチツプあたりのバンプ
を従来の2倍に増すことができ、面積を前述のよ
うにほぼ1/2にした場合でもバンプ数を従来より
40%程度ができる。いずれにせよ、フリツプチツ
プのバンプ数を増やすことができるので、その分
だけ実装密度が上がつて前述の課題が解決され
る。
The bump groups distributed on two sides in this way can be connected directly to the conductor of the wiring board as in the past due to the hassle of each, or they can be connected to the conductor of the wiring board via the aforementioned intermediary connection conductor, but someday In any case, since the connection with the conductor of the wiring board is made at a different location for the bump groups on both sides, the size of each connection point and the mutual spacing between them can be the same as before. It is possible to double the number of bumps per flip chip for the same area without shrinking it unnecessarily, and even when the area is halved as mentioned above, the number of bumps can be increased compared to the conventional one.
Approximately 40% can be achieved. In any case, since the number of bumps on the flip chip can be increased, the packaging density can be increased accordingly, and the above-mentioned problem can be solved.

〔実施例〕〔Example〕

以下、図を参照しながら本考案の実施例を説明
する。第1図は本考案によるフリツプチツプの実
装構造の三つの実施例を示すもので、従来技術に
関する前の図と同一の部分には同一の符号が付さ
れている。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows three embodiments of a flip-chip mounting structure according to the present invention, in which the same parts as in the previous figures relating to the prior art are given the same reference numerals.

同図aは本考案に用いられる両面にバンプ2を
備えたフリツプチツプ1を示し、このフリツプチ
ツプは前述のようにそれぞれ片面にバンプを備え
た2個のフリツプチツプ1a,1bを背中合わせ
に相互に接着ないし接合して構成されている。同
図bはこのフリツプチツプ1をセラミツク配線基
板10に実装する実施例を示すもので、この実施
例においてはフリツプチツプ1の図の下側の面の
バンプには半田バンプ2aが、上側の面のバンプ
には金バンプ2bが用いられる。このフリツプチ
ツプ1の実装に当たつては、まず金バンプ2bが
仲介接続導体21の一端と450℃程度の高温下で
接合される。ついで半田バンプ2aが配線基板の
図の中央部の導体12と半田付けにより接合され
る。この接合温度は半田バンプ2aに用いられた
半田によつても異なるが高温半田のとき例えば
330℃、比較的低温半田のとき例えば230℃であ
り、接合の作業自体は従来と同じ要領でよい。つ
いで仲介接続導体21の他端が配線基板10の図
の左右両側の導体11と従来と同じ要領で例えば
半田付けにより接合される。以上でフリツプチツ
プ1の配線基板10への取り付けとそのバンプの
接続の作業は終わるのであるが、耐振動性や耐衝
撃性が要求される場合、図で一点鎖線で示すよう
に弾性のある保護用の樹脂30を実装部を覆うよ
うに付けた上で硬化させる。この樹脂30として
はシリコーンラバーが最も適当で、必要に応じて
常温硬化形のものや紫外線硬化形のものを選定す
ると便利である。
Figure a shows a flip chip 1 with bumps 2 on both sides used in the present invention, and as described above, this flip chip consists of two flip chips 1a and 1b each having bumps on one side, which are bonded or bonded back to back. It is configured as follows. Figure b shows an embodiment in which this flip chip 1 is mounted on a ceramic wiring board 10. In this embodiment, the bumps on the lower surface of the flip chip 1 in the figure are solder bumps 2a, and the bumps on the upper surface of the flip chip 1 are solder bumps 2a. Gold bumps 2b are used for this. In mounting this flip chip 1, the gold bump 2b is first bonded to one end of the intermediate connection conductor 21 at a high temperature of about 450°C. The solder bumps 2a are then joined to the conductor 12 in the center of the wiring board by soldering. This bonding temperature varies depending on the solder used for the solder bump 2a, but if high temperature solder is used, for example
330°C, for example 230°C for relatively low-temperature soldering, and the joining process itself can be done in the same way as in the past. Then, the other end of the intermediate connection conductor 21 is joined to the conductors 11 on both the left and right sides of the wiring board 10 in the same manner as in the prior art, for example, by soldering. This completes the work of attaching the flip chip 1 to the wiring board 10 and connecting its bumps, but if vibration resistance or impact resistance is required, use an elastic protective A resin 30 is applied so as to cover the mounting portion and then hardened. Silicone rubber is most suitable for this resin 30, and it is convenient to select a room temperature curing type or an ultraviolet curing type as required.

同図cはフリツプチツプ1を通常のプリント配
線基板10に実装する場合の実施例を示すもの
で、この場合のバンプには両面とも金バンプ2b
が用いられ、仲介接続導体21を介して配線基板
の導体11と接続される。また、この実施例にお
けるプリント配線基板には両面に導体11を備え
る両面形が用いられ、かつ窓10aが明けられて
いてフリツプチツプ1がその中に図示のように納
められる。実装に当たつては前の実施例における
と同様にまず金バンプ2bと仲介接続導体21の
一端とを高温下で接合するが、この結合は作業は
フリツプチツプ1の両面の金バンプ2bに対して
同時にすることができる。ついで仲介接続導体2
1の他端と配線基板10の導体11との例えば半
田付けによる接合を専用の工具を用いて配線基板
10の両面の導体11に対して同時に行なう。続
いて実装全体を覆うように樹脂30を前の実施例
を同様に塗布または注入して硬化させる。これに
よつて可撓性の仲介接続導体21はフリツプチツ
プ1とともに樹脂30内に閉じ込められ、仲介接
続導体が振動や衝撃から守られ、かつフリツプチ
ツプが樹脂30を介して配線基板10に担持され
る。
Figure c shows an embodiment in which the flip chip 1 is mounted on an ordinary printed wiring board 10. In this case, the bumps are gold bumps 2b on both sides.
is used, and is connected to the conductor 11 of the wiring board via the intermediate connection conductor 21. Further, the printed wiring board in this embodiment is of a double-sided type with conductors 11 on both sides, and a window 10a is opened in which the flip chip 1 is housed as shown. For mounting, the gold bumps 2b and one end of the intermediary connection conductor 21 are first bonded under high temperature as in the previous embodiment, but this bonding work is performed on the gold bumps 2b on both sides of the flip chip 1. Can be done at the same time. Then the intermediary connection conductor 2
1 and the conductor 11 of the wiring board 10 by, for example, soldering, simultaneously to the conductor 11 on both sides of the wiring board 10 using a special tool. Subsequently, resin 30 is applied or injected in the same manner as in the previous embodiment so as to cover the entire mounting and is cured. As a result, the flexible intermediate connection conductor 21 is confined together with the flip chip 1 within the resin 30, the intermediate connection conductor is protected from vibrations and shocks, and the flip chip is supported on the wiring board 10 via the resin 30.

同図cはやや特殊であるが、フリツプチツプ1
が2枚のセラミツク配線基板10,10の間に実
装される実施例を示す。この場合のバンプには半
田バンプ2aが用いられ、両セラミツク配線基板
10,10は例えばいずれも両面形でその案内孔
10bに挿通した案内ピン40によつて相互の位
置決めが可能になつており、またスペーサ41に
よつて相互間隔を保ち得るようになつている。実
装に当たつては、まず例えば図の下方の配線基板
10上にフリツプチツプ1を半田ペースト等の適
宜の手段で仮付けした後、案内ピン40やスペー
サ41を用いて別の配線基板10をその上に置
き、加熱により半田バンプ2aを融解して配線基
板の導体11と接合すればよい。同様な構造でセ
ラミツク配線基板10を何枚も重ねてその間にフ
リツプチツプ1を実装することができる。
Figure c is a little special, but flip chip 1
An embodiment will be shown in which the circuit board is mounted between two ceramic wiring boards 10, 10. In this case, solder bumps 2a are used as bumps, and both ceramic wiring boards 10, 10 are both double-sided and can be positioned relative to each other by guide pins 40 inserted into guide holes 10b. Further, the spacer 41 allows the mutual spacing to be maintained. For mounting, first, for example, the flip chip 1 is temporarily attached to the wiring board 10 at the bottom of the figure using an appropriate means such as solder paste, and then another wiring board 10 is attached to it using guide pins 40 and spacers 41. The solder bumps 2a may be melted by heating and bonded to the conductors 11 of the wiring board. It is possible to stack a number of ceramic wiring boards 10 with a similar structure and mount the flip chip 1 between them.

以上の例示からもわかるように両面にバンプを
備えたフリツプチツプは種々変形された構造で配
線基板上ないし配線基板間に実装することができ
る。
As can be seen from the above examples, flip chips having bumps on both sides can be mounted on or between wiring boards with variously modified structures.

〔考案の効果〕[Effect of idea]

以上の説明からわかるように、本考案の実装構
造によればそれぞれ一面に複数のパンプ電極を備
えた2個の板状フリツプチツプの他面を相互に接
着ないし接合した状態でバンプ電極を配線基板の
導体に接続し、かつ該接続を介してフリツプチツ
プが配線基板により支持されるようにしたので、
バンプを用いる実装構造がボンデイング線を用い
る実装構造に対してもつ本来の利点をいわば二重
に生かすことにより、半導体装置の配線基板への
実装密度を従来より大幅に向上することができ
る。また、元来は1個である集積回路のフリツプ
チツプを2個に分割して背中合わせに接着ないし
接合して両面バンプのフリツプチツプを構成した
場合には、バンプの寸法や相互間隔にむりがない
ように設計できるようになり、またこれに対応し
て配線基板側の導体配置も楽にできるようにな
る。本考案はとくに外部との接続点数が多い集積
回路の実装に適し、上のようにバンプの配置を合
理的にすることにより、チツプ内の回路配置も合
理化することができる。
As can be seen from the above explanation, according to the mounting structure of the present invention, the bump electrodes are attached to the wiring board with the other surfaces of two plate-like flip chips each having a plurality of pump electrodes on one side bonded or bonded to each other. Since the flip chip is connected to the conductor and the flip chip is supported by the wiring board via the connection,
By taking advantage of the inherent advantages that a mounting structure using bumps has over a mounting structure using bonding lines, it is possible to significantly improve the mounting density of semiconductor devices on a wiring board compared to the conventional method. In addition, when a flip chip with double-sided bumps is constructed by dividing an integrated circuit flip chip, which is originally one, into two pieces and gluing or joining them back to back, it is necessary to make sure that the bump dimensions and mutual spacing are consistent. This also makes it easier to arrange conductors on the wiring board. The present invention is particularly suitable for mounting integrated circuits with a large number of external connection points, and by rationalizing the arrangement of bumps as described above, the circuit arrangement within the chip can also be rationalized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図が本考案に関し、本考案による実装構造
に用いられるフリツプチツプとその若干の実装例
を示す斜視図および断面図である。第2図以降は
従来技術に関し、内第2図は従来のフリツプチツ
プの斜視図、第3図および第4図は該フリツプチ
ツプをそれぞれセラミツク配線基板およびプリン
ト配線基板に実装する要領を示す断面図である。 図において、1……フリツプチツプ、1a,1
b……フリツプチツプの半部、2……バンプ、2
a……半田バンプ、2b……金バンプ、10……
配線基板、10a……配線基板中の窓、10b…
…窓内孔、11,12……配線基板の導体、21
……仲介接続導体、22……絶縁フイルム、30
……樹脂、40……案内ピン、41……スペー
サ、である。
FIG. 1 is a perspective view and a cross-sectional view showing a flip chip used in a mounting structure according to the present invention and some mounting examples thereof. Figure 2 and subsequent figures relate to the prior art, in which Figure 2 is a perspective view of a conventional flip chip, and Figures 3 and 4 are cross-sectional views showing how to mount the flip chip on a ceramic wiring board and a printed wiring board, respectively. . In the figure, 1...flip chip, 1a, 1
b...Half of the flip chip, 2...Bump, 2
a...Solder bump, 2b...Gold bump, 10...
Wiring board, 10a...Window in wiring board, 10b...
...Window inner hole, 11, 12...Conductor of wiring board, 21
...Intermediary connection conductor, 22...Insulating film, 30
. . . resin, 40 . . . guide pin, 41 . . . spacer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] それぞれ一面に複数のパンプ電極を備えた2個
の板状フリツプチツプの他面を相互に接着ないし
接合した状態で前記バンプ電極を配線基板の導体
に接続し、かつ該接続を介して前記フリツプチツ
プが前記配線基板により支持されることを特徴と
するフリツプチツプの実装構造。
The other surfaces of two plate-like flip chips each having a plurality of pump electrodes on one surface are bonded or joined together, and the bump electrodes are connected to a conductor of a wiring board, and the flip chip is connected to the conductor of the wiring board through the connection. A flip chip mounting structure characterized by being supported by a wiring board.
JP1987059805U 1987-04-20 1987-04-20 Expired - Lifetime JPH0543485Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987059805U JPH0543485Y2 (en) 1987-04-20 1987-04-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987059805U JPH0543485Y2 (en) 1987-04-20 1987-04-20

Publications (2)

Publication Number Publication Date
JPS63165855U JPS63165855U (en) 1988-10-28
JPH0543485Y2 true JPH0543485Y2 (en) 1993-11-02

Family

ID=30891644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987059805U Expired - Lifetime JPH0543485Y2 (en) 1987-04-20 1987-04-20

Country Status (1)

Country Link
JP (1) JPH0543485Y2 (en)

Also Published As

Publication number Publication date
JPS63165855U (en) 1988-10-28

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