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JP3883531B2 - Semiconductor device - Google Patents

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Publication number
JP3883531B2
JP3883531B2 JP2003322604A JP2003322604A JP3883531B2 JP 3883531 B2 JP3883531 B2 JP 3883531B2 JP 2003322604 A JP2003322604 A JP 2003322604A JP 2003322604 A JP2003322604 A JP 2003322604A JP 3883531 B2 JP3883531 B2 JP 3883531B2
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JP
Japan
Prior art keywords
base substrate
main surface
semiconductor device
semiconductor pellet
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2003322604A
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Japanese (ja)
Other versions
JP2004007005A (en
Inventor
篤 中村
邦彦 西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
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Publication date
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2003322604A priority Critical patent/JP3883531B2/en
Publication of JP2004007005A publication Critical patent/JP2004007005A/en
Application granted granted Critical
Publication of JP3883531B2 publication Critical patent/JP3883531B2/en
Anticipated expiration legal-status Critical
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description

本発明は、半導体装置及びその製造技術に関し、特に、ベース基板の主面のペレット搭載領域上に半導体ペレットが搭載され、前記半導体ペレットの主面に配置された外部端子に前記ベース基板の裏面に配置された第１電極パッドが電気的に接続される半導体装置及びその製造技術に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device and a manufacturing technique thereof, and in particular, a semiconductor pellet is mounted on a pellet mounting region on a main surface of a base substrate, and an external terminal disposed on the main surface of the semiconductor pellet is attached to the back surface of the base substrate. The present invention relates to a semiconductor device to which the arranged first electrode pads are electrically connected and a technique effective when applied to a manufacturing technique thereof.

高い実装密度が得られる半導体装置として、ＢＧＡ（Ｂall Ｇrid Ａrray）構造の半導体装置が、例えば日経マグロウヒル社発行の日経エレクトロニクス［１９９４年、２月２８日号、第１１１頁乃至第１１７頁］に開示されている。このＢＧＡ構造の半導体装置は、図１６（要部断面図）に示すように、ベース基板１の主面のペレット搭載領域上に半導体ペレット２を搭載し、ベース基板１の主面と対向するその裏面側に複数のバンプ電極４を格子状に配置した構造で構成される。 As a semiconductor device having a high mounting density is obtained, BGA semiconductor device (B all G rid A rray) structure, for example, Nikkei McGraw-Hill, published in Nikkei Electronics [1994 Feb. 28, the 111 pages to 117 pages ] Is disclosed. The semiconductor device of this BGA structure has a semiconductor pellet 2 mounted on the pellet mounting region on the main surface of the base substrate 1 and is opposed to the main surface of the base substrate 1 as shown in FIG. A plurality of bump electrodes 4 are arranged on the back side in a grid pattern.

前記ベース基板１は例えば２層配線構造のプリント配線基板で構成される。ベース基板１の主面の周辺領域（ペレット搭載領域の周囲）には複数の第２電極パッド１Ａが配置される。また、ベース基板１の主面と対向するその裏面には複数の第１電極パッド１Ｂが配置される。第２電極パッド１Ａは、ベース基板１の主面に配置された配線１Ａ１を介してスルーホール配線１Ｃに電気的に接続される。第１電極パッド１Ｂは、ベース基板１の裏面に配置された配線１Ｂ１を介してスルーホール配線１Ｃに電気的に接続される。 The base substrate 1 is composed of a printed wiring board having a two-layer wiring structure, for example. A plurality of second electrode pads 1 </ b> A are arranged in a peripheral region (around the pellet mounting region) of the main surface of the base substrate 1. A plurality of first electrode pads 1 </ b> B are disposed on the back surface of the base substrate 1 that faces the main surface. The second electrode pad 1A is electrically connected to the through-hole wiring 1C via the wiring 1A 1 disposed on the main surface of the base substrate 1. The first electrode pad 1B is electrically connected to the through-hole wiring 1C via the wiring 1B 1 disposed on the back surface of the base substrate 1.

前記半導体ペレット２は例えば単結晶珪素からなる半導体基板２Ｂを主体に構成される。半導体基板２Ｂの主面（素子形成面）には論理回路システム、記憶回路システム、或はそれらの混合回路システムが搭載される。また、半導体基板２Ｂの主面上には複数の外部端子（ボンディングパッド）２Ａが配置される。この外部端子２Ａは、半導体基板２Ｂの主面上に形成された配線層のうち最上層の配線層に形成される。   The semiconductor pellet 2 is mainly composed of a semiconductor substrate 2B made of, for example, single crystal silicon. A logic circuit system, a memory circuit system, or a mixed circuit system thereof is mounted on the main surface (element formation surface) of the semiconductor substrate 2B. A plurality of external terminals (bonding pads) 2A are disposed on the main surface of the semiconductor substrate 2B. The external terminal 2A is formed in the uppermost wiring layer among the wiring layers formed on the main surface of the semiconductor substrate 2B.

前記半導体ペレット２の外部端子２Ａはベース基板１の主面に配置された第２電極パッド１Ａにボンディングワイヤ６を介して電気的に接続される。つまり、半導体ペレット２の外部端子２Ａは、ボンディングワイヤ３、第２電極パッド１Ａ、配線１Ａ１、スルーホール配線１Ｃ、配線１Ｂ１の夫々を介して第１電極パッド１Ｂに電気的に接続される。 The external terminals 2A of the semiconductor pellet 2 are electrically connected to the second electrode pads 1A disposed on the main surface of the base substrate 1 through bonding wires 6. That is, the external terminal 2A of the semiconductor pellet 2 is electrically connected to the first electrode pad 1B via each of the bonding wire 3, the second electrode pad 1A, the wiring 1A 1 , the through-hole wiring 1C, and the wiring 1B 1. .

前記半導体ペレット２、ボンディングワイヤ６等は、ベース基板１の主面上に形成された樹脂封止体７で封止される。樹脂封止体７はトランスファモール法で形成される。
前記ベース基板１の第１電極パッド１Ｂの表面上にはバンプ電極４が電気的及び機械的に接続される。バンプ電極４は例えばＰｂ−Ｓｎ系の合金材で形成される。
このように構成されるＢＧＡ構造の半導体装置は実装基板の実装面上に実装され、そのバンプ電極４は実装基板の実装面に配置された電極パッドに電気的及び機械的に接続される。 The semiconductor pellet 2, the bonding wire 6 and the like are sealed with a resin sealing body 7 formed on the main surface of the base substrate 1. The resin sealing body 7 is formed by a transfer molding method.
A bump electrode 4 is electrically and mechanically connected to the surface of the first electrode pad 1B of the base substrate 1. The bump electrode 4 is made of, for example, a Pb—Sn alloy material.
The semiconductor device having the BGA structure configured as described above is mounted on the mounting surface of the mounting substrate, and the bump electrodes 4 are electrically and mechanically connected to the electrode pads arranged on the mounting surface of the mounting substrate.

また、高い実装密度が得られる半導体装置として、ベース基板をフレキシブル基板で構成した半導体装置が、例えば米国特許第５１４８２６５号に開示されている。この半導体装置は、フレキシブル基板で構成されたベース基板の主面のペレット搭載領域上に半導体ペレットをその主面を下にして搭載し、半導体ペレットの主面に配置された外部端子とベース基板の裏面に配置された第２電極パッドとをボンディングワイヤで電気的に接続した構造で構成される。ベース基板の第２電極パッドはその裏面に配置された配線を介してその裏面に配置された第１電極パッドに電気的に接続される。第１電極パッドの表面にはバンプ電極が電気的及び機械的に接続される。
このように構成される半導体装置は実装基板の実装面上に実装され、そのバンプ電極は実装基板の実装面に配置された電極パッドに電気的及び機械的に接続される。 In addition, as a semiconductor device that can obtain a high mounting density, a semiconductor device in which a base substrate is formed of a flexible substrate is disclosed in, for example, US Pat. No. 5,148,265. In this semiconductor device, a semiconductor pellet is mounted on a pellet mounting region on a main surface of a base substrate composed of a flexible substrate with the main surface facing down, and an external terminal and a base substrate disposed on the main surface of the semiconductor pellet are mounted. The second electrode pad disposed on the back surface is electrically connected with a bonding wire. The second electrode pad of the base substrate is electrically connected to the first electrode pad disposed on the back surface via the wiring disposed on the back surface. A bump electrode is electrically and mechanically connected to the surface of the first electrode pad.
The semiconductor device configured as described above is mounted on the mounting surface of the mounting substrate, and the bump electrodes are electrically and mechanically connected to electrode pads arranged on the mounting surface of the mounting substrate.

米国特許第５１４８２６５号US Pat. No. 5,148,265

（１）ＢＧＡ構造の半導体装置において、図１６に示すように、ベース基板１の主面に配置された第２電極パッド１Ａは、スルーホール配線１Ｃを介してベース基板１の裏面に配置された第１電極パッド１Ｂに電気的に接続される。スルーホール配線１Ｃは、ベース基板１のスルーホール内に形成されたホール領域と、ベース基板１の主面及び裏面に形成されたランド領域（フリンジ部）とで構成される。スルーホールの内径寸法は例えばφ０．３［ｍｍ］程度に設定され、スルーホール配線１Ｃのランド領域の外径寸法は例えばφ０．６［ｍｍ］程度に設定される。このスルーホールの内径寸法及びスルーホール配線１Ｃのランド領域の外径寸法は、第２電極パッド１Ａとスルーホール配線１Ｃとを電気的に接続する配線１Ａ１の配線幅及び第１電極パッド１Ｂとスルーホール配線１Ｃとを電気的に接続する配線１Ｂ１の配線幅に比べて大きく構成される。
一方、半導体ペレット２に搭載される回路システムは高集積化の傾向にあり、この回路システムの高集積化に伴って半導体ペレット２の外部端子２Ａの数及びベース基板１の第２電極パッド１Ａの数は増加する。つまり、回路システムの高集積化に伴い、第２電極パッド１Ａと第１電極パッド１Ｂとを電気的に接続するスルーホール配線１Ｃの数は増加する。このため、スルーホール配線１Ｃの数に相当する分、ベース基板１の外形サイズが増加し、半導体装置が大型化する問題があった。 (1) In the semiconductor device having the BGA structure, as shown in FIG. 16, the second electrode pad 1A disposed on the main surface of the base substrate 1 is disposed on the back surface of the base substrate 1 through the through-hole wiring 1C. It is electrically connected to the first electrode pad 1B. The through-hole wiring 1 </ b> C includes a hole region formed in the through-hole of the base substrate 1 and land regions (fringe portions) formed on the main surface and the back surface of the base substrate 1. The inner diameter dimension of the through hole is set to, for example, about φ0.3 [mm], and the outer diameter dimension of the land region of the through-hole wiring 1C is set to, for example, about φ0.6 [mm]. The inner diameter dimension of the through hole and the outer diameter dimension of the land area of the through hole wiring 1C are the wiring width of the wiring 1A 1 that electrically connects the second electrode pad 1A and the through hole wiring 1C, and the first electrode pad 1B. It is configured to be larger than the wiring width of the wiring 1B 1 that electrically connects the through-hole wiring 1C.
On the other hand, the circuit system mounted on the semiconductor pellet 2 tends to be highly integrated. As the circuit system is highly integrated, the number of external terminals 2A of the semiconductor pellet 2 and the number of second electrode pads 1A of the base substrate 1 are increased. The number increases. That is, as the circuit system is highly integrated, the number of through-hole wirings 1C that electrically connect the second electrode pads 1A and the first electrode pads 1B increases. For this reason, there is a problem in that the outer size of the base substrate 1 increases by the amount corresponding to the number of through-hole wirings 1C, and the semiconductor device becomes larger.

（２）ＢＧＡ構造の半導体装置において、スルーホール配線１Ｃの増加に伴い、スルーホール配線１Ｃは半導体ペレット２からその外側に向って遠い位置に配置される。このため、第２電極パッド１Ａとスルーホール配線１Ｃとを電気的に接続する配線１Ａ１の長さ及び第１電極パッド１Ｂとスルーホール配線１Ｃとを電気的に接続する配線１Ｂ１の長さが長くなるので、インダクタンスが増加し、半導体装置の動作速度が低下するという問題があった。 (2) In the semiconductor device having the BGA structure, the through-hole wiring 1C is arranged at a position farther from the semiconductor pellet 2 toward the outside thereof as the through-hole wiring 1C increases. For this reason, the length of the wiring 1A 1 that electrically connects the second electrode pad 1A and the through-hole wiring 1C and the length of the wiring 1B 1 that electrically connects the first electrode pad 1B and the through-hole wiring 1C. Therefore, there is a problem that the inductance increases and the operation speed of the semiconductor device decreases.

（３）ベース基板をフレキシブル基板で構成した半導体装置において、フレキシブル基板は、例えばポリエステルフィルム、ポリイミドフィルムで構成される。このフレキシブル基板は、ガラス繊維にエポキシ樹脂、ポリイミド樹脂等を含浸させたリジット基板に比べてヤング率が低く軟らかい（硬度が低い）。このため、半導体ペレットの主面に配置された外部端子とベース基板の裏面に配置された第２電極パッドとをボンディングワイヤで電気的に接続する際、第２電極パッドに加えるボンディング荷重がベース基板に吸収されてしまい、ボンディング荷重、超音波振動が第２電極パッドに有効に伝わらず、ボンディングワイヤと第２電極パッドとの接続強度が低下し、ボンディングワイヤの接続不良が発生し、半導体装置の電気的信頼性が低下するという問題があった。 (3) In the semiconductor device in which the base substrate is configured by a flexible substrate, the flexible substrate is configured by, for example, a polyester film or a polyimide film. This flexible substrate has a lower Young's modulus and is softer (lower hardness) than a rigid substrate in which glass fiber is impregnated with epoxy resin, polyimide resin, or the like. Therefore, when the external terminals arranged on the main surface of the semiconductor pellet and the second electrode pads arranged on the back surface of the base substrate are electrically connected with bonding wires, the bonding load applied to the second electrode pads is The bonding load and the ultrasonic vibration are not effectively transmitted to the second electrode pad, the connection strength between the bonding wire and the second electrode pad is lowered, and the bonding wire connection failure occurs. There was a problem that the electrical reliability decreased.

（４）ベース基板をフレキシブル基板で構成した半導体装置において、フレキシブル基板は、リジット基板に比べて平面方向の熱膨張係数が大きく、更にヤング率が低く曲がりやすい（剛性が小さい）。このため、実装基板の実装面上に半導体装置を実装する際、実装時のリフロー熱でベース基板に反り、ねじれ等の変形が生じ、実装基板の実装面に対するベース基板の裏面の平坦度が低下し、半導体装置の実装精度が低下するという問題があった。 (4) In a semiconductor device in which a base substrate is formed of a flexible substrate, the flexible substrate has a larger coefficient of thermal expansion in the planar direction than a rigid substrate, and has a low Young's modulus and is easily bent (small rigidity). For this reason, when mounting a semiconductor device on the mounting surface of the mounting substrate, the reflow heat during mounting warps the base substrate, causing deformation such as torsion, and the flatness of the back surface of the base substrate with respect to the mounting surface of the mounting substrate decreases. However, there is a problem that the mounting accuracy of the semiconductor device is lowered.

本発明の目的は、半導体装置の小型化を図ることが可能な技術を提供することにある。
本発明の他の目的は、前記半導体装置の動作速度の高速化を図ることが可能な技術を提供することにある。
本発明の他の目的は、半導体装置の電気的信頼性を高めることが可能な技術を提供することにある。
本発明の他の目的は、半導体装置の実装精度を高めることが可能な技術を提供することにある。
本発明の他の目的は、前記目的を達成する半導体装置の製造技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。 An object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.
Another object of the present invention is to provide a technique capable of increasing the operating speed of the semiconductor device.
Another object of the present invention is to provide a technique capable of improving the electrical reliability of a semiconductor device.
Another object of the present invention is to provide a technique capable of increasing the mounting accuracy of a semiconductor device.
Another object of the present invention is to provide a semiconductor device manufacturing technique that achieves the above object.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記の
とおりである。
すなわち、本発明の半導体装置は、第１主面及び前記第１主面とは反対側の第２主面と、前記第１主面から前記第２主面に貫通するスリットとを有し、前記第２主面上に複数の電極パッドを有し、リジット基板で構成されるベース基板と、主面に回路システムと複数の外部端子を有する半導体ペレットであって、前記半導体ペレットの前記主面が前記ベース基板の前記第１主面に向かい合い、かつ、前記複数の外部端子が前記スリットの内側に平面的に位置し、かつ、前記スリットの一部の領域が前記半導体ペレットの外側に平面的に位置するように前記ベース基板上に搭載された半導体ペレットと、前記半導体ペレットの前記複数の外部端子と前記ベース基板の前記複数の電極パッドとを各々電気的に接続する複数のボンディングワイヤと、前記ベース基板の前記第１主面及び前記第２主面の両側に形成され、前記スリットを介して互いに連続した樹脂封止体であって、前記複数のボンディングワイヤを封止する樹脂封止体と、前記ベース基板の前記第２主面上に形成され、前記複数の電極パッドと各々電気的に接続された複数のバンプ電極と、を備えている。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, the semiconductor device of the present invention, the first main surface and the first major surface and a second main surface on the opposite side, and a slit penetrating from the first main surface to the second major surface, the second have a plurality of electrode pads on the major surface, a base substrate composed of rigid substrate, a semiconductor pellet having a circuit system and a plurality of external terminals on the main surface, the main surface of the semiconductor pellet Faces the first main surface of the base substrate, the plurality of external terminals are planarly located inside the slit, and a partial region of the slit is planar outside the semiconductor pellet. a semiconductor pellet mounted on the base substrate so as to be positioned, a plurality of bonding wires that connect the said plurality of external terminals of the semiconductor pellet and the plurality of electrode pads of the base substrate respectively electrically A resin sealing body which is formed on both sides of the first main surface and the second main surface of the base substrate and is continuous with each other through the slit, and seals the plurality of bonding wires. When the formed on the base substrate of the second main surface, wherein a plurality of electrode pads and each electrically connected to a plurality of bump electrodes, that are provided by the.

上述した手段によれば、半導体ペレットの外部端子とベース基板の第１電極パッドとをボンディングワイヤ、第２電極パッドの夫々を介して電気的に接続することができるので、第２電極パッドと第１電極パッドとを電気的に接続するスルーホール配線を廃止することができる。この結果、スルーホール配線の占有面積（ランド領域の面積）に相当する分、ベース基板の外形サイズを縮小することができるので、半導体装置の小型化を図ることができる。 According to the hand stage described above, the semiconductor pellet of the external terminal and the base first electrode pads and the bonding wires of the substrate, it is possible to electrically connect via a respective second electrode pads, and the second electrode pad The through-hole wiring that electrically connects the first electrode pad can be eliminated. As a result, the outer size of the base substrate can be reduced by an amount corresponding to the area occupied by the through-hole wiring (area of the land region), so that the semiconductor device can be reduced in size.

また、スルーホール配線の占有面積に相当する分、第１電極パッドを第２電極パッドに近づけることができるので、第２電極パッドと第１電極パッドとを電気的に接続するベース基板の配線の長さを短くすることができる。この結果、インダクタンスを低減することができるので、半導体装置の動作速度の高速化を図ることができる。   Further, since the first electrode pad can be brought close to the second electrode pad by an amount corresponding to the occupied area of the through-hole wiring, the wiring of the base substrate that electrically connects the second electrode pad and the first electrode pad can be obtained. The length can be shortened. As a result, the inductance can be reduced, so that the operation speed of the semiconductor device can be increased.

また、リジット基板はフレキシブル基板に比べてヤング率が高く硬いので、半導体ペレットの主面に配置された外部端子とベース基板の裏面に配置された第２電極パッドとをボンディングワイヤで電気的に接続する際、第２電極パッドに加えるボンディング荷重がベース基板に吸収されず、ボンディング荷重、超音波振動が第２電極パッドに有効に伝わる。この結果、ボンディングワイヤと第２電極パッドとの接続強度を高めることができるので、ボンディングワイヤの接続不良を防止でき、半導体装置の電気的信頼性を高めることができる。   In addition, the rigid substrate has a higher Young's modulus and is harder than the flexible substrate, so that the external terminals arranged on the main surface of the semiconductor pellet and the second electrode pads arranged on the back surface of the base substrate are electrically connected by a bonding wire. In this case, the bonding load applied to the second electrode pad is not absorbed by the base substrate, and the bonding load and ultrasonic vibration are effectively transmitted to the second electrode pad. As a result, since the connection strength between the bonding wire and the second electrode pad can be increased, a bonding wire connection failure can be prevented, and the electrical reliability of the semiconductor device can be increased.

また、リジット基板はフレキシブル基板に比べて平面方向の熱膨張係数が小さく、更にヤング率が高く曲がりにくいので、実装基板の実装面上に半導体装置を実装する際、実装時のリフロー熱によるベース基板の変形（反り、ねじれ等）を防止することができる。この結果、実装基板の実装面に対するベース基板の裏面の平坦度を確保することができるので、半導体装置の実装精度を高めることができる。   In addition, the rigid substrate has a smaller coefficient of thermal expansion in the plane direction than the flexible substrate, and has a high Young's modulus and is difficult to bend. Therefore, when mounting a semiconductor device on the mounting surface of the mounting substrate, the base substrate due to reflow heat during mounting Deformation (warping, twisting, etc.) can be prevented. As a result, since the flatness of the back surface of the base substrate with respect to the mounting surface of the mounting substrate can be ensured, the mounting accuracy of the semiconductor device can be increased.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
ベース基板の主面のペレット搭載面上に半導体ペレットが搭載され、前記半導体ペレットの主面に配置された外部端子に前記ベース基板の裏面に配置された第１電極パッドが電気的に接続される半導体装置の小型化を図ることができる。
また、前記半導体装置の動作速度の高速化を図ることができる。
また、前記半導体装置の電気的信頼性を高めることができる。
また、前記半導体装置の実装精度を高めることができる。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
A semiconductor pellet is mounted on the pellet mounting surface of the main surface of the base substrate, and a first electrode pad disposed on the back surface of the base substrate is electrically connected to an external terminal disposed on the main surface of the semiconductor pellet. The semiconductor device can be reduced in size.
In addition, the operation speed of the semiconductor device can be increased.
In addition, the electrical reliability of the semiconductor device can be improved.
In addition, the mounting accuracy of the semiconductor device can be increased.

以下、本発明の構成について、ＢＧＡ構造を採用する半導体装置に本発明を適用した実施例とともに説明する。
なお、実施例を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。 The configuration of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor device adopting a BGA structure.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.

（実施例１）
本発明の実施例１であるＢＧＡ構造を採用する半導体装置の概略構成を図１（主面側の平面図）、図２（図１に示すＡ−Ａ線の位置で切った断面図）、図３（図２の要部拡大断面図）及び図４（裏面側の樹脂封止体を除去した状態を示す裏面側の要部拡大平面図）に示す。 Example 1
FIG. 1 (plan view on the main surface side), FIG. 2 (cross-sectional view taken along the line AA shown in FIG. 1) of the schematic configuration of the semiconductor device adopting the BGA structure which is Embodiment 1 of the present invention, FIG. 3 (enlarged cross-sectional view of the main part of FIG. 2) and FIG. 4 (enlarged plan view of the main part on the back side showing the state where the resin sealing body on the back side is removed) are shown.

図１、図２、図３及図４に示すように、半導体装置は、ベース基板１の主面のペレット搭載領域上に半導体ペレット２を搭載し、ベース基板１の主面と対向するその裏面側に複数のバンプ電極４を格子状に配置する。   As shown in FIGS. 1, 2, 3, and 4, the semiconductor device has the semiconductor pellet 2 mounted on the pellet mounting region on the main surface of the base substrate 1, and its back surface facing the main surface of the base substrate 1. A plurality of bump electrodes 4 are arranged in a grid pattern on the side.

前記ベース基板１は、例えばプリント配線基板で構成される。プリント配線基板は、ガラス繊維に例えばエポキシ樹脂、ポリイミド樹脂、マレイミド樹脂等を含浸させたリジット基板の表面に配線を形成した構造で構成される。つまり、ベース基板１はリジット基板で構成される。リジット基板は、ポリエステルフィルム、ポリイミドフィルム等からなるフレキシブル基板に比べてヤング率が高く硬い。また、リジット基板は、フレキシブル基板に比べて平面方向の熱膨張係数が小さく、更にヤング率が高く曲がりにくい。例えば、ガラス繊維にエポキシ樹脂又はポリイミド樹脂を含浸させたリジット基板は、１６〜２２［ＧＰａ］程度のヤング率を有し、１０〜２０×１０-6［１／℃］程度の熱膨張係数を有する。なお、ポリエステルフィルム又はポリイミドフィルムからなるフレキシブル基板は、２〜５［ＧＰａ］程度のヤング率を有し、２０〜２５×１０-6［１／℃］程度の熱膨張係数を有する。 The base substrate 1 is composed of, for example, a printed wiring board. The printed wiring board has a structure in which wiring is formed on the surface of a rigid board in which glass fiber is impregnated with, for example, epoxy resin, polyimide resin, maleimide resin or the like. That is, the base substrate 1 is constituted by a rigid substrate. A rigid substrate has a high Young's modulus and is harder than a flexible substrate made of a polyester film, a polyimide film, or the like. In addition, the rigid substrate has a smaller coefficient of thermal expansion in the plane direction than the flexible substrate, and has a higher Young's modulus and is difficult to bend. For example, a rigid substrate obtained by impregnating glass fiber with an epoxy resin or a polyimide resin has a Young's modulus of about 16 to 22 [GPa] and a thermal expansion coefficient of about 10 to 20 × 10 −6 [1 / ° C.]. Have. In addition, the flexible substrate which consists of a polyester film or a polyimide film has a Young's modulus of about 2-5 [GPa], and has a thermal expansion coefficient of about 20-25 × 10 −6 [1 / ° C.].

前記ベース基板１の裏面には複数の第２電極パッド１Ａ及び複数の第１電極パッド１Ｂが配置される。この第２電極パッド１Ａ、第１電極パッド１Ｂの夫々は、ベース基板１の裏面に配置された配線１Ｂ１を介して電気的に接続される。第２電極パッド１Ａ、第１電極パッド１Ｂ、配線の１Ｂ１夫々は例えばＣｕ膜で形成される。
前記第１電極パッド１Ｂの表面には、バンプ電極４が電気的及び機械的に接続される。このバンプ電極４は例えばＰｂ−Ｓｎ系の合金材で形成される。 A plurality of second electrode pads 1 </ b> A and a plurality of first electrode pads 1 </ b> B are disposed on the back surface of the base substrate 1. The second electrode pad 1A, Each of the first electrode pads 1B, are electrically connected through a wiring 1B 1 disposed on the rear surface of the base substrate 1. The second electrode pad 1A, the first electrode pads 1B, 1B 1 each wiring is formed of, for example, a Cu film.
A bump electrode 4 is electrically and mechanically connected to the surface of the first electrode pad 1B. The bump electrode 4 is made of, for example, a Pb—Sn alloy material.

前記半導体ペレット２は、その主面（図２、図３において下面）を下にしてベース基板１の主面のペレット搭載領域上に搭載される。つまり、半導体ペレット２は、ベース基板１の主面のペレット搭載領域上にフェースダウン方式で搭載される。半導体ペレット２の主面とベース基板１の主面のペレット搭載領域との間には絶縁層３が介在される。絶縁層３は例えばポリイミド系、エポキシ系又はシリコン系の低弾性樹脂で形成される。   The semiconductor pellet 2 is mounted on the pellet mounting region of the main surface of the base substrate 1 with its main surface (the lower surface in FIGS. 2 and 3) facing down. That is, the semiconductor pellet 2 is mounted on the pellet mounting region on the main surface of the base substrate 1 by a face-down method. An insulating layer 3 is interposed between the main surface of the semiconductor pellet 2 and the pellet mounting region on the main surface of the base substrate 1. The insulating layer 3 is formed of, for example, a polyimide, epoxy, or silicon low elastic resin.

前記半導体ペレット２は例えば平面が方形状に形成される。この半導体ペレット２は例えば単結晶珪素からなる半導体基板１Ｂを主体に構成される。半導体基板１Ｂの主面（素子形成面）には論理回路システム、記憶回路システム、或はそれらの混合回路システムが搭載される。また、半導体基板１Ｂの主面上には、方形状の各辺に沿って配列された複数の外部端子（ボンディングパッド）２Ａが配置される。この外部端子２Ａは、半導体基板２Ｂの主面上に形成された配線層のうち、最上層の配線層に形成される。つまり、半導体ペレット２の主面の外周囲には複数の外部端子２Ａが各辺毎に配置される。   For example, the semiconductor pellet 2 is formed in a rectangular plane. The semiconductor pellet 2 is mainly composed of a semiconductor substrate 1B made of, for example, single crystal silicon. A logic circuit system, a memory circuit system, or a mixed circuit system thereof is mounted on the main surface (element formation surface) of the semiconductor substrate 1B. In addition, a plurality of external terminals (bonding pads) 2A arranged along each side of the rectangular shape are disposed on the main surface of the semiconductor substrate 1B. The external terminal 2A is formed in the uppermost wiring layer among the wiring layers formed on the main surface of the semiconductor substrate 2B. That is, a plurality of external terminals 2 </ b> A are arranged for each side on the outer periphery of the main surface of the semiconductor pellet 2.

前記半導体ペレット２の外部端子２Ａと前記ベース基板１の第２電極パッド１Ａとは、ベース基板１に形成されたスリット５を通してボンディングワイヤ６で電気的に接続される。ボンディングワイヤ６は、例えば金（Ａｕ）ワイヤ、銅（Ｃｕ）ワイヤ、アルミニウム（Ａｌ）ワイヤ、或は金属ワイヤの表面に絶縁性樹脂を被覆した被覆ワイヤ等で形成される。このボンディングワイヤ６は、例えば熱圧着に超音波振動を併用したボンディング法でボンディングされる。   The external terminal 2A of the semiconductor pellet 2 and the second electrode pad 1A of the base substrate 1 are electrically connected by a bonding wire 6 through a slit 5 formed in the base substrate 1. The bonding wire 6 is formed of, for example, a gold (Au) wire, a copper (Cu) wire, an aluminum (Al) wire, or a coated wire in which an insulating resin is coated on the surface of a metal wire. The bonding wire 6 is bonded by, for example, a bonding method in which ultrasonic vibration is used in combination with thermocompression bonding.

前記ベース基板１のスリット５は、半導体ペレット２の主面にその一辺に沿って複数配列された外部端子２Ａの配列方向に沿って形成され、半導体ペレット２の各辺毎に配置される。つまり、本実施例のベース基板１は４本のスリット５を配置する。この４本のスリット５の夫々は半導体ペレット２の外部端子２Ａ上に配置される。   The slits 5 of the base substrate 1 are formed along the arrangement direction of the external terminals 2 </ b> A arranged along the one side of the main surface of the semiconductor pellet 2, and are arranged for each side of the semiconductor pellet 2. That is, the base substrate 1 of the present embodiment is provided with four slits 5. Each of the four slits 5 is disposed on the external terminal 2 </ b> A of the semiconductor pellet 2.

前記ベース基板１の第２電極パッド１Ａは、スリット５で仕切られたベース基板１の裏面の両脇の夫々の領域に配置される。スリット５で仕切られたベース基板１の裏面の一方の領域（半導体ペレット２に対して内側の領域）に配置される第２電極パッド１Ａには電源として例えば動作電位（例えば３．３［Ｖ］）、基準電位（例えば０Ｖ［Ｖ］）等が印加される。スリット５で仕切られたベース基板１の裏面の他方の領域（半導体ペレット２に対して外側の領域）に配置される第２電極パッド１Ａには信号として例えば入出力信号、制御信号等が印加される。   The second electrode pads 1 </ b> A of the base substrate 1 are disposed in respective regions on both sides of the back surface of the base substrate 1 partitioned by the slits 5. For example, an operating potential (for example, 3.3 [V]) is used as a power source for the second electrode pad 1A disposed in one region on the back surface of the base substrate 1 partitioned by the slit 5 (region inside the semiconductor pellet 2). ), A reference potential (for example, 0 V [V]) or the like is applied. For example, an input / output signal, a control signal, or the like is applied as a signal to the second electrode pad 1A disposed in the other region on the back surface of the base substrate 1 partitioned by the slit 5 (region outside the semiconductor pellet 2). The

前記半導体ペレット２において、外部端子２Ａは半導体ペレット２の一辺に対して例えば１００個ずつ配列され、その配列ピッチは例えば１００［μｍ］程度に設定される。この外部端子２Ａの数は、半導体ペレット２に搭載される回路システムの高集積化や動作速度の高速化に伴って増加される。   In the semiconductor pellet 2, for example, 100 external terminals 2A are arranged with respect to one side of the semiconductor pellet 2, and the arrangement pitch is set to about 100 [μm], for example. The number of external terminals 2A is increased as the circuit system mounted on the semiconductor pellet 2 is highly integrated and the operation speed is increased.

前記ベース基板１において、スリット５で仕切られたベース基板１の裏面の一方の領域に配置される第２電極パッド１Ａは半導体ペレット２の一辺に対して例えば５０個ずつ配列され、スリット５で仕切られたベース基板１の裏面の他方の領域に配置される第２電極パッド１Ａは半導体ペレット２の一辺に対して例えば５０個ずつ配列される。この第２電極パッド１Ａは半導体ペレット２の外部端子２Ａと同様に微細化することができないので、その配列ピッチは外部端子２Ａの配列ピッチに比べて広く構成され、例えば２００［μｍ］程度に設定される。つまり、ベース基板１の第２電極パッド１Ａは半導体ペレット２の一辺に対して２列で配置されているので、ベース基板１の第２電極パッド１Ａの配列ピッチを半導体ペレット２の外部端子２Ａの配列ピッチに対して２倍に設定しても、半導体ペレット２の一辺に対する第２電極パッド１Ａのパッド配列の長さを半導体ペレット２の一辺に配列された外部端子２Ａの端子配列の長さとほぼ同一にすることができると共に、半導体ペレット２の外部端子２Ａと対向する位置にベース基板１の第２電極パッド１Ａを配置することができる。   In the base substrate 1, for example, 50 second electrode pads 1 </ b> A arranged in one region on the back surface of the base substrate 1 partitioned by the slit 5 are arranged with respect to one side of the semiconductor pellet 2. For example, 50 second electrode pads 1 </ b> A arranged in the other region of the back surface of the base substrate 1 are arranged with respect to one side of the semiconductor pellet 2. Since the second electrode pad 1A cannot be miniaturized similarly to the external terminal 2A of the semiconductor pellet 2, the arrangement pitch thereof is wider than the arrangement pitch of the external terminal 2A, and is set to, for example, about 200 [μm]. Is done. That is, since the second electrode pads 1A of the base substrate 1 are arranged in two rows with respect to one side of the semiconductor pellet 2, the arrangement pitch of the second electrode pads 1A of the base substrate 1 is set to the external terminal 2A of the semiconductor pellet 2. Even if it is set to be twice the arrangement pitch, the length of the pad arrangement of the second electrode pad 1A with respect to one side of the semiconductor pellet 2 is almost equal to the length of the terminal arrangement of the external terminals 2A arranged on one side of the semiconductor pellet 2. While being able to make it the same, the 2nd electrode pad 1A of the base substrate 1 can be arrange | positioned in the position facing the external terminal 2A of the semiconductor pellet 2. FIG.

前記ベース基板１の主面のペレット搭載領域を除くその周辺領域上は樹脂封止体７で覆われ、前記ボンディングワイヤ６は樹脂封止体７で封止される。つまり、樹脂封止体７はベース基板１の主面側及びその裏面側に形成される。樹脂封止体７は、低応力化を図る目的として、フェノール系硬化剤、シリコーンゴム及びフィラーが添加されたエポキシ系の樹脂７Ａで形成される。
前記半導体ペレット２の主面と対向するその裏面はベース基板１の周辺領域上を覆う樹脂封止体７から露出される。 The peripheral region except the pellet mounting region on the main surface of the base substrate 1 is covered with a resin sealing body 7, and the bonding wire 6 is sealed with the resin sealing body 7. That is, the resin sealing body 7 is formed on the main surface side and the back surface side of the base substrate 1. The resin sealing body 7 is formed of an epoxy resin 7A to which a phenolic curing agent, silicone rubber, and filler are added for the purpose of reducing stress.
The back surface opposite to the main surface of the semiconductor pellet 2 is exposed from the resin sealing body 7 covering the peripheral region of the base substrate 1.

前記樹脂封止体７は、図５（要部断面図）に示す成形金型１０を用いたトランスファモールド法で形成される。成形金型１０は、上型１０Ａと下型１０Ｂとで形成されるキャビティ１１及びこのキャビティ１１に連結される流入ゲート１３を備え、更に、図示していないが、ポット、ランナーの夫々を備えている。ポットはランナー、流入ゲート１３の夫々を通してキャビティ１１に連結される。   The resin sealing body 7 is formed by a transfer molding method using a molding die 10 shown in FIG. The molding die 10 includes a cavity 11 formed by an upper mold 10A and a lower mold 10B, and an inflow gate 13 connected to the cavity 11, and further includes a pot and a runner, which are not shown. Yes. The pot is connected to the cavity 11 through the runner and the inflow gate 13.

前記キャビティ１１は上型１０Ａに形成された凹部１１Ａと下型１０Ｂに形成された凹部１１Ｂとで構成される。凹部１１Ａにはポットからランナー、流入ゲート１３の夫々を通して樹脂（７Ａ）が供給される。凹部１１Ｂにはベース基板１が装着される。   The cavity 11 includes a recess 11A formed in the upper mold 10A and a recess 11B formed in the lower mold 10B. Resin (7A) is supplied from the pot to the recess 11A through the runner and the inflow gate 13 respectively. The base substrate 1 is mounted in the recess 11B.

前記凹部１１Ｂには凹部１２が形成される。凹部１２は、凹部１１Ｂに装着されたベース基板１のスリット５と対向する位置に配置され、スリット５の延在方向に沿って形成される。凹部１２には、半導体ペレット２の外部端子（２Ａ）とベース基板１の第２電極パッド（１Ａ）とを電気的に接続したボンディングワイヤ（６）の一部及びベース基板１の第２電極パッド（１Ａ）が配置され、凹部１１Ａからベース基板１のスリット５を通して樹脂（７Ａ）が供給される。
前記凹部１２には、図示していないが、気泡の巻き込みによるボイドの発生を防止する目的として、ガス抜き孔が設けられる。 A recess 12 is formed in the recess 11B. The recess 12 is disposed at a position facing the slit 5 of the base substrate 1 mounted in the recess 11 </ b> B, and is formed along the extending direction of the slit 5. In the recess 12, a part of the bonding wire (6) that electrically connects the external terminal (2 A) of the semiconductor pellet 2 and the second electrode pad (1 A) of the base substrate 1 and the second electrode pad of the base substrate 1 (1A) is disposed, and the resin (7A) is supplied from the recess 11A through the slit 5 of the base substrate 1.
Although not shown, the recess 12 is provided with a vent hole for the purpose of preventing generation of voids due to entrainment of bubbles.

次に、前記半導体装置の製造方法について、図６乃至図９を用いて説明する。
まず、リジット基板で構成されたベース基板１を用意する。ベース基板１にはスリット５が形成され、その裏面には第２電極パッド（１Ａ）、第１電極パッド（１Ｂ）、配線（１Ｂ１）の夫々が配置される。 Next, a method for manufacturing the semiconductor device will be described with reference to FIGS.
First, a base substrate 1 composed of a rigid substrate is prepared. A slit 5 is formed in the base substrate 1, and the second electrode pad (1A), the first electrode pad (1B), and the wiring (1B 1 ) are arranged on the back surface thereof.

次に、図６（断面図）に示すように、前記ベース基板１の主面のペレット搭載領域上に半導体ペレット２を搭載する。半導体ペレット２はベース基板１の主面のペレット搭載領域上に絶縁層３を介在して固着される。
次に、ボンディングステージ（ヒートブロック）１４上に前記半導体ペレット２を下にして前記ベース基板１を装着する。ボンディングステージ１４には、半導体ペレット２を収納する凹部１４Ａが形成される。ベース基板１、半導体ペレット２の夫々はボンディングステージ１４で２００［℃］前後に加熱される。 Next, as shown in FIG. 6 (cross-sectional view), the semiconductor pellet 2 is mounted on the pellet mounting region on the main surface of the base substrate 1. The semiconductor pellet 2 is fixed on the pellet mounting region on the main surface of the base substrate 1 with an insulating layer 3 interposed.
Next, the base substrate 1 is mounted on the bonding stage (heat block) 14 with the semiconductor pellet 2 facing down. The bonding stage 14 is formed with a recess 14 </ b> A for housing the semiconductor pellet 2. Each of the base substrate 1 and the semiconductor pellet 2 is heated to about 200 [° C.] on the bonding stage 14.

次に、図７（要部断面図）に示すように、前記半導体ペレット２の主面に配置された外部端子２Ａと前記ベース基板１の裏面に配置された第２電極パッド（１Ａ）とをボンディングワイヤ６で電気的に接続する。ボンディングワイヤ６は、ベース基板１のスリット５を通して、半導体ペレット２の外部端子２Ａ、ベース基板１の第２電極パッド（１Ａ）の夫々に接続される。ボンディングワイヤ６の接続は、熱圧着に超音波振動を併用したボンディング法で行なわれる。この工程において、ベース基板１はフレキシブル基板に比べてヤング率が高く硬いリジット基板で構成されているので、第２電極パッド（１Ａ）に加えるボンディング荷重がベース基板１に吸収されず、ボンディング荷重及び超音波振動を第２電極パッド（１Ａ）に有効に伝えることができる。また、ベース基板１はフレキシブル基板に比べて平面方向の熱膨張係数が小さく、更にヤング率が高く曲がりにくいリジット基板で構成されているので、ベース基板１の熱膨張による第２電極パッド（１Ａ）の位置及び半導体ペレット２の外部端子２Ａの位置ずれを低減することができる。   Next, as shown in FIG. 7 (main part sectional view), external terminals 2A arranged on the main surface of the semiconductor pellet 2 and second electrode pads (1A) arranged on the back surface of the base substrate 1 are formed. Electrical connection is made by the bonding wire 6. The bonding wires 6 are connected to the external terminals 2A of the semiconductor pellet 2 and the second electrode pads (1A) of the base substrate 1 through the slits 5 of the base substrate 1, respectively. The bonding wire 6 is connected by a bonding method in which ultrasonic vibration is used in combination with thermocompression bonding. In this process, since the base substrate 1 is composed of a rigid substrate having a higher Young's modulus than the flexible substrate, the bonding load applied to the second electrode pad (1A) is not absorbed by the base substrate 1, and the bonding load and Ultrasonic vibration can be effectively transmitted to the second electrode pad (1A). Further, the base substrate 1 is composed of a rigid substrate that has a smaller coefficient of thermal expansion in the plane direction than the flexible substrate, and has a high Young's modulus and is difficult to bend. And the positional deviation of the external terminal 2A of the semiconductor pellet 2 can be reduced.

次に、図８（要部断面図）に示すように、成形金型１０の上型１０Ａと下型１０Ｂとで形成されるキャビティ１１内に前記ベース基板１及び半導体ペレット２を配置すると共に、キャビティ１１の凹部１１Ｂにベース基板１を装着する。ボンディングワイヤ６の一部及びベース基板１の第２電極パッド（１Ａ）は、凹部１１Ｂに形成された凹部１２に配置される。成形金型１０は、キャビティ１１内に供給される樹脂（７Ａ）の流動性を高めるため、予め１７０〜１８０［℃］程度の温度に加熱される。この工程において、ベース基板１は成形金型１０の加熱によって１７０〜１８０［℃］程度の温度に加熱されるが、ベース基板１はフレキシブル基板に比べて平面方向の熱膨張係数が小さく、更にヤング率が高く曲がりにくいリジット基板で構成されているので、成形金型１０の加熱によるベース基板１の反り、ねじれ等の変形を防止することができる。   Next, as shown in FIG. 8 (main part sectional view), the base substrate 1 and the semiconductor pellet 2 are arranged in the cavity 11 formed by the upper mold 10A and the lower mold 10B of the molding die 10, The base substrate 1 is mounted in the recess 11 </ b> B of the cavity 11. A part of the bonding wire 6 and the second electrode pad (1A) of the base substrate 1 are disposed in the recess 12 formed in the recess 11B. The molding die 10 is heated to a temperature of about 170 to 180 [° C.] in advance in order to improve the fluidity of the resin (7A) supplied into the cavity 11. In this step, the base substrate 1 is heated to a temperature of about 170 to 180 [° C.] by heating the molding die 10, but the base substrate 1 has a smaller coefficient of thermal expansion in the plane direction than the flexible substrate, and is further Since it is composed of a rigid substrate that has a high rate and is difficult to bend, deformation of the base substrate 1 due to heating of the mold 10 can be prevented.

次に、前記成形金型１０のポットに樹脂タブレットを投入する。樹脂タブレットは、予めヒータで加熱され、粘度を下げてからポットに投入される。ポットに投入された樹脂ダブレットは、成形金型１０から熱を与えられ、更に粘度が下げられる。   Next, a resin tablet is put into the pot of the molding die 10. The resin tablet is heated by a heater in advance to lower the viscosity, and then is put into the pot. The resin doublet put in the pot is heated by the molding die 10 and the viscosity is further lowered.

次に、前記樹脂タブレットをトランスファモールド装置のプランジャで加圧し、ポットからランナー、流入ゲート１３の夫々を通してキャビティ１１の凹部１１Ａ内及び凹部１２内に樹脂７Ａを供給し、図９（要部断面図）に示すように、ベース基板１の主面の周辺領域上を覆い、半導体ペレット２の裏面を露出し、かつボンディングワイヤ６を封止する樹脂封止体７を形成する。凹部１２の樹脂７Ａは、凹部１１Ａからベース基板１のスリット５を通して供給される。この工程において、凹部１１Ａからスリット５を通して凹部１２に供給される樹脂７Ａはボンディングワイヤ６の一端側からその軸方向に即ち縦方向に流れるので、ベース基板１の平面方向に即ち横方向に樹脂が流れる場合に比べて、樹脂の流れによるボンディングワイヤ６の変形を防止することができる。   Next, the resin tablet is pressurized with a plunger of a transfer mold device, and the resin 7A is supplied from the pot into the recess 11A and the recess 12 of the cavity 11 through the runner and the inflow gate 13, respectively. ), A resin sealing body 7 that covers the peripheral region of the main surface of the base substrate 1, exposes the back surface of the semiconductor pellet 2, and seals the bonding wires 6 is formed. The resin 7 </ b> A in the recess 12 is supplied from the recess 11 </ b> A through the slit 5 in the base substrate 1. In this step, the resin 7A supplied from the recess 11A to the recess 12 through the slit 5 flows from one end side of the bonding wire 6 in the axial direction, that is, in the vertical direction. Compared to the case of flowing, deformation of the bonding wire 6 due to the flow of resin can be prevented.

次に、前記成形金型１０からベース基板１を取り出し、ベース基板１の裏面の第１電極パッド１Ｂの表面にバンプ電極４を電気的及び機械的に接続することにより、図１、図２、図３及び図４に示す半導体装置がほぼ完成する。   Next, the base substrate 1 is taken out from the molding die 10 and the bump electrode 4 is electrically and mechanically connected to the surface of the first electrode pad 1B on the back surface of the base substrate 1 to obtain FIGS. The semiconductor device shown in FIGS. 3 and 4 is almost completed.

この後、半導体装置は製品として出荷される。製品として出荷された半導体装置は、図１０（断面図）に示すように、実装基板１５の実装面上に実装され、半導体装置のバンプ電極４は実装基板１５の実装面に配置された電極パッド１５Ａに電気的及び機械的に接続される。半導体装置のバンプ電極４と実装基板１５の電極パッド１５Ａとの接続は、バンプ電極４の材質によって異なるが、例えば２１０〜２３０［℃］程度のリフロー温度雰囲気中で行なわれる。この実装工程において、ベース基板１はフレキシブル基板に比べて平面方向の熱膨張係数が小さく、更にヤング率が高く曲がりにくいリジット基板で構成されているので、実装時のリフロー熱によるベース基板１の変形を防止することができる。   Thereafter, the semiconductor device is shipped as a product. As shown in FIG. 10 (cross-sectional view), the semiconductor device shipped as a product is mounted on the mounting surface of the mounting substrate 15, and the bump electrodes 4 of the semiconductor device are electrode pads arranged on the mounting surface of the mounting substrate 15. Electrically and mechanically connected to 15A. The connection between the bump electrode 4 of the semiconductor device and the electrode pad 15 </ b> A of the mounting substrate 15 is performed in a reflow temperature atmosphere of, for example, about 210 to 230 [° C.], depending on the material of the bump electrode 4. In this mounting process, the base substrate 1 is composed of a rigid substrate that has a smaller coefficient of thermal expansion in the plane direction than that of the flexible substrate, and has a high Young's modulus and is difficult to bend. Therefore, the base substrate 1 is deformed by reflow heat during mounting. Can be prevented.

このように、本実施例によれば、以下の作用効果が得られる。
（１）ベース基板１の主面のペレット搭載領域上に半導体ペレット２が搭載され、前記半導体ペレット２の主面に配置された外部端子２Ａに前記ベース基板１の裏面に配置された第１電極パッド１Ｂが電気的に接続される半導体装置において、前記ベース基板１をリジット基板で構成し、前記ベース基板１の第１電極パッド１Ｂをその裏面に配置された第２電極パッド１Ａに電気的に接続し、前記半導体ペレット２をその主面を下にして前記ベース基板１の主面のペレット搭載領域上に搭載し、前記半導体ペレット２の外部端子２Ａと前記ベース基板１の第２電極パッド１Ａとを前記ベース基板１に形成されたスリット５を通してボンディングワイヤ６で電気的に接続する。この構成により、半導体ペレット２の外部端子２Ａとベース基板１の電極パッド１Ｂとをボンディングワイヤ６、電極パッド１Ａの夫々を介して電気的に接続することができるので、第２電極パッド１Ａと第１電極パッド１Ｂとを電気的に接続するスルーホール配線を廃止することができる。この結果、スルーホール配線の占有面積（ランド領域の面積）に相当する分、ベース基板１の外形サイズを縮小することができるので、半導体装置の小型化を図ることができる。 Thus, according to the present embodiment, the following effects can be obtained.
(1) The semiconductor pellet 2 is mounted on the pellet mounting region on the main surface of the base substrate 1, and the first electrode disposed on the back surface of the base substrate 1 on the external terminal 2 </ b> A disposed on the main surface of the semiconductor pellet 2. In the semiconductor device to which the pad 1B is electrically connected, the base substrate 1 is composed of a rigid substrate, and the first electrode pad 1B of the base substrate 1 is electrically connected to the second electrode pad 1A disposed on the back surface thereof. The semiconductor pellet 2 is mounted on the pellet mounting region on the main surface of the base substrate 1 with its main surface facing down, and the external terminal 2A of the semiconductor pellet 2 and the second electrode pad 1A of the base substrate 1 are mounted. Are electrically connected by a bonding wire 6 through a slit 5 formed in the base substrate 1. With this configuration, the external terminal 2A of the semiconductor pellet 2 and the electrode pad 1B of the base substrate 1 can be electrically connected via the bonding wire 6 and the electrode pad 1A, respectively. The through-hole wiring that electrically connects the one-electrode pad 1B can be eliminated. As a result, the outer size of the base substrate 1 can be reduced by an amount corresponding to the area occupied by the through-hole wiring (area of the land region), so that the semiconductor device can be downsized.

また、スルーホール配線の占有面積に相当する分、第１電極パッド１Ｂを第２電極パッド１Ａに近づけることができるので、第２電極パッド１Ａと第１電極パッド１Ｂとを電気的に接続するベース基板１の配線１Ｂ１の長さを短くすることができる。この結果、インダクタンスを低減することができるので、半導体装置の動作速度の高速化を図ることができる。 In addition, since the first electrode pad 1B can be brought closer to the second electrode pad 1A by an amount corresponding to the area occupied by the through-hole wiring, the base for electrically connecting the second electrode pad 1A and the first electrode pad 1B. it is possible to shorten the length of wiring 1B 1 of the substrate 1. As a result, the inductance can be reduced, so that the operation speed of the semiconductor device can be increased.

また、リジット基板はフレキシブル基板に比べてヤング率が高く硬いので、半導体ペレット２の主面に配置された外部端子２Ａとベース基板１の裏面に配置された第２電極パッド１Ａとをボンディングワイヤ６で電気的に接続する際、第２電極パッド１Ａに加えるボンディング荷重がベース基板１に吸収されず、ボンディング荷重、超音波振動が第２電極パッド１Ａに有効に伝わる。この結果、ボンディングワイヤ６と第２電極パッド１Ａとの接続強度を高めることができるので、ボンディングワイヤ６の接続不良を防止でき、半導体装置の電気的信頼性を高めることができる。   Further, since the rigid substrate has a higher Young's modulus and is harder than the flexible substrate, the external terminal 2A disposed on the main surface of the semiconductor pellet 2 and the second electrode pad 1A disposed on the back surface of the base substrate 1 are bonded to the bonding wire 6. When the electrical connection is made, the bonding load applied to the second electrode pad 1A is not absorbed by the base substrate 1, and the bonding load and ultrasonic vibration are effectively transmitted to the second electrode pad 1A. As a result, since the connection strength between the bonding wire 6 and the second electrode pad 1A can be increased, connection failure of the bonding wire 6 can be prevented, and the electrical reliability of the semiconductor device can be increased.

また、リジット基板はフレキシブル基板に比べて平面方向の熱膨張係数が小さく、更にヤング率が高く曲がりにくいので、実装基板１５の実装面上に半導体装置を実装する際、実装時のリフロー熱によるベース基板１の変形（反り、ねじれ等）を防止することができる。この結果、実装基板１５の実装面に対するベース基板１の裏面の平坦度を確保することができるので、半導体装置の実装精度を高めることができる。   In addition, the rigid substrate has a smaller coefficient of thermal expansion in the plane direction than the flexible substrate, and has a high Young's modulus and is difficult to bend. Therefore, when mounting a semiconductor device on the mounting surface of the mounting substrate 15, the base due to reflow heat during mounting is used. Deformation (warping, twisting, etc.) of the substrate 1 can be prevented. As a result, since the flatness of the back surface of the base substrate 1 with respect to the mounting surface of the mounting substrate 15 can be ensured, the mounting accuracy of the semiconductor device can be increased.

また、リジット基板はフレキシブル基板に比べて平面方向の熱膨張係数が小さく、更にヤング率が高く曲がりにくいので、電極パッド１Ｂの数の増加に伴ってベース基板１の外形サイズが増加しても、ベース基板１の反りを１００［μｍ］以内に抑えることができる。   In addition, since the rigid substrate has a smaller coefficient of thermal expansion in the plane direction than the flexible substrate, and has a high Young's modulus and is difficult to bend, even if the outer size of the base substrate 1 increases as the number of electrode pads 1B increases, The warp of the base substrate 1 can be suppressed within 100 [μm].

また、ベース基板１の反りを１００［μｍ］以内に抑えることができるので、ベース基板１の反りを防止する目的で設けられる補強基板を廃止することができる。この結果、補強基板を設けた半導体装置に比べて半導体装置の製造コストを低減することができる。   In addition, since the warp of the base substrate 1 can be suppressed within 100 [μm], the reinforcing substrate provided for the purpose of preventing the warp of the base substrate 1 can be eliminated. As a result, the manufacturing cost of the semiconductor device can be reduced as compared with the semiconductor device provided with the reinforcing substrate.

また、リジット基板の裏面に第２電極パッド１Ａ、第１電極パッド１Ｂ、配線１Ｂ１の夫々を配置した単層構造のプリント配線基板でベース基板１を構成することができるので、リジット基板の主面及び裏面に配置した２層構造のプリント配線基板で構成されるベース基板に比べてベース基板１の部品コストを低減することができる。この結果、半導体装置の製造コストを低減することができる。 Further, since the base substrate 1 can be constituted by a printed wiring board having a single layer structure in which the second electrode pad 1A, the first electrode pad 1B, and the wiring 1B 1 are arranged on the back surface of the rigid board, The component cost of the base substrate 1 can be reduced as compared with a base substrate composed of a printed wiring board having a two-layer structure arranged on the front and back surfaces. As a result, the manufacturing cost of the semiconductor device can be reduced.

（２）前記スリット５を前記半導体ペレット２の主面に複数配列された外部端子２Ａの配列方向に沿って形成し、かつ前記半導体ペレット２の外部端子２Ａ上に配置する。この構成により、スリット５は半導体ペレット２の専有面積内に配置されるので、スリット５の専有面積に相当するベース基板１の外形サイズの大型化を抑制することができる。 (2) The slits 5 are formed along the arrangement direction of the external terminals 2 </ b> A arranged on the main surface of the semiconductor pellet 2 and disposed on the external terminals 2 </ b> A of the semiconductor pellet 2. With this configuration, since the slit 5 is disposed within the exclusive area of the semiconductor pellet 2, it is possible to suppress an increase in the outer size of the base substrate 1 corresponding to the exclusive area of the slit 5.

（３）前記電極パッド１Ａを前記スリット５で仕切られたベース基板１の裏面の両脇の夫々の領域に配置する。この構成により、半導体ペレット２の外部端子２Ａとベース基板１の第２電極パッド１Ａとを電気的に接続する電源経路を増加することができるので、信号の同時切り替え時に発生する電源ノイズを低減することができ、半導体装置の誤動作を防止できる。 (3) The electrode pads 1A are arranged in the respective regions on both sides of the back surface of the base substrate 1 partitioned by the slits 5. With this configuration, it is possible to increase the power supply path for electrically connecting the external terminal 2A of the semiconductor pellet 2 and the second electrode pad 1A of the base substrate 1, thereby reducing the power supply noise generated at the time of simultaneous signal switching. And malfunction of the semiconductor device can be prevented.

また、半導体ペレット２の外部端子２Ａの配列ピッチに対してベース基板１の第２電極パット１Ａの配列ピッチを広く構成しても、半導体ペレット２の一辺に対する第２電極パッド１Ａのパッド配列の長さを半導体ペレット２の一辺に配列された外部端子２Ａの端子配列の長さとほぼ同一にすることができるので、第２電極パッド１Ａのパッド配列の長さに起因するボンディングワイヤ６のワイヤ長の増加を防止することができ、トランスファモールド法に基づいてボンディングワイヤ６を封止体７で封止する際、樹脂の流動によるボンディングワイヤ６のワイヤ流れを防止することができる。   Even if the arrangement pitch of the second electrode pads 1A of the base substrate 1 is made wider than the arrangement pitch of the external terminals 2A of the semiconductor pellet 2, the length of the pad arrangement of the second electrode pads 1A with respect to one side of the semiconductor pellet 2 Since the length of the external terminal 2A arranged on one side of the semiconductor pellet 2 can be made substantially the same as the length of the terminal arrangement of the bonding electrode 6 due to the length of the pad arrangement of the second electrode pad 1A. The increase can be prevented, and when the bonding wire 6 is sealed with the sealing body 7 based on the transfer molding method, the wire flow of the bonding wire 6 due to the flow of the resin can be prevented.

また、半導体ペレット２の外部端子２Ａと対向する位置にベース基板１の第２電極パッド１Ａを配置することができるので、ボンディングワイヤ６の長さを均一にすることができ、半導体ペレット２の外部端子２Ａとベース基板１の第２電極パッド１Ａとの間における信号経路のインダクタンスを均一にすることができる。   In addition, since the second electrode pad 1A of the base substrate 1 can be disposed at a position facing the external terminal 2A of the semiconductor pellet 2, the length of the bonding wire 6 can be made uniform, and the outside of the semiconductor pellet 2 The inductance of the signal path between the terminal 2A and the second electrode pad 1A of the base substrate 1 can be made uniform.

（４）前記半導体ペレット２の主面と対向するその裏面を前記ベース基板１の主面の周辺領域上を覆う樹脂封止体７から露出させる。この構成により、半導体ペレット２に搭載された回路システムの動作で発生する熱を半導体ペレット２の裏面から外部に放出することができるので、半導体装置の放熱効率を高めることができる。
また、ベース基板１の機械的強度を樹脂封止体７の機械的強度で補うことができるので、実装時のリフロー熱によるベース基板１の変形（反り、ねじれ等）を防止することができる。 (4) The back surface opposite to the main surface of the semiconductor pellet 2 is exposed from the resin sealing body 7 covering the peripheral region of the main surface of the base substrate 1. With this configuration, heat generated by the operation of the circuit system mounted on the semiconductor pellet 2 can be released to the outside from the back surface of the semiconductor pellet 2, so that the heat dissipation efficiency of the semiconductor device can be increased.
In addition, since the mechanical strength of the base substrate 1 can be supplemented by the mechanical strength of the resin sealing body 7, deformation (warping, twisting, etc.) of the base substrate 1 due to reflow heat during mounting can be prevented.

（５）前記ボンディングワイヤ６を樹脂封止体７で封止する。この構成により、外部からの衝撃や接触によるボンディングワイヤ６の変形を防止することができるので、半導体装置の電気的信頼性を高めることができる。 (5) The bonding wire 6 is sealed with a resin sealing body 7. With this configuration, it is possible to prevent the bonding wire 6 from being deformed due to an external impact or contact, so that the electrical reliability of the semiconductor device can be improved.

（６）樹脂封止体７をベース基板１の主面側及びその裏面側に形成する。この構成により、温度サイクル試験時やバンプ電極４の接続時に発生する熱ストレスでベース基板１から樹脂封止体７が剥がれるのを防止することができるので、半導体装置の信頼性を高めることができる。 (6) The resin sealing body 7 is formed on the main surface side and the back surface side of the base substrate 1. With this configuration, it is possible to prevent the resin sealing body 7 from being peeled off from the base substrate 1 due to thermal stress that occurs during a temperature cycle test or when the bump electrodes 4 are connected, so that the reliability of the semiconductor device can be improved. .

（７）ベース基板１の主面のペレット搭載領域上に半導体ペレット２が搭載され、前記半導体ペレット２の主面に配置された外部端子２Ａに前記ベース基板１の裏面に配置された第１電極パッド１Ｂが電気的に接続される半導体装置の製造方法において、リジット基板で構成されたベース基板１の主面のペレット搭載領域上に半導体ペレット２をその主面を下にして搭載する工程と、前記半導体ペレット２の外部端子２Ａと、前記ベース基板１の第１電極パッド１Ｂに電気的に接続され、かつ前記ベース基板１の裏面に配置された第２電極パッド１Ａとを前記ベース基板１に形成されたスリット５を通してボンディングワイヤ６で電気的に接続する工程とを備える。これにより、半導体ペレット２の外部端子２Ａとベース基板１の第１電極パッド１Ｂとをボンディングワイヤ６、第２電極パッド１Ａの夫々を介して電気的に接続するので、第２電極パッド１Ａと第１電極パッド１Ｂとを電気的に接続するスルーホール配線（１Ｃ）が廃止され、このスルーホール配線の占有面積に相当する分、外形サイズが縮小されたベース基板１を使用することができる。この結果、外形サイズの小さい半導体装置を製造することができる。 (7) The semiconductor pellet 2 is mounted on the pellet mounting region on the main surface of the base substrate 1, and the first electrode disposed on the back surface of the base substrate 1 on the external terminal 2 </ b> A disposed on the main surface of the semiconductor pellet 2. In the method of manufacturing a semiconductor device in which the pad 1B is electrically connected, a step of mounting the semiconductor pellet 2 on the pellet mounting region of the main surface of the base substrate 1 constituted by a rigid substrate with the main surface facing down; An external terminal 2A of the semiconductor pellet 2 and a second electrode pad 1A electrically connected to the first electrode pad 1B of the base substrate 1 and disposed on the back surface of the base substrate 1 are connected to the base substrate 1. Electrically connecting with the bonding wire 6 through the formed slit 5. As a result, the external terminal 2A of the semiconductor pellet 2 and the first electrode pad 1B of the base substrate 1 are electrically connected via the bonding wire 6 and the second electrode pad 1A, respectively. The through-hole wiring (1C) that electrically connects the one-electrode pad 1B is abolished, and the base substrate 1 having a reduced external size corresponding to the occupied area of the through-hole wiring can be used. As a result, a semiconductor device with a small outer size can be manufactured.

また、半導体ペレット２の外部端子２Ａとベース基板１の第１電極パッド１Ｂとをボンディングワイヤ６、第２電極パッド１Ａの夫々を介して電気的に接続するので、第２電極パッド１Ａと第１電極パッド１Ｂとを電気的に接続するスルーホール配線（１Ｃ）が廃止され、このスルーホール配線の占有面積に相当する分、第２電極パッド１Ａと第１電極パッド１Ｂとを電気的に接続する配線１Ｂ１の長が短いベース基板１を使用することができる。この結果、動作速度が速い半導体装置を製造することができる。 Further, since the external terminal 2A of the semiconductor pellet 2 and the first electrode pad 1B of the base substrate 1 are electrically connected through the bonding wire 6 and the second electrode pad 1A, the second electrode pad 1A and the first electrode pad 1B are electrically connected. The through-hole wiring (1C) for electrically connecting the electrode pad 1B is eliminated, and the second electrode pad 1A and the first electrode pad 1B are electrically connected by an amount corresponding to the occupied area of the through-hole wiring. The base substrate 1 having a short length of the wiring 1B 1 can be used. As a result, a semiconductor device having a high operating speed can be manufactured.

フレキシブル基板に比べてヤング率が高く硬いリジット基板で構成されたベース基板１を使用しているので、半導体ペレット２の主面に配置された外部端子２Ａとベース基板１の裏面に配置された第２電極パッド１Ａとをボンディングワイヤ６で電気的に接続する際、第２電極パッド１Ａに加えるボンディング荷重がベース基板１に吸収されず、ボンディング荷重、超音波振動が第２電極パッド１Ａに有効に伝わる。この結果、ボンディングワイヤ６と第２電極パッド１Ａとの接続強度を高めることができるので、電気的信頼性の高い半導体装置を製造することができる。   Since the base substrate 1 made of a rigid substrate having a higher Young's modulus than the flexible substrate is used, the external terminals 2A arranged on the main surface of the semiconductor pellet 2 and the second terminals arranged on the back surface of the base substrate 1 are used. When the two-electrode pad 1A is electrically connected by the bonding wire 6, the bonding load applied to the second electrode pad 1A is not absorbed by the base substrate 1, and the bonding load and ultrasonic vibration are effectively applied to the second electrode pad 1A. It is transmitted. As a result, since the connection strength between the bonding wire 6 and the second electrode pad 1A can be increased, a semiconductor device with high electrical reliability can be manufactured.

また、フレキシブル基板に比べて平面方向の熱膨張係数が小さく、更にヤング率が高く曲がりにくいリジット基板で構成されたベース基板１を使用しているので、実装基板１５の実装面上に半導体装置を実装する際、実装時のリフロー熱によるベース基板１の変形（反り、ねじれ等）を防止することができる。この結果、実装基板１５の実装面に対するベース基板１の裏面の平坦度を確保することができるので、実装精度の高い半導体装置を製造することができる。   In addition, since the base substrate 1 made of a rigid substrate having a smaller coefficient of thermal expansion in the planar direction than that of the flexible substrate and having a high Young's modulus and is difficult to bend is used, the semiconductor device is mounted on the mounting surface of the mounting substrate 15. When mounting, deformation (warp, twist, etc.) of the base substrate 1 due to reflow heat during mounting can be prevented. As a result, since the flatness of the back surface of the base substrate 1 with respect to the mounting surface of the mounting substrate 15 can be ensured, a semiconductor device with high mounting accuracy can be manufactured.

（８）前記ボンディングワイヤ６で電気的に接続する工程の後に、前記ベース基板１の主面の周辺領域上を覆い、かつ前記ボンディングワイヤ６を封止する樹脂封止体７をトランスファモールド法で形成する工程を備える。これにより、フレキシブル基板に比べて平面方向の熱膨張係数が小さく、更に、ヤング率が高く曲がりにくいリジット基板で構成されたベース基板１を使用しているので、成形金型１０の加熱によるベース基板１の反り、ねじれ等の変形を防止することができる。 (8) After the step of electrically connecting with the bonding wire 6, the resin sealing body 7 covering the peripheral region of the main surface of the base substrate 1 and sealing the bonding wire 6 is formed by a transfer mold method. Forming. As a result, the base substrate 1 made of a rigid substrate having a smaller coefficient of thermal expansion in the planar direction than that of the flexible substrate and having a high Young's modulus and is difficult to bend is used. It is possible to prevent deformation such as warping and twisting.

また、凹部１１Ａからスリット５を通して凹部１２に供給される樹脂７Ａはボンディングワイヤ６の一端側からその軸方向に即ち縦方向に流れるので、ベース基板１の平面方向に即ち横方向に樹脂が流れる場合に比べて、樹脂７Ａの流れによるボンディングワイヤ６の変形を防止することができる。   Further, since the resin 7A supplied from the recess 11A to the recess 12 through the slit 5 flows in the axial direction, that is, in the vertical direction from one end side of the bonding wire 6, the resin flows in the plane direction of the base substrate 1, that is, in the lateral direction. In comparison with this, deformation of the bonding wire 6 due to the flow of the resin 7A can be prevented.

なお、前記樹脂封止体７は、図１１（断面図）に示すように、第２電極パッド１Ａ、第１電極パッド１Ｂの夫々の表面上を除くベース基板１の裏面上に形成してもよい。この場合、ベース基板１を樹脂封止体７で挾み込む形状になるので、ベース基板１の反りを防止することができる。   As shown in FIG. 11 (cross-sectional view), the resin sealing body 7 may be formed on the back surface of the base substrate 1 except on the surfaces of the second electrode pad 1A and the first electrode pad 1B. Good. In this case, since the base substrate 1 is shaped so as to be swollen with the resin sealing body 7, the warp of the base substrate 1 can be prevented.

また、前記ベース基板１は、図示していないが、リジット基板を複数枚積み重ねた積層構造で構成してもよい。この場合、フレキシブル基板を複数枚積み重ねて形成した積層構造のベース基板に比べて、半導体装置の製造コストを低減することができる。   Further, although not shown, the base substrate 1 may have a laminated structure in which a plurality of rigid substrates are stacked. In this case, the manufacturing cost of the semiconductor device can be reduced as compared with a base substrate having a stacked structure formed by stacking a plurality of flexible substrates.

（実施例２）
本発明の実施例２であるＢＧＡ構造を採用する半導体装置の概略構成を図１２（断面図）及び図１３（裏面側の樹脂封止体を除去した状態を示す裏面側の要部拡大平面図）に示す。 (Example 2)
12 (cross-sectional view) and FIG. 13 (enlarged plan view of the main part on the back surface side showing the state where the resin sealing body on the back surface side is removed) showing a schematic configuration of the semiconductor device adopting the BGA structure which is Embodiment 2 of the present invention. ).

図１２及び図１３に示すように、半導体装置は、ベース基板１の主面のペレット搭載領域上に絶縁層３を介在して半導体ペレット２をフェースダウン方式で搭載し、ベース基板１の裏面側に複数のバンプ電極４を格子状に配置する。   As shown in FIGS. 12 and 13, the semiconductor device mounts the semiconductor pellet 2 in a face-down manner on the pellet mounting region of the main surface of the base substrate 1 with the insulating layer 3 interposed therebetween, and the back surface side of the base substrate 1. A plurality of bump electrodes 4 are arranged in a grid pattern.

前記半導体ペレット２の主面の中央部には、その長辺に沿って配列された複数の外部端子２Ａが配置される。この複数の外部端子２Ａの夫々は、ベース基板１の裏面に配置された複数の第２電極パッド１Ａの夫々に、ベース基板１に形成されたスリット５を通してボンディングワイヤ６で電気的に接続される。複数の第２電極パッド１Ａの夫々はベース基板１の裏面に配置された複数の第１電極パッド１Ｂの夫々に配線１Ｂ１を介して電気的に接続される。この複数の第１電極パッド１Ｂの夫々の表面にはバンプ電極４が電気的かつ機械的に接続される。つまり、半導体ペレット２の外部端子２Ａは、ボンディングワイヤ６、第２電極パッド１Ａ、配線１Ｂ１の夫々を介して第１電極パッド１Ｂに電気的に接続される。 In the central portion of the main surface of the semiconductor pellet 2, a plurality of external terminals 2A arranged along the long side thereof are arranged. Each of the plurality of external terminals 2 </ b> A is electrically connected to each of the plurality of second electrode pads 1 </ b> A disposed on the back surface of the base substrate 1 through bonding wires 6 through slits 5 formed in the base substrate 1. . Each of the plurality of second electrode pads 1A are electrically connected through a wiring 1B 1 to each of the plurality of first electrode pads 1B disposed on the back surface of the base substrate 1. Bump electrodes 4 are electrically and mechanically connected to the respective surfaces of the plurality of first electrode pads 1B. That is, the external terminal 2A of the semiconductor pellet 2, the bonding wires 6, the second electrode pads 1A, is electrically connected to the first electrode pad 1B through the respective wire 1B 1.

前記ベース基板１のスリット５は、半導体ペレット２の主面の中央部にその長辺に沿って配列された複数の外部端子２Ａの配列方向に沿って形成される。また、スリット５は、ベース基板１の裏面側の開口寸法に比べてその主面側の開口寸法を小さくしたテーパ形状で構成される。   The slit 5 of the base substrate 1 is formed in the central portion of the main surface of the semiconductor pellet 2 along the arrangement direction of the plurality of external terminals 2A arranged along the long side. Further, the slit 5 has a tapered shape in which the opening size on the main surface side is smaller than the opening size on the back surface side of the base substrate 1.

このように、本実施例によれば、前述の実施例１と同様の作用効果が得られると共に、スリット５をテーパ形状に構成することにより、半導体ペレット２の外部端子２Ａにボンディングワイヤ６の一端をボンディングする際、ベース基板１とボンディングツールとの接触を防止することができるので、ボンディング工程における半導体装置の組立て歩留まりを高めることができる。   As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and the slit 5 can be formed into a tapered shape so that one end of the bonding wire 6 is connected to the external terminal 2A of the semiconductor pellet 2. Since the contact between the base substrate 1 and the bonding tool can be prevented when bonding, the assembly yield of the semiconductor device in the bonding process can be increased.

（実施例３）
本発明の実施例３であるＢＧＡ構造を採用する半導体装置の概略構成を図１４（裏面側の樹脂封止体を除去した状態を示す裏面側の要部平面図）に示す。 (Example 3)
FIG. 14 (plan view of the main part on the back side showing the state where the resin sealing body on the back side is removed) shows a schematic configuration of a semiconductor device adopting the BGA structure which is Embodiment 3 of the present invention.

図１４に示すように、半導体装置は、ベース基板１の主面のペレット搭載領域上に絶縁層（３）を介在して半導体ペレット２をフェースダウン方式で搭載し、ベース基板１の裏面側に複数のバンプ電極４を格子状に配置する。   As shown in FIG. 14, the semiconductor device mounts the semiconductor pellet 2 in a face-down manner on the pellet mounting region on the main surface of the base substrate 1 with an insulating layer (3) interposed therebetween. A plurality of bump electrodes 4 are arranged in a grid pattern.

前記半導体ペレット２の主面の外周囲には、その各辺に沿って配列された複数の外部端子２Ａが配置される。また、半導体ペレット２の主面の中央部には、その長辺若しくは短辺に沿って配列された複数の外部端子２Ａが配置される。この複数の外部端子２Ａの夫々は、ベース基板１の裏面に配置された複数の第２電極パッド１Ａの夫々に、ベース基板１に形成されたスリット５を通してボンディングワイヤ６で電気的に接続される。複数の第２電極パッド１Ａの夫々は、ベース基板１の裏面に配置された複数の第１電極パッド１Ｂの夫々に配線（１Ｂ１）を介して電気的に接続される。この複数の第１電極パッド１Ｂの夫々の表面上にはバンプ電極４が電気的及び機械的に接続される。つまり、半導体ペレット２の外部端子２Ａは、ボンディングワイヤ６、第２電極パッド１Ａ、配線１Ｂ１の夫々を介して第１電極パッド１Ｂに電気的に接続される。 Around the outer periphery of the main surface of the semiconductor pellet 2, a plurality of external terminals 2A arranged along each side are arranged. In addition, a plurality of external terminals 2 </ b> A arranged along the long side or the short side are arranged at the center of the main surface of the semiconductor pellet 2. Each of the plurality of external terminals 2 </ b> A is electrically connected to each of the plurality of second electrode pads 1 </ b> A disposed on the back surface of the base substrate 1 through bonding wires 6 through slits 5 formed in the base substrate 1. . Each of the plurality of second electrode pads 1A is electrically connected to each of the plurality of first electrode pads 1B disposed on the back surface of the base substrate 1 via wiring (1B 1 ). A bump electrode 4 is electrically and mechanically connected to the surface of each of the plurality of first electrode pads 1B. That is, the external terminal 2A of the semiconductor pellet 2, the bonding wires 6, the second electrode pads 1A, is electrically connected to the first electrode pad 1B through the respective wire 1B 1.

前記ベース基板１のスリット５は、半導体ペレット２の各辺毎に配置されると共に、半導体ペレット２の中央部の位置に配置される。つまり、本実施例のベース基板１は５本のスリット５を配置する。この５本のスリット５の夫々は半導体ペレット２の外部端子２Ａ上に配置される。   The slits 5 of the base substrate 1 are arranged for each side of the semiconductor pellet 2 and are arranged at the center of the semiconductor pellet 2. That is, the base substrate 1 of the present embodiment has five slits 5 disposed therein. Each of the five slits 5 is disposed on the external terminal 2 </ b> A of the semiconductor pellet 2.

このように、本実施例によれば、前述の実施例１と同様の作用効果が得られる。また、スリット５を半導体ペレット２の各辺毎及び半導体ペレット２の中央部の位置に配置することにより、半導体ペレット２の主面に配置される外部端子２Ａの数を増加することができると共に、ベース基板１の裏面に配置される第２電極パッド１Ａの数を増加することができるので、半導体ペレット２の外部端子２Ａとベース基板１の電極パッド１Ａとを電気的に接続する電源経路を増加することができ、出力信号の同時切り替え時に発生する電源ノイズを更に低減することができる。また、半導体ペレット２の外部端子２Ａとベース基板１の第２電極パッド１Ａとを電気的に接続する信号経路を増加することができ、外部端子２Ａの数で律則される半導体ペレット２の外形サイズを縮小することができる。   Thus, according to the present embodiment, the same operational effects as those of the first embodiment can be obtained. In addition, by arranging the slits 5 at each side of the semiconductor pellet 2 and at the position of the central portion of the semiconductor pellet 2, the number of external terminals 2A arranged on the main surface of the semiconductor pellet 2 can be increased, Since the number of second electrode pads 1A arranged on the back surface of the base substrate 1 can be increased, the number of power supply paths for electrically connecting the external terminals 2A of the semiconductor pellet 2 and the electrode pads 1A of the base substrate 1 is increased. Therefore, it is possible to further reduce the power supply noise generated when the output signals are switched simultaneously. In addition, the number of signal paths for electrically connecting the external terminals 2A of the semiconductor pellet 2 and the second electrode pads 1A of the base substrate 1 can be increased, and the outer shape of the semiconductor pellet 2 regulated by the number of external terminals 2A. The size can be reduced.

なお、本実施例は、半導体ペレット２の中央部の位置にスリット５を１本配置した構成で説明したが、半導体ペレット２の中央部の位置にスリット５を平行若しくは交差するように複数本配置し、スリット５の本数を増加することにより、ベース基板１の第２電極パッド１Ａの数及び半導体ペレット２の外部端子２Ａの数を更に増加することができる。   In addition, although the present Example demonstrated by the structure which arrange | positioned one slit 5 in the position of the center part of the semiconductor pellet 2, two or more slits 5 are arrange | positioned so that the position of the center part of the semiconductor pellet 2 may be parallel or cross | intersected. Then, by increasing the number of slits 5, the number of second electrode pads 1A of the base substrate 1 and the number of external terminals 2A of the semiconductor pellet 2 can be further increased.

（実施例４）
本発明の実施例４であるＢＧＡ構造を採用する半導体装置の概略構成を図１５（裏面側の樹脂封止体を除去した状態を示す裏面側の要部平面図）に示す。 Example 4
A schematic configuration of a semiconductor device adopting the BGA structure which is Embodiment 4 of the present invention is shown in FIG. 15 (plan view of the main part on the back side showing a state where the resin sealing body on the back side is removed).

図１５に示すように、半導体装置は、ベース基板１の主面のペレット搭載領域上に絶縁層（３）を介在して半導体ペレット２をフェースダウン方式で搭載し、ベース基板１の裏面側に複数のバンプ電極４を格子状に配置する。ベース基板１は例えば３層配線構造のプリント配線基板で構成される。   As shown in FIG. 15, the semiconductor device has the semiconductor pellet 2 mounted in a face-down manner on the pellet mounting region on the main surface of the base substrate 1 with an insulating layer (3) interposed therebetween. A plurality of bump electrodes 4 are arranged in a grid pattern. The base substrate 1 is composed of a printed wiring board having a three-layer wiring structure, for example.

前記半導体ペレット２の主面の外周囲には、その各辺に沿って配列された複数の外部端子２Ａが配置される。この複数の外部端子２Ａの夫々は、ベース基板１の裏面に配置された複数の第２電極パッド１Ａの夫々に、ベース基板１に形成されたスリット５を通してボンディングワイヤ６で電気的に接続される。   Around the outer periphery of the main surface of the semiconductor pellet 2, a plurality of external terminals 2A arranged along each side are arranged. Each of the plurality of external terminals 2 </ b> A is electrically connected to each of the plurality of second electrode pads 1 </ b> A disposed on the back surface of the base substrate 1 through bonding wires 6 through slits 5 formed in the base substrate 1. .

前記複数の第２電極パッド１Ａのうち、電極パッド１Ａ２は電極プレート８Ａと一体に形成される。この電極プレート８Ａはスルーホール配線（図示せず）及びベース基板１の内部配線（図示せず）を介して他の電極プレード８Ａに電気的に接続される。電極プレート８Ａには電源として例えば基準電位（例えば０［Ｖ］）が印加される。前記複数の第２電極パッド１Ａのうち、電極パッド１Ａ３は電極プレート８Ｂと一体に形成される。この電極プレート８Ａには、電源として例えば動作電位（例えば３．３［Ｖ］）が印加される。 Among the plurality of second electrode pads 1A, the electrode pads 1A 2 is formed integrally with the electrode plate 8A. The electrode plate 8A is electrically connected to another electrode plate 8A via a through-hole wiring (not shown) and an internal wiring (not shown) of the base substrate 1. For example, a reference potential (for example, 0 [V]) is applied to the electrode plate 8A as a power source. Among the plurality of second electrode pads 1A, the electrode pads 1A 3 is formed integrally with the electrode plate 8B. For example, an operating potential (for example, 3.3 [V]) is applied to the electrode plate 8A as a power source.

このように、本実施例によれば、ベース基板１の主面に配置された第２電極パッド（１Ａ）とその裏面に配置された第１電極パッド１Ｂとを電気的に接続するスルーホール配線（１Ｃ）の廃止によって電極プレート８Ａ、電極プレート８Ｂの夫々をベース基板１の裏面側に配置することができるので、バンプ電極４の配置を自由に設定でき、半導体ペレット２の外部端子２Ａとバンプ電極４との距離を短くすることができる。この結果、インダクタンスを低減することができるので、半導体装置の動作速度の高速化を図ることができる。   Thus, according to the present embodiment, the through-hole wiring for electrically connecting the second electrode pad (1A) disposed on the main surface of the base substrate 1 and the first electrode pad 1B disposed on the back surface thereof. By eliminating (1C), each of the electrode plate 8A and the electrode plate 8B can be arranged on the back side of the base substrate 1, so that the arrangement of the bump electrodes 4 can be freely set, and the external terminals 2A and bumps of the semiconductor pellet 2 can be set. The distance from the electrode 4 can be shortened. As a result, the inductance can be reduced, so that the operation speed of the semiconductor device can be increased.

以上、本発明者によってなされた発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

本発明の実施例１であるＢＧＡ構造を採用する半導体装置の主面側の平面図。1 is a plan view of a main surface side of a semiconductor device that employs a BGA structure that is Embodiment 1 of the present invention. 図１に示すＡ−Ａ線の位置で切った断面図。Sectional drawing cut in the position of the AA line shown in FIG. 図２の要部拡大断面図。The principal part expanded sectional view of FIG. 前記半導体装置の裏面側の樹脂封止体を除去した状態を示す裏面側の要部拡大平面図。The principal part enlarged plan view of the back surface side which shows the state which removed the resin sealing body of the back surface side of the said semiconductor device. 前記半導体装置の樹脂封止体を形成する成形金型の要部断面図。The principal part sectional drawing of the shaping die which forms the resin sealing body of the said semiconductor device. 前記半導体装置の製造方法を説明するための断面図。Sectional drawing for demonstrating the manufacturing method of the said semiconductor device. 前記半導体装置の製造方法を説明するための要部断面図。FIG. 6 is an essential part cross-sectional view for explaining the method for manufacturing the semiconductor device. 前記半導体装置の製造方法を説明するための要部断面図。FIG. 6 is an essential part cross-sectional view for explaining the method for manufacturing the semiconductor device. 前記半導体装置の製造方法を説明するための要部断面図。FIG. 6 is an essential part cross-sectional view for explaining the method for manufacturing the semiconductor device. 前記半導体装置を実装基板に実装した状態を示す要部断面図。FIG. 3 is a main part cross-sectional view showing a state where the semiconductor device is mounted on a mounting substrate. 前記半導体装置の変形例を示す断面図。Sectional drawing which shows the modification of the said semiconductor device. 本発明の実施例２であるＢＧＡ構造を採用する半導体装置の断面図。Sectional drawing of the semiconductor device which employ | adopts the BGA structure which is Example 2 of this invention. 前記半導体装置の裏面側の樹脂封止体を除去した状態を示す裏面側の要部拡大平面図。The principal part enlarged plan view of the back surface side which shows the state which removed the resin sealing body of the back surface side of the said semiconductor device. 本発明の実施例３であるＢＧＡ構造を採用する半導体装置の裏面側の樹脂封止体を除去した状態を示す裏面側の要部平面図。The principal part top view on the back surface side which shows the state which removed the resin sealing body by the side of the back surface of the semiconductor device which employ | adopts the BGA structure which is Example 3 of this invention. 本発明の実施例４であるＢＧＡ構造を採用する半導体装置の裏面側の樹脂封止体を除去した状態を示す裏面側の要部平面図。The principal part top view on the back surface side which shows the state which removed the resin sealing body by the side of the back surface of the semiconductor device which employ | adopts the BGA structure which is Example 4 of this invention. 従来のＢＧＡ構造を採用する半導体装置の要部断面図。Sectional drawing of the principal part of the semiconductor device which employ | adopts the conventional BGA structure.

符号の説明Explanation of symbols

１：ベース基板
１Ａ：電極パッド
１Ｂ：電極パッド
２：半導体ペレット
２Ａ：外部端子
３：絶縁層
４：バンプ電極
５：スリット
６：ボンディングワイヤ
７：樹脂封止体
７Ａ：樹脂
８Ａ，８Ｂ：電極プレート
１０：成形金型
１０Ａ：上型
１０Ｂ：下型
１１：キャビティ
１１Ａ，１１Ｂ，１２：凹部
１３：流入ゲート
１４：ヒートステージ
１４Ａ：凹部
１５：実装基板
１５Ａ：電極パッド
1: Base substrate 1A: Electrode pad 1B: Electrode pad 2: Semiconductor pellet 2A: External terminal 3: Insulating layer 4: Bump electrode 5: Slit 6: Bonding wire 7: Resin sealing body 7A: Resin 8A, 8B: Electrode plate 10: Molding die 10A: Upper mold 10B: Lower mold 11: Cavity 11A, 11B, 12: Recess 13: Inflow gate 14: Heat stage 14A: Recess 15: Mounting substrate 15A: Electrode pad

Claims (8)

第１主面及び前記第１主面とは反対側の第２主面と、前記第１主面から前記第２主面に貫通するスリットとを有し、前記第２主面上に複数の電極パッドを有し、リジット基板で構成されるベース基板と、
主面に回路システムと複数の外部端子を有する半導体ペレットであって、前記半導体ペレットの前記主面が前記ベース基板の前記第１主面に向かい合い、かつ、前記複数の外部端子が前記スリットの内側に平面的に位置し、かつ、前記スリットの一部の領域が前記半導体ペレットの外側に平面的に位置するように前記ベース基板上に搭載された半導体ペレットと、
前記半導体ペレットの前記複数の外部端子と前記ベース基板の前記複数の電極パッドとを各々電気的に接続する複数のボンディングワイヤと、
前記ベース基板の前記第１主面及び前記第２主面の両側に形成され、前記スリットを介して互いに連続した樹脂封止体であって、前記複数のボンディングワイヤを封止する樹脂封止体と、
前記ベース基板の前記第２主面上に形成され、前記複数の電極パッドと各々電気的に接続された複数のバンプ電極と、
を備えたことを特徴とする半導体装置。 A second main surface opposite to the first main surface and the first major surface, and a slit penetrating in the second major surface of said first main surface, a plurality on the second main surface have a electrode pad, and the base substrate composed of rigid substrates,
A semiconductor pellet having a circuit system and a plurality of external terminals on a main surface, wherein the main surface of the semiconductor pellet faces the first main surface of the base substrate, and the plurality of external terminals are inside the slit. And a semiconductor pellet mounted on the base substrate such that a partial region of the slit is planarly positioned outside the semiconductor pellet,
A plurality of bonding wires respectively electrically connecting the plurality of electrode pads of the base substrate and the plurality of external terminals of the semiconductor pellet,
A resin sealing body which is formed on both sides of the first main surface and the second main surface of the base substrate and is continuous with each other through the slit, and seals the plurality of bonding wires. When,
A plurality of bump electrodes formed on the second main surface of the base substrate and electrically connected to the plurality of electrode pads;
A semiconductor device comprising: 請求項１において、前記ベース基板の前記第１主面側に形成された前記樹脂封止体の一部は、前記半導体ペレット及び前記ベース基板の前記第１主面に接触し、前記ベース基板の前記第２主面側に形成された前記樹脂封止体の一部は、前記複数の電極パッドが形成された領域の前記第２主面に接触していることを特徴とする半導体装置。 In claim 1, a portion of the resin sealing body formed on the first main surface side of said base substrate is in contact with the semiconductor pellet and the first major surface of said base substrate, said base substrate A part of the resin sealing body formed on the second main surface side is in contact with the second main surface in a region where the plurality of electrode pads are formed. 請求項２において、前記半導体ペレットの前記主面に対向する裏面は、前記ベース基板の前記第１主面側に形成された前記樹脂封止体から露出していることを特徴とする半導体装置。 The semiconductor device according to claim 2 , wherein a back surface of the semiconductor pellet that faces the main surface is exposed from the resin sealing body that is formed on the first main surface side of the base substrate. 請求項１において、前記複数のボンディングワイヤは、金ワイヤであり、前記半導体ペレットの前記複数の外部端子と前記ベース基板の前記複数の電極パッドとの接続は、超音波・熱圧着ボンディングにより行われることを特徴とする半導体装置。 2. The bonding wires according to claim 1 , wherein the plurality of bonding wires are gold wires, and the connection between the plurality of external terminals of the semiconductor pellet and the plurality of electrode pads of the base substrate is performed by ultrasonic / thermocompression bonding. A semiconductor device. 請求項１において、前記樹脂封止体は、添加物としてフィラーを含む樹脂から形成されることを特徴とする半導体装置。 The semiconductor device according to claim 1 , wherein the resin sealing body is formed of a resin containing a filler as an additive. 請求項１において、前記複数のバンプ電極の各々の高さは、前記ベース基板の厚さ方向における前記第２主面側に形成された前記樹脂封止体の部分の厚さより大きく形成されていることを特徴とする半導体装置。 According to claim 1, each of the heights of the plurality of bump electrodes are formed larger than the thickness of the portion of the resin sealing body formed on the second main surface side in the thickness direction of the base substrate A semiconductor device. 請求項６において、前記複数のバンプ電極の各々は、Ｐｂ−Ｓｎ系の合金材で形成されることを特徴とする半導体装置。 7. The semiconductor device according to claim 6 , wherein each of the plurality of bump electrodes is formed of a Pb—Sn alloy material. 請求項６において、前記複数のバンプ電極の各々は、実装基板に電気的及び機械的に接続するために形成されていることを特徴とする半導体装置。 7. The semiconductor device according to claim 6 , wherein each of the plurality of bump electrodes is formed to be electrically and mechanically connected to a mounting substrate.
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