JPH05346454A - Lsi tester - Google Patents

Abstract

PURPOSE:To obtain a low price LSI tester compatible with high pin count circuit to be measured. CONSTITUTION:Parallel pulse output from a circuit 8 to be measured is inputted through a test board 7 to a shift register 2 in an LSI tester 1. The parallel pulse output is converted through the shift register 2 into a serial pulse train which is fed to a comparator 4 and compared sequentially with a high potential side voltage reference VOH and a low potential side voltage reference VOL. Output from the comparator 4 is fed to a comparator control section 3. On the other hand, expected values corresponding with defined levels of parallel pulse train outputted from the circuit 8 to be measured are previously set for respective pulses in an expected value setting circuit 5, which delivers serial pulse train having appropriate level to the comparator control section 3 at the timing of the comparator 4 delivering serial pulse train from the circuit 8 to be measured to the comparator control section 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI test apparatus.

[0002]

2. Description of the Related Art In a conventional LSI test apparatus, as shown in FIG. 3, a parallel output pulse of a circuit under test 6 is input to the LSI test apparatus 1 through a test board 7, and each pin of the circuit under test is tested. The same number of waveform level comparators 4-1, 4-2, 4-3 and 4-4 are input.
In these comparators 4-1, 4-2, 4-3, and 4-4, output levels are compared through comparison with V _OH and V _OL , respectively, and the comparison result is input to the comparator control unit 3. To be done. In the comparator control unit 3, the comparison result is compared and collated with the pattern level output from the expected pattern 5 to determine the quality of the parallel output pulse of the circuit under measurement. For example, if the parallel output pulse output from the circuit under test 6 is a 4-bit output and the normal operation is defined as pins 1 to 4 (1, 0, 1, 1), the expected pattern 5 The expected pattern designated by is also (1, 0, 1, 1).

[0003]

DISCLOSURE OF THE INVENTION The conventional LSI described above
In the test equipment, as the circuit under test becomes multifunctional,
The number of output pins tends to increase, and for a circuit under test with a large number of pins, the number of circuit components increases as a corresponding LSI test device, resulting in higher cost and higher cost. There is a drawback that it becomes a simple device.

[0004]

An LSI test apparatus of the present invention targets a parallel pulse train output from an LSI to be measured as a test target and compares the level of each pulse of the parallel pulse train with a predetermined expected value level. Thus, in the LSI test apparatus for judging the quality of the parallel pulse train, a parallel / serial conversion circuit for inputting the parallel pulse train output from the LSI to be measured, converting the parallel pulse train into a serial pulse train, and outputting the serial pulse train is added. By doing so, the quality of the parallel pulse train is determined by comparing the level of each pulse of the serial pulse train with a predetermined expected value level with the serial pulse train output from the parallel / serial conversion circuit as a test target. It is characterized by doing.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, the LSI of this embodiment
The test apparatus 1 corresponds to the circuit under test 8 and the test board 7, and has a parallel input / serial output shift register 2, a comparator control unit 3, a comparator 4, and an expected value setting circuit 5.
And a relay 6.

In FIG. 1, the parallel pulse output from the circuit under test 8 is input to the LSI test apparatus 1 via the test board 7 and first to the shift register 2. The shift register 2 is a shift register that outputs a parallel input as a serial output as described above, and the parallel pulse output output from the circuit under test 8 is converted into a serial pulse train in the shift register 2 and the relay 6 Is input to the comparator 4 via. In the comparator 4, the serial pulse train is sequentially compared with the reference voltage V _OH on the high potential side and the reference voltage V _OL on the low potential side, and the output thereof is input to the comparator control unit 3.

On the other hand, in the expected value setting circuit 5, an expected value corresponding to the specified level of the parallel pulse train output from the measured circuit 8 is set in advance for each pulse, and the comparator 4 measures the measured value. Corresponding to the timing when the serial pulse train from the circuit 8 is input to the comparator control unit 3, the expected value setting circuit 5 outputs a corresponding appropriate level serial pulse train and inputs the serial pulse train to the comparator control unit 3.
In the comparator control unit 3, each level of the pulse train to be measured input from the comparator 4 and the pulse train of the expected value level input from the expected value setting circuit 5 is compared and collated to determine whether the measured pulse train is good or bad. (P / F) is determined. The role of the relay 6 is to distinguish the line of the serial pulse train output from the shift register 2 from the line in the normal operation.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 2, the LSI of this embodiment
The test apparatus 1 corresponds to a circuit under test 8, a test board 7, and a power supply adapter 9 including a parallel input / serial output shift register 2, and a comparator control unit 3 and a comparator 4 are provided.
And an expected value setting circuit 5.

In FIG. 2, the parallel pulse output output from the circuit under test 8 is input to the shift register 2 included in the pin conversion adapter 9. The parallel pulse output from the circuit under test 8 is converted into a serial pulse train in the shift register 2 and input into the comparator 4 via the test board 7. In the comparator 4, the serial pulse train is sequentially compared with the reference voltage V _OH on the high potential side and the reference voltage V _OL on the low potential side, and the output thereof is input to the comparator control unit 3.

On the other hand, in the expected value setting circuit 5, an expected value corresponding to the specified level of the parallel pulse train output from the measured circuit 8 is set in advance for each pulse, and the comparator 4 measures the measured value. Corresponding to the timing when the serial pulse train from the circuit 8 is input to the comparator control unit 3, the expected value setting circuit 5 outputs a corresponding appropriate level serial pulse train and inputs the serial pulse train to the comparator control unit 3.
In the comparator control unit 3, each level of the pulse train to be measured input from the comparator 4 and the pulse train of the expected value level input from the expected value setting circuit 5 is compared and collated to determine whether the measured pulse train is good or bad. (P / F) is determined.

The second embodiment is different from the first embodiment in that the pin conversion adapter 9 is provided between the circuit under test 8 and the test board 7, but it is functionally different from the first embodiment. Is exactly the same in.

[0014]

As described above, according to the present invention, the parallel pulse output of the circuit under test of the circuit under test is converted into the series pulse train to perform the level determination, thereby irrespective of the number of pins of the circuit under test. LS that can be configured as a test device that supports a small number of pins, reduces cost, and is low cost
There is an effect that an I test device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 LSI test device 2 Shift register 3 Comparator control unit 4, 4-1 to 4-4 Comparator 5 Expected value setting circuit 6 Relay 7 Test board 8 Tested circuit 9 Pin conversion adapter

Claims (1)

[Claims] 1. An LSI for determining the quality of a parallel pulse train by comparing a level of each pulse of the parallel pulse train with a predetermined expected value level with a parallel pulse train output from the LSI to be measured as a test target. In the test apparatus, by inputting the parallel pulse train output from the LSI to be measured, converting the parallel pulse train into a serial pulse train, and outputting the parallel pulse train, the parallel / serial converter circuit outputs the parallel pulse train. An LSI test apparatus, wherein a quality of the parallel pulse train is determined by comparing a level of each pulse of the serial pulse train with a predetermined expected value level with the serial pulse train being tested as a test target.