JP2998390B2 - IC inspection equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ASIC (Applicatio
n Inspection equipment used for the inspection of Specific Integrated Circuits, etc.
The present invention relates to an apparatus capable of inspecting the use state of an IC.

[0002]

2. Description of the Related Art A conventional IC inspection apparatus is as follows. An IC to be inspected is set in the apparatus, and a test pattern is given to the IC. IC from this test pattern
Is compared with the expected value pattern expected for the output pattern of FIG. 7 and the output pattern actually obtained when the test pattern is input to the IC. The quality of the IC is determined based on the comparison result. Since such an apparatus is used for inspection of a general-purpose IC, the inspection is performed on the assumption that the load conditions of the pins of all the ICs are the same.

[0003] Such an apparatus has the following problems. When an IC is mounted on an actual printed board, the load varies depending on the use conditions. ASI requiring high speed
When an IC such as C is actually mounted on a printed circuit board, the characteristics of the CMOS device greatly change depending on the load condition, so that the output pattern causes an operation different from that at the time of inspection, and the device as a whole malfunctions. I will.
This is a very serious problem when it comes to ASICs. This is because the ASIC occupies the core part of the product and the glow logic part, and is therefore a critical path of the system.

[0004] As a countermeasure, the system designer must use A
Simulation of ASIC operation during SIC design,
By using complex techniques, margins for actual load conditions were verified. In this verification, since the verification was not performed on an actual device, the only option was to design with a very large margin to kill the function and speed of the ASIC, or to design with ease and experience. By doing so, a malfunction does not occur when the ASIC is mounted on a product.

As a method of solving this problem, it is conceivable to carry out an inspection by matching the load condition in the mounted state with impedance matching. Therefore, the load condition and the pin arrangement of the pins are different for each ASIC, and a dedicated IC inspection device is required. However, compared to a memory or a general-purpose IC, the production amount is extremely small. For this reason, it is costly and not economical to produce a dedicated device.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an IC inspection apparatus which improves the accuracy and efficiency of an inspection by giving actual IC use conditions to the IC.

[0007]

According to the present invention, a test pattern is provided to an IC to be inspected, and an expected value pattern expected from an output pattern of the IC to be inspected from the test pattern and an output pattern actually obtained are obtained. In comparison, in the IC inspection apparatus for determining the quality of the IC to be inspected,
And a load application section connected to the output side of C and for setting a load condition to the IC under test simulating the actual use state. Further, a control unit for setting a load condition to be applied to the load applying unit based on a load condition connected to a pin of the IC to be measured, such as a wiring capacitance and a terminal capacitance, is provided. The load applying unit may include a plurality of resistors having different resistance values, a first selection unit that selects the resistors, a plurality of capacitors having different capacitances, a second selection unit that selects the capacitors, Inductors having different inductances and third selecting means for selecting the inductors.

[0008]

According to the present invention, by providing the load applying section for applying a load to the output pin of the IC and the control section for setting the load condition of the load applying section, the accuracy and efficiency of the inspection are improved. This makes it possible to realize an IC inspection apparatus that has been operated.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a configuration diagram showing one embodiment of the present invention. In the figure,
A CPU 1 controls the entire system, and is connected to a bus connected to another device (for example, a printer or a memory device). 2 is a timing generator for generating a timing signal, and 3 is a pattern generator for generating a test pattern. These are controlled by a signal from the CPU 1. 4 is a format controller for receiving a timing signal from the timing generator 2 and shaping the pattern waveform from the pattern generator 3, 5 is a driver connected to the format controller 4, and RL 1 is a driver relay connected to the driver 5 , 6 are input voltage generators for determining the output voltage level of the driver 5 under the control of the CPU 1. Reference numeral 7 denotes an IC to be measured (hereinafter abbreviated as DUT) connected to the driver relay RL1.
vice Under Test). RL2 is a comparator relay connected to the output side of the DUT 7, and RL3 is a DC relay connected to the DUT 7, and is connected to a DC test bus. Reference numeral 8 denotes a load applying unit that is connected to the comparator relay RL2 and sets such load conditions in actual use conditions. 9 is a comparator connected to the load applying unit 8, 10 is an output comparison voltage generator that is connected to the CPU 1 and the comparator 9 and supplies a voltage for comparison by the comparator 9, and 11 is a timing generator 2 The pattern comparator receives the strobe signal from the comparator 9 and compares the output pattern from the comparator 9 with the expected value pattern from the pattern generator 3. Reference numeral 12 denotes a test data buffer which is connected to the CPU 1 and stores the comparison result of the pattern comparator 11. It is to be noted that a device used to identify a voltage level using two comparators of a high level and a low level, determine whether the voltage level is “high”, “low” or “intermediate level”, and use the same for comparison with an expected value pattern is generally used. It is a target.

In the CPU 1, reference numeral 101 denotes a control unit for setting a load condition of the load applying unit 8. For example, a wiring connected to an output pin of the DUT 7 obtained by a circuit design CAD or a printed board design CAD capable of performing board simulation. Set load conditions such as capacitance and terminal capacitance.

FIG. 2 is a diagram showing a specific configuration example of the load applying unit of the apparatus shown in FIG. In the figure, the resistance value R _n is respectively different from R _1, a capacitor of value C _m is respectively different from C _1, from L ₁ L _i an inductor respectively different values. 81 is a selecting means as a first selecting means for selecting a resistor, 82 is a selecting means as a second selecting means for selecting a capacitor, and 83 is a third means for selecting an inductor.
Selection means. These selecting means receive a load selection set value from the control unit 101 and make a selection. The following settings can be arbitrarily set by each selection means. (A) Setting only the load capacitance (b) Setting the actual substrate impedance of the DUT and the resistive load (c) Setting the load circuit conditions of the distributed constant approximated by the lumped constant

The operation of such a device will be described below.
FIG. 3 is an explanatory diagram of the operation of the apparatus of FIG. (I) is a no-load waveform when no load is applied, (ii) is a waveform when a load capacitance is applied by a capacitor, and (iii) is a load applying unit 8.
(Iv) is a waveform when the inductor component is set, and (iv) is a waveform when the load applying unit 8 performs impedance matching. The test pattern is output from the pattern generator 3, and the test pattern is input to the DUT 7. And
According to the setting of the control unit 101, the load applying unit 8 sets the load. By doing so, the output pattern of the DUT 7 output from the load applying unit 8 is output as a waveform from (i) to (iv) according to the set load condition, for example. Then, the output waveform is compared by the comparator 9 with a voltage of a high level or a low level, and a logical determination of “1” or “0” is performed. When the comparison is performed by the pattern comparator 11, the enable signal from the timing generator 2 is received, and the comparison is performed with the expected value pattern.

At this time, comparing the output patterns for each load, the waveforms (iii) and (iii) are compared with the waveforms (i) and (ii).
The waveform of (iv) has a delay. In the actual implementation state, (ii
Waveforms such as i) and (iv) are output. As a result, there is a difference in logical judgment between the output waveform when no load is applied and the output waveform when a load is applied. The fact that there is a difference in the logical judgment means that even if the test under no load is normal, the device as a whole will malfunction when mounted. In order to prevent such a malfunction, a mounting state is created by the load applying unit, and a function evaluation test according to the actual situation is performed.

In the present invention, the case where the control unit is provided in the CPU is shown. However, the present invention is not limited to this, and the control unit may be provided outside the CPU. In the load applying unit, the example of the arrangement of the resistor, the inductor, and the capacitor as in the embodiment has been described. However, the present invention is not limited to this, and it is sufficient that a pseudo load condition can be set based on these three relationships.

[0015]

According to the present invention, the following effects can be obtained. By providing the load applying unit, a load can be set for each pin of the DUT, so that a test can be performed according to an actual use state, and the accuracy of IC inspection is improved. In addition, since the accuracy is improved, the efficiency is improved. Since the ASIC can be quasi-packaged, it is not necessary to design a large margin to prevent malfunction.
There is an effect that the performance of can be sufficiently brought out.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating a specific configuration example of a load applying unit of the apparatus in FIG. 1;

FIG. 3 is an operation explanatory diagram of the device of FIG. 1;

[Explanation of symbols]

7 DUT 8 load applying section 81 to 83 selection means 101 control unit R ₁ to R _n resistance C ₁ -C _m capacitor L ₁ ~L _i inductor

Claims (3)

(57) [Claims] A test pattern is provided to an IC to be inspected, and an expected value pattern expected from an output pattern of the IC to be inspected based on the test pattern is compared with an actually obtained output pattern. An IC inspection device for judging pass / fail, comprising: a load application unit connected to an output side of the IC to be inspected and simulatedly setting a load condition on the IC to be inspected assuming an actual use state. An IC inspection device characterized by the above-mentioned. 2. A control unit for setting a load condition to be applied to a load applying unit based on a load condition connected to a pin of an IC to be measured, such as a wiring capacitance and a terminal capacitance, is provided. IC inspection equipment. 3. A load applying unit comprising: a plurality of resistors having different resistance values; first selecting means for selecting the resistors; a plurality of capacitors having different capacitances; and a second selecting means for selecting the capacitors. 2. The IC inspection apparatus according to claim 1, comprising: a plurality of inductors having different inductances; and third selecting means for selecting said inductors.