JPH05326719A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To provide a semiconductor element manufacturing method to form a multilayer wiring corresponding to the line using a process-integrated multichamber device for removal of the reaction product which is generated between the gas discharged from an interlayer insulating film and a resist component and etching gas or Al alloy wiring. CONSTITUTION:After an interlayer insulating film has been deposited in the first CVD chamber of the first multichannel device, an Si nitride film 15 is formed in the second CVD chamber of the device without exposing the wafer the outside air. Then, the above-mentioned material is moved to a sputtering chamber in a vacuum atmosphere, and a metal film 16, to be used for a mask, is formed by sputtering. Subsequently, a through hole is made in this metal film. Further, after a through hole has been formed in the Si nitride film 15 and the interlayer insulating film 14 in the etching chamber of the second multichamber device, they are moved to the sputtering chamber of the second chamber device, a sputter-cleaning operation is conducted. Then, they are moved to the sputtering chamber of the second multichamber device, and an upper layer wiring film 18 is formed by sputtering.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a multilayer wiring forming process in VLSI manufacturing.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. FIG. 4 is a cross-sectional view of such a conventional semiconductor element two-layer wiring forming process. Hereinafter, the process will be described step by step.

(1) First, as shown in FIG. 4A, an intermediate insulating film (BPSG) 2 is formed on a silicon substrate 1, and a first wiring layer (Al-1%) is formed on the intermediate insulating film 2. Si
-0.5% Cu) 3 is patterned. (2) Next, as shown in FIG. 4 (b), O ₃ -TEOS
(Ozone-tetra-ethyl-ortho-silicate) -S
A CVD interlayer insulating film 4 having a good covering property such as an iO ₂ film is deposited.

(3) Next, as shown in FIG. 4C, a resist 5 is applied, and a through hole portion is opened in a photolithography process. (4) Next, as shown in FIG. 4D, the through holes 6 are etched by RIE (reactive ion etching) or ECR (electron cyclotron resonance). The shape of the through hole is tapered so as to improve the coverage of the second layer Al alloy.

(5) Next, as shown in FIG. 4E, the resist 5 is removed after the patterning is completed. (6) Finally, clean the surface of the dirty first layer Al alloy wiring with A
After cleaning by r ⁺ reverse sputtering, as shown in FIG. 4 (f), the second layer Al alloy material (Al-1% Si-0.5% C
u) Deposit 7.

The above process is the simplest case,
Layer Al alloy wiring with AlSiCu / TiN or Ti
Even when a laminated structure such as / TiN / AlSiCu / TiN is formed or a through-hole shape is made into a wine glass shape by making full use of wet / dry etching, the prototype is generally produced by the process flow of FIG. Also, C
The VD interlayer insulating film deposition, etching, and sputtered Al alloy vapor deposition are processed by separate and independent devices, and the wafer is exposed to the atmosphere during transfer between the devices.

[0007]

However, in the above-mentioned conventional manufacturing method, the O ₃ -TEOS.
The SiO ₂ film absorbs a large amount of water and H ₂ while being left in the air, and these are released during the film formation of the second layer Al alloy to deteriorate the film quality of the Al alloy film. In addition, a reaction product of the resist component and the etching gas or Al is formed in the etching process, and remains as a residue after removing the resist, which lowers the yield of wiring.

Furthermore, after through-hole etching, the surface of the first-layer Al alloy wiring is exposed to oxygen plasma, a stripping agent, and the atmosphere and becomes dirty, which makes it difficult to remove it by reverse sputter cleaning, and throughput decreases. I will end up. The present invention provides a gas released from the above-described interlayer insulating film,
It is possible to form excellent multi-layered wiring corresponding to the line using the multi-chamber device with integrated process to remove the reaction product of resist component and etching gas or Al and the contamination of the lower layer Al alloy wiring. It is an object of the present invention to provide a method of manufacturing a semiconductor element.

[0009]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, in which after forming a lower layer wiring, an upper layer wiring is formed. A step of depositing an interlayer insulating film in a CVD chamber, a step of forming a silicon nitride film in a second CVD chamber of the first multi-chamber apparatus without exposing it to the outside air, and a subsequent step of exposing it to the outside air. A step of moving to a sputter deposition chamber and forming a mask metal film by sputter deposition in the sputter deposition chamber,
Forming a through hole in the mask metal film,
A step of forming through holes in the silicon nitride film and the interlayer insulating film in the etching chamber of the second multi-chamber apparatus, and thereafter, without exposing to the outside air, transfer to the sputter chamber of the second multi-chamber apparatus to carry out the sputtering. A step of performing sputter cleaning in the chamber and a step of thereafter moving to a sputter deposition chamber of the second multi-chamber apparatus without exposing to the outside air and forming an upper wiring film by sputter deposition in the sputter deposition chamber It was done like this.

[0010]

According to the present invention, as described above, the CVD process and the sputter deposition process are performed in the first multi-chamber apparatus, and the etching process and the sputter deposition process are performed in the second multi-chamber apparatus. That is, the interlayer insulating film is deposited in the first CVD chamber of the first multi-chamber apparatus, then the silicon nitride film is formed in the second CVD chamber without being exposed to the outside air, and thereafter, without being exposed to the outside air. , The first multi-chamber apparatus is moved to a sputter deposition chamber, and a metal film for a mask is formed by sputter deposition in the sputter deposition chamber.

Further, in the etching chamber of the second multi-chamber apparatus, through holes are formed in the insulating film, and thereafter, the through hole is transferred to the sputtering chamber of the second multi-chamber apparatus without exposing to the outside air, and the sputtering chamber and the sputtering chamber are removed. Then, sputter cleaning is performed, and thereafter, the substrate is transferred to a sputter deposition chamber of the second multi-chamber apparatus without being exposed to the outside air, and an upper wiring film is formed by sputter deposition in the sputter deposition chamber.

Therefore, the hygroscopicity of the interlayer insulating film can be suppressed. Further, since the interlayer insulating film is covered with the silicon nitride film continuously formed by the multi-chamber device, it is possible to prevent the interlayer insulating film from absorbing and releasing gas.

[0013]

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 and 2 are cross-sectional views of a process for forming a two-layer wiring of a semiconductor device showing an embodiment of the present invention, and FIG. 3 is a view showing a multi-chamber device used in the present invention. (1) First, as shown in FIG. 1A, a silicon substrate 1
1, an intermediate insulating (BPSG) film 12 is formed, an Al alloy wiring 13 of a first layer is formed on the intermediate insulating film 12, and an interlayer insulating (O ₃ -TEOS • SiO ₂ ) film 14 is further formed. To do.

(2) Next, as shown in FIG. 1B, a SiNx film 15 is formed on the interlayer insulating film 14. (3) Next, as shown in FIG. 1C, an Al alloy or TiN film 16 as a mask metal film is formed on the SiNx film 15. Here, in the steps of FIGS. 1A to 1C described above, continuous processing is performed by the multi-chamber apparatus shown in FIG. That is, in the CVD chamber 21, the interlayer insulating film 14
As an O ₃ -TEOS / SiO ₂ film (about 10,000
Å) After being deposited, it is transferred to the CVD chamber 22 through the intermediate chamber 24 which is a high vacuum chamber without exposing to the outside air, and the CVD is performed.
In the chamber 22, after depositing the SiNx film 15 (about 300 Å), the SiNx film 15 is transferred to the sputter deposition chamber 23 through the intermediate chamber 24 which is a high vacuum chamber without being exposed to the outside air again. A TiN film 16 (about 500Å) is formed. In addition, in FIG.
Is a load lock room.

(4) Next, as shown in FIG. 1D, a resist 17 is applied. (5) Next, as shown in FIG. 1E, a resist pattern is formed by a photolithography process. (6) Next, as shown in FIG. 1F, a through hole portion is opened in the Al alloy or TiN film 16.

Here, in the step of FIG. 1F, only the Al alloy or the TiN film 16 is opened by anisotropic etching with a chlorine-based gas. (7) Then, as shown in FIG.
[See FIG. 1 (f)] is removed with an O ₂ asher and a stripping agent. (8) Next, as shown in FIG. 2B, the SiNx film 15
And through holes are formed in the interlayer insulating (O ₃ -TEOS.SiO ₂ ) film 14.

(9) Finally, as shown in FIG. 2 (c),
A second layer of Al alloy wiring 18 is formed by sputter deposition. Here, the steps of FIGS. 2 (b) to 2 (c) described above are continuously performed by the multi-chamber apparatus shown in FIG. 3 (b). That is, in the etching chamber 31,
The SiNx film 15 and the interlayer insulating film 14 are anisotropically etched with a fluorine-based gas. At this time, a taper condition is desirable so that the coverage of the second-layer Al alloy wiring 18 is improved. After that, without exposing to the outside air, the intermediate chamber 34, which is a high vacuum chamber, is transferred to the Ar ⁺ reverse sputtering chamber 32,
In the Ar ⁺ reverse sputtering chamber 32, Ar ⁺ reverse sputtering cleaning (soft cleaning) is performed, and thereafter, without exposing to the outside air, the intermediate chamber 34, which is a high vacuum chamber, is moved to the sputtering deposition chamber 33, and the sputtering deposition chamber 33 is moved. Three
In 3, the second layer Al alloy is sputter-deposited. In FIG. 3B, reference numeral 35 is a load lock chamber.

Here, when an Al alloy is used as the mask metal, it is hardly etched by the fluorine-based gas used in the through-hole etching, so that it remains after etching and can be used as a part of the second-layer Al alloy wiring 18. .. On the other hand, when TiN is used, since etching is performed with a fluorine-based gas, the etching ends with either TiN, SiNx, or the interlayer insulating film depending on the film thickness and etching conditions.

In this case, especially TiN is left and the second layer Al
The structure laid under the alloy wiring can be used to strengthen the wiring. Further, as a matter of course, it is possible to form the second-layer Al alloy film without leaving both TiN and Al alloy.
Further, the metal for each mask is made of Al alloy / TiN, or T
It may be laminated such as an iN / Al alloy.

In the above embodiment, SiNx is used as the cap of the interlayer insulating film, but the masking metal also has the function, so it may be omitted. Further, in the embodiment, 1
Although the layer wiring structure is an Al alloy single layer, it may be a laminated structure of an Al alloy and a refractory metal. Also at this time,
If TiN or WN is used as the refractory metal on the wiring, the through-hole resistance can be improved by removing it by anisotropic etching of fluorine-based gas after etching the interlayer insulating film in the step of FIG. 2B. Can be reduced.

The Al alloy material used for the mask and the Al alloy material used for the wiring may be the same or different. In addition,
By leaving a TiN film, an Al alloy film, or a laminated structure film thereof as a mask metal film, the side wall of the through hole is an upper wiring film single layer, and on the interlayer insulating film, these mask metal film and upper wiring film. And a wiring structure having a laminated structure of

The material of the upper wiring film is pure A
1, Al alloy, Cu, W, Au, Ag, Ti, TiN,
TiW or a laminated structure film thereof can be used. Furthermore, the present invention can be applied to a multi-layer wiring formation process of two or more layers. It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0023]

As described above in detail, according to the present invention, (1) after the interlayer insulating film is deposited, the SiNx film is continuously deposited as a cap. Gas absorption and gas release from the interlayer film are eliminated, and an upper-layer wiring film having good film quality can be formed.

(2) Since the resist is removed after the masking metal film, for example, the Al alloy film or the TiN film is patterned, the amount of the compound containing the resist component is reduced, and the residue can be reduced. (3) Since the multi-chamber apparatus is used, the surface of the underlying wiring film is kept clean after the through hole etching, and a low resistance through hole contact can be easily obtained.

(4) By leaving the metal film for the mask, it becomes an underlay of the upper wiring film, which is useful for strengthening the wiring. Further, since the etching can be stopped by the SiNx film or the interlayer insulating film, a wiring film having different characteristics can be formed on these films.

[Brief description of drawings]

FIG. 1 is a sectional view (No. 1) of a step of forming a two-layer wiring of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) of the step of forming the two-layer wiring of the semiconductor element showing the embodiment of the present invention.

FIG. 3 is a diagram showing a multi-chamber device used in the present invention.

FIG. 4 is a cross-sectional view of a conventional two-layer wiring forming process of a semiconductor element.

[Explanation of symbols]

11 Silicon Substrate 12 Intermediate Insulating Film (BPSG) 13 First Layer Al Alloy Wiring 14 Interlayer Insulation (O ₃ -TEOS / SiO ₂ ) Film 15 SiNx Film 16 Al Alloy or TiN Film 17 Resist 18 Second Layer Al Alloy Wiring 21,22 CVD chamber 23,33 Sputter deposition chamber 24,34 Intermediate chamber 25,35 Load lock chamber 31 Etching chamber 32 Ar ⁺ reverse sputtering chamber

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, in which after forming a lower layer wiring, an upper layer wiring is formed, the method comprises: (a) depositing an interlayer insulating film in a first CVD chamber of a first multi-chamber apparatus; b) Then, without exposing to the open air,
Forming a silicon nitride film in the second CVD chamber of the first multi-chamber apparatus, and (c)
Transferring to a sputter deposition chamber without exposing to the outside air, forming a mask metal film by sputter deposition in the sputter deposition chamber, (d) forming a through hole in the mask metal film, and (e) A step of forming through holes in the silicon nitride film and the interlayer insulating film in the etching chamber of the second multi-chamber apparatus, and (f) after that, transfer to a sputtering chamber of the second multi-chamber apparatus without exposing to the outside air. A step of performing sputter cleaning in the sputter chamber, and (g) thereafter, moving to a sputter deposition chamber of the second multi-chamber apparatus without exposing to the outside air, and in the sputter deposition chamber, an upper wiring film is formed by sputter deposition. And a step of forming the semiconductor element. 2. The interlayer insulating film in the step (a) is O
_The method for manufacturing a semiconductor device according to claim 1, wherein the film is a _3- TEOS.SiO ₂ film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the masking metal film in the step (c) is an Al alloy film, a TiN film, or a laminated structure film thereof.