JP3189970B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3189970B2 JP3189970B2 JP25304998A JP25304998A JP3189970B2 JP 3189970 B2 JP3189970 B2 JP 3189970B2 JP 25304998 A JP25304998 A JP 25304998A JP 25304998 A JP25304998 A JP 25304998A JP 3189970 B2 JP3189970 B2 JP 3189970B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- interlayer insulating
- wiring
- insulating film
- etch stopper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 40
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 230000004888 barrier function Effects 0.000 claims description 31
- 239000011229 interlayer Substances 0.000 claims description 30
- 230000009977 dual effect Effects 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 19
- 239000010410 layer Substances 0.000 claims description 14
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 239000010949 copper Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- FYQJUJFQWJXEGS-UHFFFAOYSA-N C(C)[Ti]N Chemical compound C(C)[Ti]N FYQJUJFQWJXEGS-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VMQMZMRVKUZKQL-UHFFFAOYSA-N Cu+ Chemical compound [Cu+] VMQMZMRVKUZKQL-UHFFFAOYSA-N 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- DHXVGJBLRPWPCS-UHFFFAOYSA-N Tetrahydropyran Chemical compound C1CCOCC1 DHXVGJBLRPWPCS-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005108 dry cleaning Methods 0.000 description 1
- OJCDKHXKHLJDOT-UHFFFAOYSA-N fluoro hypofluorite;silicon Chemical compound [Si].FOF OJCDKHXKHLJDOT-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特にデュアルダマシン法により、多層配線を
形成する半導体装置の製造方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a multilayer wiring is formed by a dual damascene method.
【０００２】[0002]
【従来の技術】半導体集積回路の集積度の向上に伴い、
多層配線の形成が不可欠となっている。この多層配線を
形成する方法として、デュアルダマシン法が知られてい
る。この方法は、図１２に示すように、下層配線２０を
形成した後、下層配線２０と同一の材料で上層配線に接
続するヴィアプラグを形成する方法である。2. Description of the Related Art As the degree of integration of semiconductor integrated circuits increases,
The formation of multilayer wiring has become indispensable. As a method of forming this multilayer wiring, a dual damascene method is known. In this method, as shown in FIG. 12, after the lower wiring 20 is formed, a via plug connected to the upper wiring is formed using the same material as the lower wiring 20.
【０００３】図１２に示すように、デュアルダマシン法
においては、まず、下層配線２０たとえばＣｕ配線をダ
マシン法で作製した後、下層配線２０の上に、第１エッ
チストッパ膜３たとえば窒化シリコンを堆積し、その上
にヴィアレベルの層間絶縁膜４を堆積し、その上に第２
エッチストッパ膜５たとえば酸化シリコンを堆積する。
ここに、層間絶縁膜４はＳｉＮとＳｉＯ2から成る膜で
あってもよい。そして、更に、第２エッチストッパ膜５
の上に上層層間絶縁膜６を堆積し、その上にバリア膜８
たとえばＴｉＮを堆積する。As shown in FIG. 12, in the dual damascene method, first, a lower wiring 20 such as a Cu wiring is formed by a damascene method, and then a first etch stopper film 3 such as silicon nitride is deposited on the lower wiring 20. Then, a via-level interlayer insulating film 4 is deposited thereon, and a second
An etch stopper film 5, for example, silicon oxide is deposited.
Here, the interlayer insulating film 4 may be a film made of SiN and SiO 2 . Further, the second etch stopper film 5
An upper interlayer insulating film 6 is deposited on the substrate, and a barrier film 8 is formed thereon.
For example, TiN is deposited.
【０００４】次に、図１３に示すように、フォトレジス
ト７をマスクとして、第２エッチストッパー膜５が抜け
るところまでエッチングして、ヴィアホールを形成す
る。[0004] Next, as shown in FIG. 13, using the photoresist 7 as a mask, etching is performed until the second etch stopper film 5 comes off to form a via hole.
【０００５】次に、図１４に示すように、フォトレジス
ト膜７を除去して新たにフォトレジスト膜７１を配線溝
パターンに形成した後、高選択比エッチング（Ｓｉ
Ｏ2：ＳｉＮ＝２０：１）によりデュアルダマシン形状
にエッチングする。Next, as shown in FIG. 14, after removing the photoresist film 7 and newly forming a photoresist film 71 in a wiring groove pattern, a high selectivity etching (Si
Etch into a dual damascene shape by O 2 : SiN = 20: 1).
【０００６】次に、図１５に示すように、下層配線２０
上の第１エッチストッパ膜３を下層配線２０の表面まで
エッチングする。以上のようにして、デュアルダマシン
形状が形成される。[0006] Next, as shown in FIG.
The upper first etch stopper film 3 is etched to the surface of the lower wiring 20. As described above, a dual damascene shape is formed.
【０００７】上述した従来の技術では、あらかじめ上層
層間絶縁膜６を堆積した直後にバリア膜８を堆積してあ
る。この理由は、下層配線２０の表面すなわちヴィア底
部からバリア膜を除去するためのエッチバック工程で上
層層間絶縁膜６表面のバリア膜８も除去され、この後の
Ｃｕ−ＣＶＤで上層層間絶縁膜６表面にＣｕが直接堆積
することになり、堆積したＣｕ膜の剥がれや上層層間絶
縁膜６中へのＣｕの拡散など問題を生じることを回避す
ベく、エッチバック後にも層間絶縁膜６表面にバリア膜
８が残存させるためである。In the conventional technique described above, the barrier film 8 is deposited immediately after the upper interlayer insulating film 6 is deposited in advance. The reason is that the barrier film 8 on the surface of the upper interlayer insulating film 6 is also removed by an etch-back process for removing the barrier film from the surface of the lower wiring 20, that is, the bottom of the via. Cu is directly deposited on the surface to avoid problems such as peeling of the deposited Cu film and diffusion of Cu into the upper interlayer insulating film 6. This is because the barrier film 8 remains.
【０００８】[0008]
【発明が解決しようとする課題】しかし、図１５に示す
高選択比エッチングの際にバリア膜８としての例えばＴ
ｉＮは第１エッチストッパ膜３たとえばＳｉＮ膜との選
択比が少なくエッチングされにくい。従って、多くのデ
ポ物を生じ、デポ物が付着した第２ストッパ膜５たとえ
ば酸化膜がエッチングされないなどの問題から高選択比
エッチングによるデュアルダマシン溝のエッチング形状
が崩れる。However, at the time of high selectivity etching shown in FIG.
iN has a low selectivity to the first etch stopper film 3, for example, a SiN film, and is hardly etched. Therefore, the etched shape of the dual damascene trench by the high selectivity etching is broken due to the problem that many deposits are generated and the second stopper film 5 to which the deposits adhere, for example, the oxide film is not etched.
【０００９】これを回避するためには、デュアルダマシ
ン溝を形成した後にバリア膜８を堆積することも考えら
れる。In order to avoid this, it is conceivable to deposit the barrier film 8 after forming the dual damascene groove.
【００１０】しかし、通常のスパッタ法やＣＶＤ法では
下層配線２０表面にもバリア膜８が堆積してしまう。However, the barrier film 8 is deposited on the surface of the lower wiring 20 by the ordinary sputtering method or CVD method.
【００１１】そこで、本発明は、形状の崩れのないデュ
アルダマシン溝を形成し、下層配線と上層配線とをヴィ
アプラグで接続することを課題としている。Accordingly, an object of the present invention is to form a dual damascene groove having no deformation in shape and to connect a lower wiring and an upper wiring with a via plug.
【００１２】[0012]
【課題を解決するための手段】上記の課題を解決するた
めの本発明は、下層層間絶縁膜と、前記下層層間絶縁膜
に設けたエッチング溝と、前記エッチング溝に形成した
下層バリア膜と、前記エッチング溝を埋め込む下層配線
と、前記下層層間絶縁膜上に形成した第１エッチストッ
パ膜と、前記第１エッチストッパ膜上に形成したヴィア
レベル層間絶縁膜と、前記ヴィアレベル層間絶縁膜上に
形成した第２エッチストッパ膜と、第２エッチストッパ
膜上に形成した上層層間絶縁膜とを含む半導体装置の製
造方法であって、前記エッチング溝上にデュアルダマシ
ン形状の溝を形成し、前記上層層間絶縁膜の表面と前記
下層配線表面と前記デュアルダマシン形状の溝の側壁と
にバリア膜を形成し、前記バリア膜をエッチバックし
て、前記上層層間絶縁膜の表面及び前記下層配線表面か
ら前記バリア膜を除去し、前記デュアルダマシン形状の
溝を清浄化して前記バリア層を除去し、前記デュアルダ
マシン形状の溝の側壁に上層バリア膜を形成し、前記デ
ュアルダマシン形状の溝を上層配線材料で埋め込むよう
にしている。According to the present invention, there is provided a lower interlayer insulating film, an etching groove provided in the lower interlayer insulating film, a lower barrier film formed in the etching groove, A lower wiring for filling the etching groove; a first etch stopper film formed on the lower interlayer insulating film; a via level interlayer insulating film formed on the first etch stopper film; A method of manufacturing a semiconductor device, comprising: a formed second etch stopper film; and an upper interlayer insulating film formed on the second etch stopper film, wherein a dual damascene-shaped groove is formed on the etching groove, and A barrier film is formed on the surface of an insulating film, the surface of the lower wiring, and the side wall of the dual damascene trench, and the barrier film is etched back to form the upper interlayer insulation. Removing the barrier film from the surface of the film and the lower wiring surface, cleaning the dual damascene-shaped groove to remove the barrier layer, forming an upper barrier film on the side wall of the dual damascene-shaped groove, The dual damascene trench is filled with an upper wiring material.
【００１３】[0013]
【発明の実施の形態】以下、図面を参照して、本発明の
実施の形態について説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１４】図１は、本発明の半導体装置の製造方法で
製造したヴィアプラグの断面図である。図１に示すよう
に、下層層間絶縁膜１中の下層配線２０と上層配線層間
絶縁膜６中の上層配線１０とが下層配線２０と同一の材
料たとえばＣｕのヴィアプラグにより接続されている。
ここで、下層バリア膜２はヴィアプラグの下地である。
又、第１エッチストッパ膜３、ヴィアレベルの層間絶縁
膜４、及び第２エッチストッパ膜５の各材料は、デュア
ルダマシン溝を形成するために、エッチングレートが大
きく異なる材料から選択されている。FIG. 1 is a sectional view of a via plug manufactured by the method of manufacturing a semiconductor device according to the present invention. As shown in FIG. 1, the lower wiring 20 in the lower interlayer insulating film 1 and the upper wiring 10 in the upper wiring interlayer insulating film 6 are connected by the same material as the lower wiring 20, for example, via plug of Cu.
Here, the lower barrier film 2 is a base of the via plug.
The materials of the first etch stopper film 3, the via-level interlayer insulating film 4, and the second etch stopper film 5 are selected from materials having greatly different etching rates in order to form a dual damascene groove.
【００１５】図２乃至図１０は、本発明のヴィアプラグ
の形成方法の工程図である。2 to 10 are process diagrams of a method for forming a via plug according to the present invention.
【００１６】図２に示すように、まず、下層配線２０例
えばＣｕ配線をダマシン法で作製した後、下層配線２０
の上に、第１エッチストッパ膜３たとえば窒化シリコン
を堆積し、その上にヴィアレベルの層間絶縁膜４を堆積
し、その上に第２エッチストッパ膜５たとえば酸化シリ
コンを堆積する。ここに、ヴィアレベルの下層層間絶縁
膜４はＳｉＮとＳｉＯ2から成る膜であってもよい。そ
して、更に、第２エッチストッパ膜５の上に上層層間絶
縁膜６を堆積する。As shown in FIG. 2, first, a lower wiring 20 such as a Cu wiring is formed by a damascene method, and then the lower wiring 20 is formed.
A first etch stopper film 3 such as silicon nitride is deposited thereon, a via-level interlayer insulating film 4 is deposited thereon, and a second etch stopper film 5 such as silicon oxide is deposited thereon. Here, the via-level lower interlayer insulating film 4 may be a film made of SiN and SiO 2 . Then, an upper interlayer insulating film 6 is further deposited on the second etch stopper film 5.
【００１７】第１エッチストッパ層３は例えばＳｉＮ層
であり、第２エッチストッパ層は例えば、ＳｉＯ2層で
あり、プラズマＣＶＤ法により積層する。各層の膜厚は
第１エッチストッパ層３が１０００Å、ヴィアレベルの
層間絶縁膜４が５０００Å、 第２のエッチストッパーが
３０００Åである。 The first etch stopper layer 3 is, for example, a SiN layer, and the second etch stopper layer is, for example, an SiO 2 layer, which is laminated by a plasma CVD method. The thickness of each layer is
The first etch stopper layer 3 has a thickness of 1000
The interlayer insulating film 4 is 5000Å, and the second etch stopper is
3000 $.
【００１８】次に、図３に示すように、フォトレジスト
７を塗布し、ヴィアホールパターンに成形した後、ヴィ
アホールを上層の第２のエッチストッパー膜５が抜ける
ところまでエッチングする。Next, as shown in FIG. 3, a photoresist 7 is applied to form a via hole pattern, and then the via hole is etched until the upper second etch stopper film 5 is removed.
【００１９】次に、図４に示すように、ヴィアホールパ
ターンのフォトレジスト７を除去した後、新たにフォト
レジスト７１を塗布し、配線溝パターンに成形する。Next, as shown in FIG. 4, after removing the photoresist 7 in the via hole pattern, a new photoresist 71 is applied to form a wiring groove pattern.
【００２０】次に、図５に示すように、高選択比エッチ
ング（ＳｉＯ2：ＳｉＮ＝２０：１）によりデュアルダ
マシン形状にエッチングする。高選択比エッチングに
は、エッチングガスにＣＦ4，ＣＨＦ3，ＣＯ，Ｏ2を用
いた反応性イオンエッチング（ＲＩＥ）を用いることが
できる。Next, as shown in FIG. 5, a dual damascene shape is etched by high selectivity etching (SiO 2 : SiN = 20: 1). Reactive ion etching (RIE) using CF 4 , CHF 3 , CO, and O 2 as an etching gas can be used for the high selectivity etching.
【００２１】次に、図６に示すように、レジスト剥離の
酸素プラズマにＣｕ表面がさらされることを避けるた
め、前もってレジストを除去する。そして、その後、下
層配線２０のＣｕ上の第１エッチストッパ膜３のＳｉＮ
膜をＣｕ表面まで通常のＲＩＥによりエッチングする。Next, as shown in FIG. 6, the resist is removed in advance in order to prevent the Cu surface from being exposed to oxygen plasma for stripping the resist. Then, thereafter, the SiN of the first etch stopper film 3 on Cu of the lower wiring 20 is formed.
The film is etched to the Cu surface by normal RIE.
【００２２】次に、図７に示すように、テトラキスジエ
チルアミノチタン（ＴＤＥＡＴ：ｔｅｔｒａｋｉｓｄｉ
ｅｔｈｙｌ−ａｍｉｎｏ−ｔｉｔａｎｉｕｍ）を原料と
してバリア層８としてのＭＯＣＶＤ−ＴｉＮ膜（５００
Å）を３００℃で成膜する。Next, as shown in FIG. 7, tetrakisdiethylaminotitanium (TDEAT: tetrakisdi)
MOCVD-TiN film (500) as barrier layer 8 using ethyl-amino-titanium as a raw material.
Å) is formed at 300 ° C.
【００２３】次に、図８に示すように、このバリア層８
としてのＴｉＮ膜をエッチバックにより下層配線２０と
してのＣｕ表面から除去する。又、ウェットおよびドラ
イクリーニングを行い、ヴィアホール内部を清浄化す
る。そして、図示していないが、更に、ヴィアホール側
壁のバリア層８を除去する。 Next, as shown in FIG.
Is removed from the Cu surface as the lower wiring 20 by etch back. Further, by wet and dry cleaning, to clean the inside via hole
You. And, although not shown, the via hole side
The barrier layer 8 on the wall is removed.
【００２４】次に、図９に示すように、斜めスパッタに
より絶縁層間膜上面に優先的に上層バリア層９としての
ＴｉＮ膜を成膜する。ここで、斜めスパッタにおいて
は、図１１に示すように、スパッタリングターゲットに
対して半導体ウエハを傾けて回転させる。こうすること
により、スパッタされた粒子は、ヴィアホール側壁に堆
積し、ヴィアホールの底部、すなわち、下層配線２０の
表面には、スパッタされた粒子は到達しない。Next, as shown in FIG. 9, a TiN film as an upper barrier layer 9 is formed preferentially on the upper surface of the insulating interlayer film by oblique sputtering. Here, in the oblique sputtering, as shown in FIG. 11, the semiconductor wafer is tilted and rotated with respect to the sputtering target. By doing so, the sputtered particles are deposited on the side wall of the via hole, and the sputtered particle does not reach the bottom of the via hole, that is, the surface of the lower wiring 20.
【００２５】次に、図１０に示すように、トリメチルヴ
ィニルシリルヘキサフルオロアセチルアセトネート銅
（Ｃｕ（ｈｆａｃ）（ｔｍｖｓ）：ｔｒｉｍｅｔｈｙｌ
ｖｎｉｌｓｉｌｙｌｈｅｘａｆｌｕｏｒｏａｃｅｔｙｌ
ａｃｅｔｏｎａｔｏ Ｃｏｐｐｅｒ（Ｉ）をプリカーサ
としたＣＶＤ法により１７０℃で上層配線１０例えばＣ
ｕを８０００Å成膜する。Ｃｕ膜の密着性向上、粒成長
のため窒素アニール（４００℃×３０ｍｉｎ．）を行っ
た後、アルミナスラリーを用いたＣＭＰにより図１に示
す配線形状を形成する。Next, as shown in FIG. 10, copper trimethylvinylsilyl hexafluoroacetylacetonate (Cu (hfac) (tmvs): trimethyl)
vnilsilylhexafluoroacetyl
The upper wiring 10 such as C at 170 ° C. by the CVD method using acetonato copper (I) as a precursor.
u is deposited at 8000 °. After performing nitrogen annealing (400 ° C. × 30 min.) For improving the adhesion of the Cu film and growing grains, the wiring shape shown in FIG. 1 is formed by CMP using alumina slurry.
【００２６】以上、本発明の実施形態について説明した
が、本発明はこれに限らず、上層配線膜１０としての８
０００ÅのＣＶＤ−Ｃｕ膜に替えて、ＣＶＤ−Ｃｕ膜を
１０００Å以下とし、その上に、銅めっきを施してもよ
い。Although the embodiment of the present invention has been described above, the present invention is not limited to this.
Instead of the 2,000-cm CVD-Cu film, the thickness of the CVD-Cu film may be 1000 mm or less, and copper plating may be applied thereon.
【００２７】又、第１エッチストッパ膜３としてＳｉＮ
膜を用い、第２エッチストッパ膜５としてエッチングの
選択比が大きいＳｉＯ2膜を用いたが、ＳｉＯ2膜に替え
て、酸化弗化シリコンＳｉＯＦ膜やシルセスキオクサン
水素（ＨＳＱ（Ｈｙｄｒｏｇｅｎ Ｓｉｌｓｅｓｑｕｉ
ｏｘａｎｅ）膜を用いてもよい。The first etch stopper film 3 is made of SiN.
Although a SiO 2 film having a large etching selectivity was used as the second etch stopper film 5 instead of the SiO 2 film, a silicon oxyfluoride SiOF film or a silsesquioxane hydrogen (HSQ) was used instead of the SiO 2 film.
oxane) film may be used.
【００２８】[0028]
【発明の効果】以上説明した本発明によれば、デュアル
ダマシン法における配線溝およびヴィアホールのパター
ンニング（エッチング）を窒化膜（ＳｉＮ）ストッパー
を用いた高選択比エッチングが良好に行えるので、ヴィ
アプラグが上下層配線とバリア膜を介さないホモ接合構
造の低抵抗多層配線の形成が可能となる。According to the present invention described above, patterning (etching) of wiring trenches and via holes in the dual damascene method can be favorably performed by high selectivity etching using a nitride film (SiN) stopper. It is possible to form a low-resistance multilayer wiring having a homojunction structure in which the plug does not pass through the upper and lower wiring layers and the barrier film.
【００２９】又、本発明によれば、斜めスパッタで成膜
したバリア膜が配線溝側壁に逆テーパー（溝の出口方向
に厚い）に堆積しているため、化学的機械研磨（ＣＭ
Ｐ）による配線の配線溝からの抜けを起こりにくくして
いる。According to the present invention, since the barrier film formed by oblique sputtering is deposited on the side wall of the wiring groove in a reverse taper (thick in the direction of the groove exit), chemical mechanical polishing (CM) is performed.
P) makes it difficult for the wiring to come off from the wiring groove.
【図１】本発明の半導体装置の製造方法による多層配線
の断面図。FIG. 1 is a cross-sectional view of a multilayer wiring according to a method for manufacturing a semiconductor device of the present invention.
【図２】本発明の半導体装置の製造方法の工程図。FIG. 2 is a process chart of a method for manufacturing a semiconductor device of the present invention.
【図３】本発明の半導体装置の製造方法の工程図（続
き）。FIG. 3 is a process chart of a method for manufacturing a semiconductor device of the present invention (continued).
【図４】本発明の半導体装置の製造方法の工程図（続
き）。FIG. 4 is a process diagram (continued) of the method for manufacturing a semiconductor device of the present invention.
【図５】本発明の半導体装置の製造方法の工程図（続
き）。FIG. 5 is a process chart of the method for manufacturing a semiconductor device of the present invention (continued).
【図６】本発明の半導体装置の製造方法の工程図（続
き）。FIG. 6 is a process diagram (continued) of the method for manufacturing a semiconductor device of the present invention.
【図７】本発明の半導体装置の製造方法の工程図（続
き）。FIG. 7 is a process chart of the method for manufacturing a semiconductor device of the present invention (continued).
【図８】本発明の半導体装置の製造方法の工程図（続
き）。FIG. 8 is a process chart (continued) of the method for manufacturing a semiconductor device of the present invention.
【図９】本発明の半導体装置の製造方法の工程図（続
き）。FIG. 9 is a process chart (continued) of the method for manufacturing a semiconductor device according to the present invention.
【図１０】本発明の半導体装置の製造方法の工程図（続
き）。FIG. 10 is a process chart of the method for manufacturing a semiconductor device of the present invention (continued).
【図１１】斜めスパッタの概念図。FIG. 11 is a conceptual diagram of oblique sputtering.
【図１２】従来の多層配線形成工程の工程図。FIG. 12 is a process diagram of a conventional multilayer wiring forming process.
【図１３】従来の多層配線形成工程の工程図（続き）。FIG. 13 is a process diagram of a conventional multilayer wiring forming process (continued).
【図１４】従来の多層配線形成工程の工程図（続き）。FIG. 14 is a process diagram of a conventional multilayer wiring forming process (continued).
【図１５】従来の多層配線形成工程の工程図（続き）。FIG. 15 is a process diagram of a conventional multilayer wiring forming process (continued).
１ 下層層間絶縁膜 ２ 下層バリア膜 ３ 第１エッチストッパ膜 ４ ヴィアレベルの層間絶縁膜 ５ 第２エッチストッパ膜 ６ 上層層間絶縁膜 ７，７１ フォトレジスト膜 ８ バリア膜 ９ 上層バリア層 １０ 上層配線 ２０ 下層配線 Reference Signs List 1 lower interlayer insulating film 2 lower barrier film 3 first etch stopper film 4 via-level interlayer insulating film 5 second etch stopper film 6 upper interlayer insulating film 7, 71 photoresist film 8 barrier film 9 upper barrier layer 10 upper wiring 20 Lower layer wiring
Claims (3)
に設けたエッチング溝と、前記エッチング溝に形成した
下層バリア膜と、前記エッチング溝を埋め込む下層配線
と、前記下層層間絶縁膜上に形成した第１エッチストッ
パ膜と、前記第１エッチストッパ膜上に形成したヴィア
レベル層間絶縁膜と、前記ヴィアレベル層間絶縁膜上に
形成した第２エッチストッパ膜と、第２エッチストッパ
膜上に形成した上層層間絶縁膜とを含む半導体装置の製
造方法であって、 前記エッチング溝上にデュアルダマシン形状の溝を形成
し、 前記上層層間絶縁膜の表面と前記下層配線表面と前記デ
ュアルダマシン形状の溝の側壁とにバリア膜を形成し、 前記バリア膜をエッチバックして、前記上層層間絶縁膜
の表面及び前記下層配線表面から前記バリア膜を除去
し、 前記デュアルダマシン形状の溝を清浄化して前記バリア
層を除去し、 前記デュアルダマシン形状の溝の側壁に上層バリア膜を
形成し、 前記デュアルダマシン形状の溝を上層配線で埋め込むこ
とを特徴とする半導体装置の製造方法。A lower interlayer insulating film; an etching groove provided in the lower interlayer insulating film; a lower barrier film formed in the etching groove; a lower wiring filling the etching groove; A first etch stopper film formed, a via level interlayer insulating film formed on the first etch stopper film, a second etch stopper film formed on the via level interlayer insulating film, and a second etch stopper film on the second etch stopper film. A method of manufacturing a semiconductor device, comprising: a formed upper interlayer insulating film; a dual damascene-shaped groove formed on the etching groove; and a surface of the upper interlayer insulating film, a lower wiring surface, and the dual damascene-shaped groove. A barrier film is formed on the side wall of the substrate and the barrier film is etched back to remove the barrier film from the surface of the upper interlayer insulating film and the surface of the lower wiring. Removing the barrier layer by cleaning the dual damascene-shaped groove, forming an upper barrier film on a side wall of the dual damascene-shaped groove, and filling the dual damascene-shaped groove with an upper wiring. Manufacturing method of a semiconductor device.
形成することを特徴とする請求項１記載の半導体装置の
製造方法。2. The method according to claim 1, wherein the upper barrier film is formed by an oblique sputtering method.
と同一の成分元素を含み、前記上層配線は、前記下層配
線と同一の成分元素を含むことを特徴とする請求項１記
載の半導体装置の製造方法。3. The semiconductor device according to claim 1, wherein the upper barrier film contains the same component element as the lower barrier film, and the upper wiring contains the same component element as the lower wiring. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25304998A JP3189970B2 (en) | 1998-09-07 | 1998-09-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25304998A JP3189970B2 (en) | 1998-09-07 | 1998-09-07 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000091425A JP2000091425A (en) | 2000-03-31 |
| JP3189970B2 true JP3189970B2 (en) | 2001-07-16 |
Family
ID=17245781
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25304998A Expired - Fee Related JP3189970B2 (en) | 1998-09-07 | 1998-09-07 | Method for manufacturing semiconductor device |
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| JP (1) | JP3189970B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4858895B2 (en) * | 2000-07-21 | 2012-01-18 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| JP3540302B2 (en) | 2001-10-19 | 2004-07-07 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP3877613B2 (en) | 2002-03-05 | 2007-02-07 | 三洋電機株式会社 | Method for manufacturing organic electroluminescence display device |
| JP2004128074A (en) | 2002-09-30 | 2004-04-22 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
| JP2004140198A (en) | 2002-10-18 | 2004-05-13 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| CN100524734C (en) | 2003-09-09 | 2009-08-05 | 三洋电机株式会社 | Semiconductor module including circuit device and insulating film, method for manufacturing same, and application of same |
| DE102007020263B4 (en) * | 2007-04-30 | 2013-12-12 | Infineon Technologies Ag | Verkrallungsstruktur |
| US9076821B2 (en) | 2007-04-30 | 2015-07-07 | Infineon Technologies Ag | Anchoring structure and intermeshing structure |
| FR2917893B1 (en) * | 2007-06-22 | 2009-08-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING AN ELECTRICAL CONNECTION BASED ON CARBON NANOTUBES |
| JP5407340B2 (en) * | 2009-01-07 | 2014-02-05 | 富士通セミコンダクター株式会社 | Wiring formation method |
| JP5104924B2 (en) * | 2010-08-23 | 2012-12-19 | 富士通セミコンダクター株式会社 | Semiconductor device |
| WO2012127861A1 (en) * | 2011-03-22 | 2012-09-27 | パナソニック株式会社 | Method for manufacturing nonvolatile storage device |
| CN103390628B (en) * | 2012-05-08 | 2016-08-03 | 复旦大学 | Resistor-type memory of rear end structure being integrated in integrated circuit and preparation method thereof |
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1998
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|---|---|
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