JPH05324365A - System for inspecting module identifier repetition - Google Patents

Abstract

PURPOSE:To previously detect module ID repetition when module ID setting is repeated by a human system error. CONSTITUTION:Modules 30-1 to 30-n which are connected to CPU 10 with a serial bus 20 are constituted in such a way that, when the modules 30-1 and 30-2, for example, are set to a unique ID output mode by CPU 10 by the designation of a module ID which is the same one as the module ID being set by the ID switches 31-1 and 31-2, information adding unique ID which is decided by the mounted position of the modules 30-1 and 30-2 is outputted from shift registers 32-1 and 32-2 to the output line 22 of a bus 20 with drivers 35-1 and 35-2 and a signal in the output line 22 is fetched so as to be compared with the output signal from the registers 32-1 and 32-2 by comparing circuits 36-1 and 36-2 so that abnormality is reported to CPU 10 with the control line 22 of the bus 20 when noncoincidence is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system in which a CPU communicates with various modules via a bus, and particularly detects a duplication of module identifiers in a system in which an identifier of each module can be arbitrarily set by a switch. The present invention relates to a module identifier duplication check method suitable for doing so.

[0002]

2. Description of the Related Art As shown in FIG. 4, in a computer system in which a CPU 1 communicates with various modules 3-1 to 3-n via a system bus 2, the CPU 1 is a communication partner by an identifier called a module ID. It is common to specify a module.

Each of the modules 3-1 to 3-n has a switch (ID switch) 4-1 to set a module ID.
4-n are provided. Modules 3-1 to 3-n are CP
When the module ID for designating the communication partner is transferred from U1 via the system bus 2, the designated module ID is compared with its own module ID set by the ID switches 4-1 to 4-n. If the two IDs match, it is determined that it has been designated, and communication is performed with the CPU 1.

Module ID of each module 3-1 to 3-n
Can be arbitrarily set by a user or the like operating the ID switches 4-1 to 4-n. For this reason, there is a possibility that the switch ID may be erroneously set and the module ID may be duplicated in a plurality of modules. If the module ID designated by the CPU 1 is set redundantly in a plurality of modules, the plurality of modules operate at the same time, causing a problem such as data collision (data destruction).

[0005]

As described above, the CP
In the conventional computer system in which U communicates with various modules via the bus, if the module ID is set redundantly in multiple modules due to a human error, the module ID is specified. When attempting to determine a module to be a communication partner, a plurality of modules operate at the same time, which causes a problem such as data collision.

The present invention has been made in view of the above circumstances, and an object thereof is a computer system in which a CPU communicates with various modules via a bus, and a module identifier (module ID) is set by a human error. An object of the present invention is to provide a module identifier duplication inspection method capable of detecting the duplication of the module identifiers in advance when the duplication is performed in a plurality of modules.

[0007]

According to the present invention, in a computer system in which a CPU designates a module ID to communicate with a module having a module ID matching a designated ID among a plurality of modules, Module ID from the CPU for each of the above modules
Output means for outputting a unique ID (unique ID) determined by the mounting position of the module to a bus for connecting the CPU and a plurality of modules when the module is selected by designating the module ID for duplication check And a comparison means for comparing the data output to the bus by the output means with the data on the bus, and the duplication of the module ID is detected by the comparison result of the comparison means. To do.

[0008]

In the above structure, if the module IDs do not overlap, C for module ID duplication check is performed.
Only one module is selected by the module ID designation from the PU. In this case, the unique ID output to the bus from the output means of the only selected module
And the data on the bus match. Therefore, the comparison means of the selected modules detects a match, indicating that the designated module IDs are not duplicated.

On the other hand, when the designated module IDs are duplicated, two or more modules are selected. In this case, the unique IDs of the respective modules are output from the output means of the selected two or more modules on the bus, and are ORed on the bus. The data on this bus does not match the unique ID output from the output means. Therefore, the comparison means of the selected modules detects a mismatch and indicates that the designated module IDs are duplicated.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a module identifier (ID) of the present invention.
It is a block configuration diagram showing one embodiment of a computer system to which the duplication check method is applied.

In FIG. 1, reference numeral 10 is a CPU which serves as a control center of the system. The CPU 10 includes a system bus (not shown) and an RAS (Reli) provided independently of the bus.
ability, availability, serviceability) Various modules 30-1, 3 by the serial bus 20 for collecting information
0-2 ... 30-n are connected. Serial bus 20
The module 30-1 to 30-n has a 1-bit input line 21, a 1-bit output line 22 and a control line 23 for notifying an abnormality.

The modules 30-1 and 30-2 are provided with switches (ID switches) 31-1 and 31-2 capable of arbitrarily setting the IDs (module IDs) of the modules 30-1 and 30-2. ing.

The modules 30-1 and 30-2 also have shift registers 32-1 and 32-2 for shifting the input data bit by bit (and outputting it to the output line 22 of the serial bus 20). It is provided. When the modules 30-1 and 30-2 are selected for the module ID duplication check, the CPs are assigned to the shift registers 32-1 and 32-2.
For example, 8-bit start code S and end code E sent from U10 via input line 21 of serial bus 20, module ID set by ID switches 31-1, 31-2, and corresponding module 30
-1 and 30-2, the unique IDs (to be referred to as unique IDs hereinafter) determined by the mounting positions of the modules (hereinafter referred to as unique IDs) are taken in the order of the start code S, the module ID, the unique ID, and the end code E. It is supposed to be. The unique ID is generated by a combination of pull-up / pull-down of signals at the mounting position when the module is mounted (via a connector or the like). Module I in this embodiment
It is assumed that D and the unique ID are composed of 8 bits, and the upper 4 bits thereof are “0” in hexadecimal notation.

The modules 30-1 and 30-2 are further provided with output signals 33 output serially from the shift registers 32-1 and 32-2 (that is, output signals of the modules 30-1 and 30-2).
-1, 33-2 as output signals 34-1, 34-2 to the output line 22 of the serial bus 20 and output drivers (D) 35-1, 35-2, and ID switches 31-1, 31 -2
Comparing circuits 36-1 and 36-2 for checking the duplication of the module IDs set by the above are provided.

The comparator circuits 36-1 and 36-2 have two inputs, one of which has the modules 30-1 and 3-3.
0-2 (the shift registers 32-1 and 32-2 thereof) output signals 33-1 and 33-2, and the other input B receives the signal on the output line 22 of the serial bus 20 as a check signal. 37-
It is introduced as 1, 37-2. The outputs of the comparison circuits 36-1 and 36-2 are connected to the control line 23 of the serial bus 20 via the abnormality notification lines 38-1 and 38-2. Although the configuration of the modules other than the modules 30-1 and 30-2 is omitted in FIG. 1, the basic configuration is the same as the modules 30-1 and 30-2.

Next, the operation of the configuration shown in FIG. 1 will be described. CP
When starting up the computer system, the U10 checks whether or not the module ID settings in the modules 30-1 to 30-n are duplicated.

That is, the CPU 10 includes modules 30-1 to 30-1.
Module ID that can be set with 30-n (in hexadecimal notation)
The module ID duplication check is performed by repeating the operation of setting the module designated by the module ID to the unique ID output mode while sequentially counting up from the initial value “00” to the maximum value “0F”.

A specific example of this module ID duplication check is described below.
When the CPU 10 sets the module with the module ID “0C” (hexadecimal expression) in the unique ID output mode, the module IDs of the modules 30-1 and 30-2 of the modules 30-1 to 30-n are A case will be described in which (by the ID switches 31-1 and 31-2) the duplication setting is made to "0C". In the following explanation,
Unless otherwise specified, the values of the module ID and unique ID are represented by hexadecimal numbers.

Now, in order to set the module whose module ID is "0C" to the unique ID output mode, the CPU
From 10 to the system bus (not shown), the function information for setting the unique ID output mode is the module ID
It shall be transmitted together with "0C".

Then, the CPU 10 is connected via the system bus.
Among the modules 30-1 to 30-n connected to the two modules, the two modules 30-1 and 30-2 whose module IDs are set to "0C" are simultaneously selected and set to the unique ID output mode. To be done.

When the CPU 10 sends the function information for setting the unique ID output mode, the start code S and the end code E for determining the timing of the unique ID output from the designated module are sequentially input to the serial bus 20 bit by bit. Send on line 21. Between the start code S and the end code E, a 16-bit space in which a module ID and a unique ID can be inserted is secured.

The start code S and end code E transferred via the input line 21 of the serial bus 20 are (C
Module 30 in the unique ID output mode (selected by the module ID “0C” designation from PU 10)
-1, 30-2 received only in the module 30
-1, 30-2 in the shift registers 32-1 and 32-2 in order.

Then, when the last bit of the end code E is taken into the shift registers 32-1 and 32-2, the start code S and the end code E in the shift registers 32-1 and 32-2.
Between the ID switches 3 of the modules 30-1 and 30-2
Module ID set in 1-1 and 31-2 (here,
"0C" that has been set redundantly) and modules 30-1, 3
Unique ID that is a unique value determined by the mounting position of 0-2
(Here, “06” and “0A”) are inserted.

Then, the contents of the shift register 32-1, that is, the start code S and the module ID of the module 30-1
“0C”, the unique ID “06” of the module 30-1, and the end code E are output signals 33 of the module 30-1.
Serially output as -1. At the same time, the contents of the shift register 32-2, that is, the start code S, the module ID “0C” of the module 30-2, the unique ID “0A” of the module 30-2, and the end code E are the module 30-1.
Are serially output as the output signal 33-1 of This situation is shown in the timing chart of FIG. 2 for the period between the start code S and the end code E.

Now, the output signals 33-1 and 3 from (the shift registers 32-1 and 32-2 of) the modules 30-1 and 30-2.
3-2 is an output signal 3 by the output drivers 35-1 and 35-2.
Output lines 22 of the serial bus 20 as 4-1 and 34-2
Are sent to the same time. This causes signals 34-1 and 34-2 to be generated.
Are wired or on output line 22.

The signal on the output line 22 of the serial bus 20 is the module 30-in the unique ID output mode.
One of the inputs of the comparison circuits 36-1 and 36-2 of 1, 33-2,
The inspection signals 37-1 and 37-2 are input. Comparison circuit 3
Modules 30-1, 3 are connected to the other inputs of 6-1 and 36-2.
The output signals 33-1 and 33-2 from 0-2 (the shift registers 32-1 and 32-2) are input.

(Comparison circuit 3 of modules 30-1 and 30-2 (
6-1, 36-2) input inspection signals 37-1, 37-2
The modules 30-1 and 30-2 themselves are output drivers 35.
The output signals 34-1 and 34-2 output on the output line 22 by -1, 35-2 are signals wired or ORed on the same line 22. The signals 37-1 and 37-2 are transmitted to the modules 30-1 and 30-2 (shift registers 32-1 and 32-2 thereof).
The output signals 33-1 and 33-2 from 1 are matched with the OR signal, and the signal state in the period between the start code S and the end code E is as shown in FIG.

Here, output signals 33-1 from (shift registers 32-1 and 32-2 of) the modules 30-1 and 30-2,
The unique ID in 33-2 is “06”, “0A” (in binary representation, “00000110”, “00001010”)
And are different. In this case, the inspection signals 37-1, 3
As shown in the timing chart of FIG. 2, the corresponding portion in 7-2 is “00001110” in binary representation and the output signal 3
It is different from any of the unique IDs in 3-1 and 33-2.

Comparison circuit 3 in modules 30-1 and 30-2
6-1 and 36-2 are output signals 33-1 and 33 from (the shift registers 32-1 and 32-2 of) the modules 30-1 and 30-2.
-2 and the inspection signals 37-1, 37-2 taken into the modules 30-1, 30-2 from the output line 22 of the serial bus 20.
And between the shift operations of the shift registers 32-1 and 32-2, that is, from the output of the first bit of the start code S to the output of the last bit of the end code E (provided that a mismatch is detected. Is until the end of its detection) period 1
Compare bit by bit. It is also possible to internally hold all the bits from the first bit of the start code S to the last bit of the end code E in the serial input parallel output register or the like and then compare them all at once.

The comparison circuits 36-1 and 36-2 have the unique IDs in the output signals 33-1 and 33-2 and the inspection signals 37-1 and 3-2.
In the comparison with the corresponding part of 7-2, the disagreement is detected at the points P1 and P2 in FIG. FIG. 3 shows the signal input / output state of the comparison circuit 36-2 of the module 30-2 at the point P2.

Comparison circuit 3 in modules 30-1 and 30-2
When 6-1 and 36-2 detect inconsistency at points P1 and P2 in FIG. 2, it is determined that the module IDs set in the modules 30-1 and 30-2 are duplicated, and the abnormality notification line 3
An abnormality notification signal is output to 8-1 and 38-2. The abnormality notification signals on the abnormality notification lines 38-1 and 38-2 are the serial bus 2
It is transmitted to the CPU 10 via the control line 23 of 0. As a result, the CPU 10 recognizes that the module ID “0C” designated by itself is set redundantly in a plurality of modules.

Next, the case where the module ID "0C" designated by the CPU 10 is set only in the module 30-1, for example, will be briefly described. in this case,
Only the module 30-1 is selected to enter the unique ID output mode, and the module 30-1 (the shift register 3 in the
Data is output only from 2-1). Therefore, the output signal 33-1 from the module 30-1 (the shift register 32-1 therein) and the check signal 37-1 taken into the module 30-1 from the output line 22 of the serial bus 20 match, No abnormality notification signal is output from the comparison circuit 36-1 to the control line 23 of the serial bus 20.

When no abnormality notification is returned from the module specified by the module ID via the control line 23, the CPU 10 determines that the module ID is not set redundantly. In this case, the CPU 10
Captures the output signal sent on the output line 22 of the serial bus 20 from the only specified module in the unique ID output mode, and outputs the unique ID in the output signal.
As a result, the mounting position of the module to which the designated module IDs are set does not overlap is recognized.

Although the serial bus 20 provided for collecting the RAS information is used for the module ID duplication check in the above embodiment, the system bus may be used in the same manner. ..

In the above embodiment, the module 30-1 is used.
Since the module ID once set to ~ 30-n does not change at all times, it was explained that the module ID duplication check is performed at system startup (after maintenance and expansion). Also, for example, it may be performed periodically. In this case, even if the output data from the designated module is broken on the bus due to some failure of the bus, the abnormality can be detected.

[0036]

As described in detail above, according to the present invention,
When each module connected to the CPU via the bus is selected by the module ID designation for the module ID duplication check from the CPU, a unique ID (unique ID determined by the mounting position of the module) Since the output means for outputting (ID) to the bus and the comparison means for comparing the data output to the bus by the output means with the data on the bus are provided,
Module ID in multiple modules due to human error
Even if the two are set redundantly, the overlapping setting can be easily detected by the comparison result of the comparison means.

Further, conventionally, even if a problem such as data destruction occurs due to simultaneous communication of a plurality of modules due to duplication of module IDs, the cause is not noticed as duplication of module IDs, and another place is investigated. However, according to the present invention, the module ID
It is possible to eliminate such waste because it is possible to reliably inspect the duplication.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a computer system to which a module identifier (ID) duplication check method of the present invention is applied.

FIG. 2 is a timing chart for explaining an operation at the time of a module ID duplication check in the embodiment.

3 is a timing chart of FIG. 2 at a point P2,
The figure which shows the signal input / output state of the comparison circuit 36-2 of the module 30-2.

FIG. 4 is a diagram showing a basic system configuration of a computer system in which a CPU communicates with various modules via a bus.

[Explanation of symbols]

10 ... CPU, 20 ... Serial bus, 21 ... Input line, 22 ... Output line, 23 ... Control line, 3
0-1 to 30-n ... Module, 31-1, 31-2 ... ID switch, 32-1, 32-2 ... Shift register, 36-1, 36
-2 ... Comparison circuit.

Claims (1)

[Claims] 1. A computer system that communicates with a module having a module identifier that matches the designated identifier among a plurality of modules that can communicate with the CPU when the CPU designates the module identifier. And a bus for connecting the plurality of modules to each other, provided in each of the modules, and determined by the mounting position of the module when selected by the module identifier designation from the CPU for the module identifier duplication check Output means for outputting a unique identifier to the bus, and comparison means provided in each of the modules for comparing the data output to the bus by the output means in the module with the data on the bus. According to the comparison result of the comparison means, A module identifier duplication check method characterized by detecting duplication of a child.