JPH05313188A - Matrix type display device - Google Patents
Matrix type display deviceInfo
- Publication number
- JPH05313188A JPH05313188A JP11472192A JP11472192A JPH05313188A JP H05313188 A JPH05313188 A JP H05313188A JP 11472192 A JP11472192 A JP 11472192A JP 11472192 A JP11472192 A JP 11472192A JP H05313188 A JPH05313188 A JP H05313188A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode
- gate
- charge
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims description 31
- 239000010408 film Substances 0.000 claims abstract description 213
- 238000003860 storage Methods 0.000 claims abstract description 40
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 42
- 229910021417 amorphous silicon Inorganic materials 0.000 description 12
- 230000007547 defect Effects 0.000 description 9
- 230000014759 maintenance of location Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000012769 display material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 101000652359 Homo sapiens Spermatogenesis-associated protein 2 Proteins 0.000 description 1
- 101000642464 Homo sapiens Spermatogenesis-associated protein 2-like protein Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 102100030254 Spermatogenesis-associated protein 2 Human genes 0.000 description 1
- 229910004164 TaMo Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、マトリックス型表示装
置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display device.
【０００２】[0002]
【従来の技術】マトリックス型表示装置は、通常２枚の
対向する基板のあいだに液晶などの表示材料が挟持さ
れ、この表示材料に選択的に電圧が印加されるように構
成されている。前記基板の少なくとも一方には、マトリ
ックス状に配列された透明性導電膜からなる画素電極が
設けられ、これらの画素電極毎に選択的に電圧を印加す
るためのトランジスタなどのスイッチング素子および電
荷を保持するための電荷保持容量が設けられている。前
記トランジスタのゲート絶縁膜および電荷保持容量用絶
縁膜の短絡欠陥を低減するために、これらの絶縁膜は２
層に形成されている。従来のこの種の装置としては、図
５および図６に示すものがあった。図６は、従来のマト
リックス型表示装置の画素の平面図、図５はその断面図
である。2. Description of the Related Art A matrix type display device is usually constructed such that a display material such as liquid crystal is sandwiched between two facing substrates and a voltage is selectively applied to the display material. Pixel electrodes made of transparent conductive films arranged in a matrix are provided on at least one of the substrates, and a switching element such as a transistor for selectively applying a voltage to each of the pixel electrodes and a charge retention unit. A charge storage capacitor is provided for this purpose. In order to reduce short-circuit defects of the gate insulating film of the transistor and the insulating film for charge storage capacitor, these insulating films are
Formed in layers. As a conventional device of this type, there is one shown in FIGS. FIG. 6 is a plan view of a pixel of a conventional matrix type display device, and FIG. 5 is a sectional view thereof.
【０００３】図５および図６において、透明絶縁性基板
１上にゲート電極線３と接続される電荷保持容量用下部
電極２ならびにゲート電極３ａおよびそれらを連結する
ゲート電極線３が形成され、その上に１層目の第１のゲ
ート絶縁膜16、および２層目の第２のゲート絶縁膜17が
形成され、第２のゲート絶縁膜17上で、前記ゲート電極
３ａ部分の上に、ノンドープアモルファスシリコン層
７、リンドープアモルファスシリコン層９、ソース電極
10ａおよびそれらを連結するソース電極線10とドレイン
電極11が順次形成されている。さらに、電荷保持容量部
分では、前述の電荷保持容量用下部電極２上に、前述の
第１および第２ゲート絶縁膜16、17が延長してそれぞれ
第１および第２の電荷保持容量用絶縁膜16ａ、17ａが形
成され、さらにその上にドレイン電極11に接続された透
明導電膜からなる画素電極12が形成され、両者の表面に
保護膜13が形成されている。5 and 6, a lower electrode 2 for a charge storage capacitor connected to a gate electrode line 3, a gate electrode 3a and a gate electrode line 3 connecting them are formed on a transparent insulating substrate 1. A first gate insulating film 16 of a first layer and a second gate insulating film 17 of a second layer are formed on the second gate insulating film 17, and a non-doped layer is formed on the gate electrode 3a portion on the second gate insulating film 17. Amorphous silicon layer 7, phosphorus-doped amorphous silicon layer 9, source electrode
10a and a source electrode line 10 and a drain electrode 11 connecting them are sequentially formed. Further, in the charge storage capacitor portion, the above-mentioned first and second gate insulating films 16 and 17 are extended on the above-mentioned lower electrode 2 for charge storage capacitor to respectively form the first and second insulating films for charge storage capacitor. 16a and 17a are formed, a pixel electrode 12 made of a transparent conductive film connected to the drain electrode 11 is further formed thereon, and a protective film 13 is formed on the surfaces of both.
【０００４】従来のマトリックス型表示装置において
は、前述のように、電荷保持容量および薄膜トランジス
タの絶縁膜の異物やピンホールによる短絡不良を低減す
るために、２層に形成されている。しかも、工程の増加
を抑えるため、前述のように、ゲート絶縁膜と電荷保持
容量用絶縁膜はそれぞれ同一材料で同一厚さに形成され
ている。In the conventional matrix type display device, as described above, two layers are formed in order to reduce short-circuit defects due to foreign matter or pinholes in the charge storage capacitor and the insulating film of the thin film transistor. Moreover, in order to suppress an increase in the number of steps, as described above, the gate insulating film and the charge retention capacitor insulating film are formed of the same material and have the same thickness.
【０００５】つぎに、その製造工程を述べる。まず、透
明絶縁性基板１上にゲート電極３ａ、ゲート電極線３お
よび電荷保持容量用下部電極２を形成したのち、１層目
の第１のゲート絶縁膜16と１層目の第１の電荷保持容量
用絶縁膜16ａとなる第１の絶縁膜を形成し、さらに２層
目の第２のゲート絶縁膜17および２層目の第２の電荷保
持容量用絶縁膜17ａとなる第２の絶縁膜を形成する。さ
らに、ノンドープアモルファスシリコン層７、リンドー
プアモルファスシリコン層９を成膜し、アイランド18に
パターニングする。そののち、画素電極12を形成し、ソ
ース電極10ａとソース電極線10およびドレイン電極11を
形成し、チャネル上の不要なリンドープアモルファスシ
リコン層９を除去し、保護膜13を形成してマトリックス
型表示装置が作製される。Next, the manufacturing process will be described. First, after forming the gate electrode 3a, the gate electrode line 3 and the lower electrode 2 for the charge storage capacitor on the transparent insulating substrate 1, the first gate insulating film 16 of the first layer and the first charge of the first layer are formed. A first insulating film to be the storage capacitor insulating film 16a is formed, and a second insulating film to be the second layer second gate insulating film 17 and the second layer second charge retaining capacitor insulating film 17a is formed. Form a film. Further, a non-doped amorphous silicon layer 7 and a phosphorus-doped amorphous silicon layer 9 are formed and patterned on the island 18. After that, the pixel electrode 12 is formed, the source electrode 10a, the source electrode line 10 and the drain electrode 11 are formed, the unnecessary phosphorus-doped amorphous silicon layer 9 on the channel is removed, and the protective film 13 is formed to form a matrix type. A display device is manufactured.
【０００６】[0006]
【発明が解決しようとする課題】従来のマトリックス型
表示装置は、電荷保持容量および薄膜トランジスタの絶
縁膜の不良による短絡欠陥を低減すると共に、製造工程
の低減のために、ゲート絶縁膜と電荷保持容量用絶縁膜
を同一の絶縁膜で形成して兼用し、その絶縁膜は２層で
形成されている。しかし、このように絶縁膜をすべて兼
用にすると材料および膜厚をゲート絶縁膜および電荷保
持容量用絶縁膜の要求する仕様をすべて満足するように
最適化することは困難であり、短絡欠陥の低減対策には
不充分である。すなわち、ゲート絶縁膜としては、良好
な薄膜トランジスタの特性および短絡欠陥不良の低減が
えられること、電荷保持容量用絶縁膜としては、面積低
減のための高誘電率および短絡欠陥低減のための高耐圧
が要求されることの両方の要求をすべて満足する絶縁膜
を選択することは困難であるという問題がある。In the conventional matrix type display device, short-circuit defects due to defects in the charge holding capacitor and the insulating film of the thin film transistor are reduced, and in order to reduce the manufacturing process, the gate insulating film and the charge holding capacitor are reduced. The insulating film for use is formed of the same insulating film and is also used, and the insulating film is formed of two layers. However, it is difficult to optimize the material and film thickness so as to satisfy all the specifications required for the gate insulating film and the insulating film for the charge storage capacitor when the insulating film is also used in this way, and it is possible to reduce short circuit defects. Insufficient countermeasures. That is, as the gate insulating film, good characteristics of the thin film transistor and reduction of short-circuit defects can be obtained, and as the insulating film for the charge storage capacitor, high dielectric constant for area reduction and high breakdown voltage for short-circuit defect reduction. However, there is a problem that it is difficult to select an insulating film that satisfies both of these requirements.
【０００７】本発明は、前記のような従来の問題を解決
するためになされたもので、工程の増加を抑えながら、
ゲート絶縁膜および（または）電荷保持容量用絶縁膜を
多層化し、しかもそれぞれの絶縁膜に最適化が可能な、
高歩留で表示特性が高品質のマトリックス型表示装置を
実現することを目的としている。The present invention has been made to solve the above-mentioned conventional problems, and suppresses an increase in the number of steps,
The gate insulating film and / or the insulating film for charge storage capacitor can be multi-layered and optimized for each insulating film.
It is an object of the present invention to realize a matrix type display device having high yield and high display characteristics.
【０００８】[0008]
【課題を解決するための手段】本発明に係るマトリック
ス型表示装置は、透明の絶縁性基板上に形成されたゲー
ト電極、該ゲート電極上に形成された２以上のゲート絶
縁膜、該２以上のゲート絶縁膜上に半導体層を介して形
成されたソース電極およびドレイン電極からなる薄膜ト
ランジスタと、該薄膜トランジスタの前記ドレイン電極
に接続された透明電極からなる画素電極を有し、前記画
素電極の少なくとも一部が２以上の電荷保持容量用絶縁
膜を介して電荷保持容量用電極と重畳するように構成さ
れる電荷保持容量部とがマトリックス状に並設されてい
るマトリックス型表示装置であって、前記ゲート絶縁膜
の少なくとも１の絶縁膜と前記電荷保持容量用絶縁膜の
少なくとも１の絶縁膜が同一材料で兼用して形成され、
前記ゲート絶縁膜の少なくとも１の絶縁膜と前記電荷保
持容量用絶縁膜の少なくとも１の絶縁膜はそれぞれ専用
の絶縁膜で形成されている。A matrix type display device according to the present invention comprises a gate electrode formed on a transparent insulating substrate, two or more gate insulating films formed on the gate electrode, and two or more gate insulating films. A thin film transistor including a source electrode and a drain electrode formed on the gate insulating film via a semiconductor layer, and a pixel electrode including a transparent electrode connected to the drain electrode of the thin film transistor, and at least one of the pixel electrodes. A matrix-type display device, in which charge storage capacitors are arranged side by side in a matrix so as to overlap the charge storage electrodes through two or more insulating films for charge storage capacitors. At least one insulating film of the gate insulating film and at least one insulating film of the charge retaining capacitor insulating film are formed of the same material
At least one insulating film of the gate insulating film and at least one insulating film of the charge retaining capacitor insulating film are respectively formed of dedicated insulating films.
【０００９】また、請求項２記載の発明に係るマトリッ
クス型表示装置は、ゲート絶縁膜と電荷保持容量用絶縁
膜がそれぞれ２層で形成され、２層目の第２の電荷保持
容量用絶縁膜と１層目の第１のゲート絶縁膜とが兼用し
て形成され、１層目の第１の電荷保持容量用絶縁膜と２
層目の第２のゲート絶縁膜は専用絶縁膜として形成され
ている。According to a second aspect of the present invention, in the matrix type display device, the gate insulating film and the charge retaining capacitance insulating film are each formed of two layers, and the second charge retaining capacitance insulating film is the second layer. And the first gate insulating film of the first layer are also formed, and the first charge insulating capacitor film of the first layer and the second gate insulating film of the second layer are formed.
The second gate insulating film of the layer is formed as a dedicated insulating film.
【００１０】さらに、請求項３記載の発明に係るマトリ
ックス型表示装置は、電荷保持容量用絶縁膜またはゲー
ト絶縁膜のいずれか一方は、単層の絶縁膜で、他方は、
多層の絶縁膜で形成され、単層の絶縁膜は多層の絶縁膜
の１層と同一材料で兼用して形成されている。Further, in the matrix type display device according to a third aspect of the present invention, one of the charge retention capacitor insulating film and the gate insulating film is a single-layer insulating film, and the other is
The insulating film is formed of a multi-layer insulating film, and the single-layer insulating film is formed of the same material as that of one layer of the multi-layer insulating film.
【００１１】[0011]
【作用】前記のように構成されるマトリックス型表示装
置は、ゲート絶縁膜および電荷保持容量用絶縁膜がそれ
ぞれ同一膜で形成された兼用絶縁膜と各々の絶縁膜に適
した専用絶縁膜とで形成されているため、絶縁膜の組合
せが自由であり、ゲート絶縁膜として最適な多層の絶縁
膜および電荷保持容量用絶縁膜として最適な多層の絶縁
膜とすることができる。しかも、一部絶縁膜は両者で同
一材料、同一厚さに形成されて兼用しているため、工程
の増加は最小限に抑えることができる。したがって、電
荷保持容量用絶縁膜およびゲート絶縁膜の特性を満足
し、かつ短絡欠陥低減に必要な多層の絶縁膜を工程の増
加を抑えて形成でき、低コストで、高歩留かつ高品質の
マトリックス型表示装置がえられる。In the matrix type display device having the above-described structure, the gate insulating film and the charge retaining capacitor insulating film are formed of the same film, and the dual-purpose insulating film is formed as a dedicated insulating film. Since it is formed, the combination of insulating films is free, and it is possible to obtain the optimum multilayer insulating film as the gate insulating film and the optimum multilayer insulating film as the charge holding capacitor insulating film. In addition, since the partial insulating film is formed of the same material and has the same thickness for both of them, the number of steps can be minimized. Therefore, it is possible to form a multi-layered insulating film that satisfies the characteristics of the charge retention capacitor insulating film and the gate insulating film and that is necessary for reducing short-circuit defects, while suppressing an increase in the number of steps, and at low cost, with high yield and high quality. A matrix type display device can be obtained.
【００１２】[0012]
【実施例】つぎに、本発明の一実施例を図１および図２
を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to.
【００１３】本発明のマトリックス型表示装置の薄膜ト
ランジスタ部は、透明絶縁性基板１上にゲート電極３ａ
およびゲート電極線３が形成され、その上に第１のゲー
ト絶縁膜５ａとしての兼用絶縁膜５、第２のゲート絶縁
膜としてのゲート絶縁用専用絶縁膜６、半導体層７、９
が順次形成され、ソース電極10ａ、ソース電極線10およ
びドレイン電極11が形成されている。また電荷保持容量
部は薄膜トランジスタ部とは別の場所で、透明絶縁性基
板１上に電荷保持容量用下部電極２が形成され、その上
に第１の電荷保持容量用絶縁膜として、電荷保持容量用
専用絶縁膜４、第２の電荷保持容量用絶縁膜５ｂとして
の兼用絶縁膜５、画素電極１２が順次形成され、兼用絶
縁膜５は薄膜トランジスタ部のゲート絶縁膜と同時に形
成され、薄膜トランジスタ部では第１の絶縁膜として、
電荷保持容量部では第２の電荷保持容量用絶縁膜として
用いられる。The thin film transistor portion of the matrix type display device of the present invention comprises a gate electrode 3a on a transparent insulating substrate 1.
And the gate electrode line 3 are formed, and the dual-purpose insulating film 5 serving as the first gate insulating film 5a, the gate insulating dedicated insulating film 6 serving as the second gate insulating film, and the semiconductor layers 7 and 9 are formed thereon.
Are sequentially formed, and a source electrode 10a, a source electrode line 10 and a drain electrode 11 are formed. In addition, the charge storage capacitor portion is formed in a place different from the thin film transistor portion, and the charge storage capacitor lower electrode 2 is formed on the transparent insulating substrate 1, and the charge storage capacitor lower electrode 2 is formed thereon as a charge storage capacitor insulating film. The dedicated insulating film 4, the dual-purpose insulating film 5 as the second charge storage capacitor insulating film 5b, and the pixel electrode 12 are sequentially formed. The dual-purpose insulating film 5 is formed at the same time as the gate insulating film of the thin film transistor portion. As the first insulating film,
In the charge storage capacitor portion, it is used as a second charge storage capacitor insulating film.
【００１４】前記絶縁膜としては、Ｓｉ、Ａｌ、Ｔａ、
Ｔｉ、Ｚｒなどの酸化物（たとえばＳｉＯ2、Ｔａ2Ｏ5
など）やチッ化物（たとえばＳｉ3Ｎ4など）、あるいは
それら金属の合金の酸化物（たとえばＴａＭｏ合金の酸
化物など）または３元系酸化物（たとえばＢａＴｉＯ3
、ＬｉＴａＯ3 など）などからつくられたものがあ
げられる。As the insulating film, Si, Al, Ta,
Oxides such as Ti and Zr (eg, SiO 2 , Ta 2 O 5
Etc.), nitrides (eg Si 3 N 4 etc.), or oxides of alloys of these metals (eg oxides of TaMo alloys) or ternary oxides (eg BaTiO 3).
, LiTaO 3, etc.) and the like.
【００１５】本発明では、マトリックス型表示装置の薄
膜トランジスタ部と電荷保持容量部にそれぞれ複数層で
形成される絶縁膜の一部は共通に形成され、他の膜にそ
れぞれの特性を満たすように専用膜が使用されることに
より、高特性で製造工数の少ないマトリックス型表示装
置をうるもので、他の電極や透明絶縁性基板などは従来
用いられているものを同様に使用できる。また、絶縁膜
の形成法も従来から使用されているプラズマＣＶＤ法、
スパッタ法、ＥＢ蒸着法などにより形成できる。According to the present invention, a part of the insulating film formed of a plurality of layers is commonly formed in the thin film transistor part and the charge storage capacitor part of the matrix type display device, and the other films are dedicated to satisfy their respective characteristics. By using the film, it is possible to obtain a matrix type display device having high characteristics and a small number of manufacturing steps, and other electrodes, transparent insulating substrates and the like which have been conventionally used can be used similarly. In addition, the insulating film forming method is the plasma CVD method which has been used conventionally,
It can be formed by a sputtering method, an EB vapor deposition method, or the like.
【００１６】前述の説明では薄膜トランジスタ部と電荷
保持容量部の絶縁膜をそれぞれ２層の例で説明したが、
一方の特性を満たす絶縁膜を兼用絶縁膜として１層で使
用し、他方の絶縁膜を兼用絶縁膜と専用絶縁膜を用いた
複数層としてもよく、また３層以上に形成することもで
きる。このばあいも、兼用絶縁膜と専用絶縁膜を使用す
ることにより、本発明の特徴があらわれる。In the above description, the thin film transistor section and the charge holding capacitor section each have two layers of insulating films.
An insulating film satisfying one of the characteristics may be used as a single-purpose insulating film in one layer, and the other insulating film may be a plurality of layers including a dual-purpose insulating film and a dedicated insulating film, or may be formed in three or more layers. Also in this case, the features of the present invention are exhibited by using the dual-purpose insulating film and the dedicated insulating film.
【００１７】また、前記複数のゲート絶縁膜と前記複数
の電荷保持容量用絶縁膜の専用絶縁膜のすべてが異なる
材料で形成されれば、耐薬品、エッチングガスに対する
選択性の点から好ましい。Further, it is preferable that all of the plurality of gate insulating films and the dedicated insulating films of the plurality of charge holding capacitor insulating films are made of different materials from the viewpoint of chemical resistance and selectivity to etching gas.
【００１８】［実施例１］つぎに、本実施例のマトリッ
クス型表示装置の具体的な製法について説明する。[Embodiment 1] Next, a specific method for manufacturing the matrix type display device of this embodiment will be described.
【００１９】まず、透明絶縁性基板１上にＣｒなどをス
パッタ法などにより成膜する。つぎに、フォトリソグラ
フィによりゲート電極３ａとそれらを連結するゲート電
極線３および電荷保持容量用の下部電極２のパターンを
成形する。つぎに電荷保持容量の専用絶縁膜４としてＴ
ａ2Ｏ5などを形成し、ゲート電極上をフォトリソグラフ
ィおよびエッチングにより除去する。さらに、ゲート絶
縁膜５ａと電荷保持容量用絶縁膜５ｂの兼用絶縁膜５と
なるＳｉ3Ｎ4などの絶縁膜をプラズマＣＶＤ法などを用
いて成膜する。つぎに、ＩＴＯなどの透明電極材料を成
膜し、電荷保持容量用下部電極２と一部を重畳させて画
素電極12を形成する。この時点で、電荷保持容量が専用
絶縁膜４と兼用絶縁膜５の２層のそれぞれ第１および第
２の絶縁膜で形成される。さらに、専用のゲート絶縁膜
となる第２のゲート絶縁膜６をＳｉＯ2などで形成し、
連続的にノンドープアモルファスシリコン層７およびチ
ャネル保護膜８を成膜する。この時点で、兼用絶縁膜５
とゲート絶縁専用絶縁膜６からなる第１および第２のゲ
ート絶縁膜が形成される。つぎに、チャネル保護膜をパ
ターニングし、リンドープアモルファスシリコン層９を
成膜する。さらに、画素電極12とドレイン電極11を接続
するための開口14部をパターニングで形成し、ソース電
極10ａとそれらを連続するソース電極線10およびドレイ
ン電極11となるＣｒおよびＡｌを連続的に成膜し、パタ
ーニングする。つぎに、チャネル上および画素電極12上
のアモルファスシリコン層をエッチングして、保護膜13
をその上に形成して、薄膜トランジスタ（ＴＦＴ）基板
が完成する。First, a film of Cr or the like is formed on the transparent insulating substrate 1 by a sputtering method or the like. Next, the pattern of the gate electrode 3a, the gate electrode line 3 connecting them and the lower electrode 2 for the charge storage capacitor is formed by photolithography. Next, as the dedicated insulating film 4 for the charge storage capacitor, T
Then, a 2 O 5 or the like is formed, and the gate electrode is removed by photolithography and etching. Further, an insulating film such as Si 3 N 4 which will serve as the insulating film 5 serving as both the gate insulating film 5a and the charge storage capacitor insulating film 5b is formed by using the plasma CVD method or the like. Next, a transparent electrode material such as ITO is deposited, and the pixel electrode 12 is formed by partially overlapping the lower electrode 2 for charge storage capacitor. At this point, the charge storage capacitor is formed by the two layers of the dedicated insulating film 4 and the dual-purpose insulating film 5, which are the first and second insulating films, respectively. Further, a second gate insulating film 6 serving as a dedicated gate insulating film is formed of SiO 2 or the like,
The non-doped amorphous silicon layer 7 and the channel protection film 8 are continuously formed. At this point, the dual-purpose insulating film 5
The first and second gate insulating films composed of the gate insulating film 6 for gate insulating are formed. Next, the channel protective film is patterned to form the phosphorus-doped amorphous silicon layer 9. Further, the opening 14 for connecting the pixel electrode 12 and the drain electrode 11 is formed by patterning, and the source electrode 10a and the source and source electrode lines 10 and the Cr and Al to be the drain electrode 11 which are continuous with the source electrode 10a are continuously formed. Patterning. Next, the amorphous silicon layer on the channel and the pixel electrode 12 is etched to remove the protective film 13
Are formed thereon to complete a thin film transistor (TFT) substrate.
【００２０】本実施例では、電荷保持容量用絶縁膜は２
層の絶縁膜で形成され、第１の絶縁膜は専用絶縁膜から
なり、第２の絶縁膜は第１のゲート絶縁膜と同一の材料
で形成される２層構造となる。また、第１のゲート絶縁
膜は下層部は電荷保持容量の絶縁膜との兼用絶縁膜であ
り、かつアモルファスシリコンと界面を形成する第２の
絶縁膜の２層絶縁膜になる。したがって、成膜工程を一
工程増加するのみで、ゲート絶縁膜および電荷保持容量
用の絶縁膜をそれぞれ異なる膜構成で２層化することが
でき、それぞれの絶縁膜に最適な構成の絶縁膜の２層化
が可能になり、２層化による歩留向上と絶縁膜の最適化
による表示特性の向上を達成できる。In this embodiment, the charge retention capacitor insulating film is 2
The first insulating film is formed of a layered insulating film, the first insulating film is a dedicated insulating film, and the second insulating film is a two-layer structure formed of the same material as the first gate insulating film. The lower portion of the first gate insulating film is also an insulating film that also serves as an insulating film of the charge storage capacitor, and is a two-layer insulating film of a second insulating film that forms an interface with amorphous silicon. Therefore, the gate insulating film and the charge retention capacitor insulating film can be formed into two layers with different film configurations by only increasing the number of film forming steps, and the insulating film having the optimal configuration for each insulating film can be formed. The two-layer structure is possible, and the yield ratio can be improved by the two-layer structure and the display characteristics can be improved by optimizing the insulating film.
【００２１】また、この例では、第１のゲート絶縁膜と
第２の電荷保持容量用絶縁膜を同一材料で兼用絶縁膜と
して形成しているため、ゲート絶縁用の専用絶縁膜は電
荷保持容量部では画素電極の上に形成することができ、
とくにパターニングする必要なく形成できる。Further, in this example, since the first gate insulating film and the second charge retaining capacitor insulating film are formed of the same material as the dual purpose insulating film, the gate insulating dedicated insulating film is the charge retaining capacitor. Part can be formed on the pixel electrode,
It can be formed without any particular patterning.
【００２２】［実施例２］図３および図４に、本発明の
他の実施例の構造を前述の実施例と同様に示す。この実
施例では電荷保持容量用絶縁膜を専用絶縁膜と、ゲート
絶縁膜と同じ材料で形成した兼用絶縁膜５とで２層化
し、ゲート絶縁膜は、単層の絶縁膜で形成したばあいの
実施例を示す。絶縁膜などの材料および形成法は前述と
同様である。図面を参照しながらこの実施例の製法につ
いて、説明する。[Embodiment 2] FIGS. 3 and 4 show the structure of another embodiment of the present invention similarly to the above-mentioned embodiment. In this embodiment, the charge retention capacitor insulating film is made into a two-layer structure by a dedicated insulating film and a dual-purpose insulating film 5 made of the same material as the gate insulating film, and the gate insulating film is made of a single-layer insulating film. An example is shown. The material of the insulating film and the forming method are the same as described above. The manufacturing method of this embodiment will be described with reference to the drawings.
【００２３】まず、透明絶縁性基板１上に電荷保持容量
用下部電極２を形成し、つぎに電荷保持容量用専用絶縁
膜４を成膜し、ゲート電極線３と上記電荷保持容量用下
部電極２とを接続するための開口部15を形成し、ゲート
電極３ａおよびゲート電極線３を形成する。さらに、電
荷保持容量用絶縁膜５ｂと兼用するゲート絶縁膜５ａお
よびノンドープアモルファスシリコン膜７およびリンド
ープアモアルファスシリコン膜９を形成し、アモルファ
スシリコンのアイランド18を形成する。つぎに、画素電
極12を形成したのち、ＣｒおよびＡｌなどを成膜し、ソ
ース電極10ａとそれらを連結するソース電極線10および
ドレイン電極11を形成し、チャネル部上の不要なリンド
ープアモルファスシリコン膜を除去し、最後に保護膜13
を形成する。First, the lower electrode 2 for charge storage capacitor is formed on the transparent insulating substrate 1, then the insulating film 4 for charge storage capacitor is formed, and the gate electrode line 3 and the lower electrode for charge storage capacitor are formed. An opening 15 for connecting with 2 is formed, and a gate electrode 3a and a gate electrode line 3 are formed. Further, the gate insulating film 5a which also serves as the charge retaining capacitance insulating film 5b, the non-doped amorphous silicon film 7 and the phosphorus-doped ammo-alpha silicon film 9 are formed, and the amorphous silicon island 18 is formed. Next, after the pixel electrode 12 is formed, Cr and Al are deposited to form the source electrode 10a and the source electrode line 10 and the drain electrode 11 that connect them, and unnecessary phosphorus-doped amorphous silicon on the channel portion is formed. Remove the film and finally the protective film 13
To form.
【００２４】[0024]
【発明の効果】以上のように、本発明によれば、ゲート
絶縁膜および電荷保持容量用絶縁膜のそれぞれ一部が兼
用絶縁膜として同じ材料で形成され、残りが専用絶縁膜
で形成された多層の絶縁膜とすることにより、製造工程
の増加を最小限に抑えながら、多層化により短絡欠陥を
低減でき、歩留が向上する。また、ゲート絶縁膜と電荷
保持容量用絶縁膜を異なる膜構成にすることが可能とな
るので、それぞれに最適化が可能になり、表示特性が向
上する。As described above, according to the present invention, a part of each of the gate insulating film and the charge retention capacitor insulating film is formed of the same material as the dual-purpose insulating film, and the rest is formed of the dedicated insulating film. By using a multi-layer insulating film, short-circuit defects can be reduced and the yield can be improved by minimizing the increase in the number of manufacturing processes. In addition, since the gate insulating film and the charge storage capacitor insulating film can have different film configurations, optimization can be performed for each and the display characteristics are improved.
【図１】本発明の一実施例であるマトリックス型表示装
置の画素部分の構成断面図（図２のＡ−Ａ断面図）を示
す。FIG. 1 is a structural cross-sectional view (a cross-sectional view taken along line AA in FIG. 2) of a pixel portion of a matrix type display device which is an embodiment of the present invention.
【図２】本発明の一実施例によるマトリックス型表示装
置の画素部分の平面図を示す。FIG. 2 is a plan view of a pixel portion of a matrix type display device according to an exemplary embodiment of the present invention.
【図３】本発明の第２の実施例によるマトリックス型表
示装置の画素部分の構成断面図（図４のＢ−Ｂ断面図）
を示す。FIG. 3 is a sectional view showing a pixel portion of a matrix type display device according to a second embodiment of the present invention (sectional view taken along line BB in FIG. 4).
Indicates.
【図４】本発明の第２の実施例によるマトリックス型表
示装置の画素部分の平面図を示す。FIG. 4 is a plan view of a pixel portion of a matrix type display device according to a second embodiment of the present invention.
【図５】従来のマトリックス型表示装置の画素部分の構
成断面図（図６のＣ−Ｃ断面図）を示す。FIG. 5 is a cross-sectional view of a pixel portion of a conventional matrix-type display device (cross-sectional view taken along the line CC in FIG. 6).
【図６】従来のマトリックス型表示装置の画素部分の平
面図を示す。FIG. 6 is a plan view of a pixel portion of a conventional matrix type display device.
１ 透明絶縁性基板 ２ 電荷保持容量用下部電極 ３ ゲート電極線 ３ａ ゲート電極 ４ 電荷保持容量用専用絶縁膜 ５ 兼用絶縁膜 ６ ゲート絶縁用専用絶縁膜 10 ソース電極線 10ａ ソース電極 11 ドレイン電極 12 画素電極 1 Transparent Insulating Substrate 2 Lower Electrode for Charge Retaining Capacitor 3 Gate Electrode Line 3a Gate Electrode 4 Dedicated Insulating Film for Charge Retaining Capacitor 5 Combined Insulating Film 6 Dedicated Insulating Film for Gate Insulation 10 Source Electrode Line 10a Source Electrode 11 Drain Electrode 12 Pixel electrode
Claims (3)
電極、該ゲート電極上に形成された２以上のゲート絶縁
膜、該２以上のゲート絶縁膜上に半導体層を介して形成
されたソース電極およびドレイン電極からなる薄膜トラ
ンジスタと、該薄膜トランジスタの前記ドレイン電極に
接続された透明電極からなる画素電極を有し、前記画素
電極の少なくとも一部が２以上の電荷保持容量用絶縁膜
を介して電荷保持容量用電極と重畳するように構成され
る電荷保持容量部とがマトリックス状に並設されている
マトリックス型表示装置であって、前記ゲート絶縁膜の
少なくとも１の絶縁膜と前記電荷保持容量用絶縁膜の少
なくとも１の絶縁膜が同一材料で兼用して形成され、前
記ゲート絶縁膜の少なくとも１の絶縁膜と前記電荷保持
容量用絶縁膜の少なくとも１の絶縁膜はそれぞれ専用の
絶縁膜で形成されることを特徴とするマトリックス型表
示装置。1. A gate electrode formed on a transparent insulating substrate, two or more gate insulating films formed on the gate electrode, and a semiconductor layer formed on the two or more gate insulating films via a semiconductor layer. A thin film transistor including a source electrode and a drain electrode and a pixel electrode including a transparent electrode connected to the drain electrode of the thin film transistor are provided, and at least a part of the pixel electrode is provided with two or more insulating films for charge storage capacitors. A matrix-type display device in which a charge-retaining capacitor portion configured to overlap with a charge-retaining capacitor electrode is arranged in a matrix, wherein at least one insulating film of the gate insulating film and the charge-retaining capacitor are provided. At least one insulating film of the gate insulating film is also formed by using the same material, and at least one insulating film of the gate insulating film and the insulating film for the charge holding capacitor are small. A matrix type display device characterized in that at least one insulating film is formed of a dedicated insulating film.
のゲート絶縁膜および第２のゲート絶縁膜が順次形成さ
れたゲート絶縁膜、半導体層およびソース電極とドレイ
ン電極が形成されてなる薄膜トランジスタと、前記透明
絶縁性基板上に電荷保持容量用電極、第１および第２の
電荷保持容量用絶縁膜が順次形成された電荷保持容量用
絶縁膜および前記ドレイン電極に接続された透明電極か
らなる画素電極が形成されてなる電荷保持部とがマトリ
ックス状に並設され、第２の電荷保持容量用絶縁膜と第
１のゲート絶縁膜とが兼用して形成され、第１の電荷保
持容量用絶縁膜と第２のゲート絶縁膜は専用絶縁膜とし
て形成されてなることを特徴とするマトリックス型表示
装置。2. A gate electrode, a first electrode on a transparent insulating substrate.
A gate insulating film in which a gate insulating film and a second gate insulating film are sequentially formed, a semiconductor layer, a thin film transistor in which a source electrode and a drain electrode are formed, a charge storage capacitor electrode on the transparent insulating substrate, The charge retaining capacitor insulating film in which the first and second charge retaining capacitor insulating films are sequentially formed and the charge retaining portion in which the pixel electrode including the transparent electrode connected to the drain electrode is formed are arranged in a matrix. The first charge insulating capacitor insulating film and the second gate insulating film are formed as a dedicated insulating film. A matrix type display device characterized by the following.
電極、該ゲート電極上に形成された１または２以上のゲ
ート絶縁膜、該ゲート絶縁膜上に半導体層を介して形成
されたソース電極およびドレイン電極からなる薄膜トラ
ンジスタと、該薄膜トランジスタの前記ドレイン電極に
接続された透明電極からなる画素電極を有し、前記画素
電極の少なくとも一部が１または２以上の電荷保持容量
用絶縁膜を介して電荷保持容量用電極と重畳するように
構成される電荷保持容量部とがマトリックス状に並設さ
れているマトリックス型表示装置であって、前記ゲート
絶縁膜と前記電荷保持容量用絶縁膜のいずれか一方は、
他方の１の絶縁膜と兼用する単一の絶縁膜で形成され、
他方は、前記兼用の絶縁膜と他の１以上の専用絶縁膜と
で構成されることを特徴とするマトリックス型表示装
置。3. A gate electrode formed on a transparent insulating substrate, one or more gate insulating films formed on the gate electrode, and a source formed on the gate insulating film via a semiconductor layer. A thin film transistor including an electrode and a drain electrode; and a pixel electrode including a transparent electrode connected to the drain electrode of the thin film transistor, wherein at least a part of the pixel electrode is provided with one or more insulating films for charge storage capacitors. A matrix type display device in which a charge storage capacitor portion configured to overlap with a charge storage capacitor electrode is arranged side by side in a matrix, wherein either the gate insulating film or the charge storage capacitor insulating film is provided. One is
It is formed of a single insulating film that doubles as the other one insulating film,
The other is a matrix type display device characterized by comprising the above-mentioned double-sided insulating film and one or more other dedicated insulating films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11472192A JP3031056B2 (en) | 1992-05-07 | 1992-05-07 | Matrix display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11472192A JP3031056B2 (en) | 1992-05-07 | 1992-05-07 | Matrix display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05313188A true JPH05313188A (en) | 1993-11-26 |
| JP3031056B2 JP3031056B2 (en) | 2000-04-10 |
Family
ID=14644961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11472192A Expired - Lifetime JP3031056B2 (en) | 1992-05-07 | 1992-05-07 | Matrix display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3031056B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433367C (en) * | 2005-09-23 | 2008-11-12 | 北京京东方光电科技有限公司 | Thinfilm transistor device for reducing leaping voltage |
-
1992
- 1992-05-07 JP JP11472192A patent/JP3031056B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433367C (en) * | 2005-09-23 | 2008-11-12 | 北京京东方光电科技有限公司 | Thinfilm transistor device for reducing leaping voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3031056B2 (en) | 2000-04-10 |
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