CN100433367C - Thinfilm transistor device for reducing leaping voltage - Google Patents

Abstract

The thin film transistor device includes following parts: a transparent glass base plate; gate electrode; insulating layer of gate electrode for partitioning scan line of gate electrode from scan line of source electrode; active layer, doping layer; source/drain electrodes; passivation layer for partitioning scan line of source electrode from transparent pixel electrode. Gate insulating layer under the active layer includes three layers of insulating medium. Dielectric constant of middle insulating-film is lower than Dielectric constants of insulating-film at upper layer and insulating-film at lower layer. Thus, the device possesses lower leaping voltage so as to restrain flicker and crosstalk on liquid crystal display of using the thin film transistor as well as improve quality of displayed images.

Description

A kind of film transistor device that reduces leaping voltage

Technical field

This patent is the thin-film transistor about a kind of panel of LCD, particularly reduces the structure of leaping voltage by the control parasitic capacitance, belongs to field of liquid crystal.

Background technology

Since nearly ten years, LCD has attracted to come more the more concern as a kind of flat panel display.It has the little and portable characteristics of volume, compares with other flat panel display (showing as plasma) with traditional cathode ray tube, and the power consumption of LCD is less.Particularly the TFT-LCD device is widely used in office equipment and family's imaging equipment.The TFT-LCD device is controlled each pixel by thin-film transistor and is obtained different driving voltages, thereby realizes the demonstration of meticulous picture.

Fig. 1 represents in a kind of TFT-LCD device of prior art the cross section of thin-film transistor in the single pixel.Common manufacturing process is:

At first the method with magnetron sputtering deposits the layer of metal film on the glass 1 that cleaned, as the gate electrode 2 of scan line.Figure conversion and etching technics by optical mask have formed the required scan line of thin-film transistor display panel.Next on gate electrode 2, deposit one deck grid electrode insulating layer 3 (as silicon nitride), layer of semiconductor thin layer 4 (as amorphous silicon) and the low-resistance semiconductor lamella 5 of one deck (as the n+ doped amorphous silicon) in order.Form island structure by photoetching process then.Next on transparency carrier, deposit layer of metal film (as molybdenum, aluminium, alumel etc.), as data wire and source-drain electrode.Form source electrode 6 and drain electrode 7 by photoetching process.Next on metal electrode, deposit one deck passivation layer 8 to shield.Utilize photoetching process the part drain electrode to be exposed, deposit layer of transparent pixel electrode 9 (as tin indium oxide) again, make it to contact with drain electrode 8 in the passivation layer perforate.Utilize photoetching process to form the pattern of pixel electrode at last.

Yet the grid electrode insulating layer has also formed parasitic capacitance between grid and source electrode when cutting off grid metal and amorphous silicon.This parasitic capacitance reduces the operating load of source-drain electrode, causes so-called leaping voltage (Kick-back).

As shown in Figure 3, be expressly understood the generation of leaping voltage and the effect of parasitic capacitance more.When coming the definition of data line with mask, misalignment may take place in the technical process, cause overlapping between gate electrode 2 and the source electrode 6.The parasitic capacitance 14 of Xing Chenging can be described with the equivalent electric circuit Cgs among Fig. 3 thus.On thin-film transistor 13, apply certain Vg, the source electrode of thin-film transistor and drain electrode conducting.The signal of data wire can be sent on liquid crystal layer electric capacity 16 (Clc) and the storage capacitance 15 (Cst).After finishing a scan period, remove the voltage Vg on the scan line 11, make thin-film transistor 13 be in cut-off state.Liquid crystal layer electric capacity 16 relies on storage capacitance 15 to keep operating load.Available Δ Vp of signal voltage Vsignal variable quantity-leaping voltage (kick-back voltage) that parasitic capacitance produces such as formula 1 are described:

$\mathrm{\ΔVp}=\frac{\mathrm{Cgs}}{\mathrm{Cgs}+\mathrm{Cst}+\mathrm{Clc}}(\mathrm{Vgh}-\mathrm{Vgl})$ Formula 1

Wherein, Vgh is the cut-in voltage of scan line 11 and gate electrode 2; Vgl is the voltage of closing of scan line 11 and gate electrode 2.

According to formula 1, leaping voltage Δ Vp is the function that changes with Cgs, and Cgs is more little, and Δ Vp is just more little.

As previously mentioned, Cgs that overlapping between gate electrode 2 and the source electrode 6 produces and the existence of Δ Vp cause the reduction of picture quality, as glimmering, crosstalk etc.

Therefore, for the research staff who is engaged in the TFT-LCD association area, the leaping voltage that reduces thin-film transistor is the important topic of thin film transistor (TFT) array design to improve its feed-in characteristic.

Summary of the invention

The objective of the invention is to reduce leaping voltage Δ Vp, thereby overcome image flicker, crosstalk etc., improved the display quality of TFT-LCD by the parasitic capacitance that reduces film transistor device.

Before introducing the present invention at first the brief description dielectric to the influence of electric capacity.

The size of parasitic capacitance Cgs14 can be described by formula 2:

$C=\mathrm{\&epsiv;}\frac{\mathrm{<figure-callout\; id="2"\; label="A\; d\; Formula"\; filenames="C20051010329900071.png"\; state="\{\{state\}\}">A</figure-callout>}}{d}$ Formula 2

Wherein ε is the dielectric constant of dielectric, and A is an electrode area, and d is an electrode spacing.

Can infer that by formula 2 more little dielectric constant causes more little capacitance.

The object of the present invention is achieved like this:

A kind of film transistor device that reduces leaping voltage, it comprises a transparent glass substrate; Gate electrode; The grid electrode insulating layer that cuts off gate electrode scan line and source electrode scan line; Active layer; Doped layer; Source/drain electrode; The passivation layer of partition source electrode scan line and transparent pixels electrode, wherein the grid electrode insulating layer under the active layer comprises three-layer insulated film, and the dielectric constant of the insulation film in the middle of being positioned at is lower than the dielectric constant of the upper and lower insulation film.The dielectric constant of the intermediate insulation film of grid electrode insulating layer is lower than 6.The intermediate insulation film of grid electrode insulating layer can also be a multilayer structure.

Guaranteeing that film transistor device has under the prerequisite of excellent dielectric properties like this, grid source parasitic capacitance is equivalent to three capacitances in series, has reduced the dielectric constant of grid electrode insulating layer, thereby has reduced parasitic capacitance Cgs, has reduced leaping voltage.

The present invention compares with the manufacturing technology of original TFT-LCD, does not need to change panel designs, does not also increase the photoetching number of times.Utilized prior art and equipment fully, significantly do not increased process cycle and do not reducing under the situation of production capacity, can reach and improve the picture display quality.

Description of drawings

Fig. 1: the device cross of technology formerly;

Fig. 2: the equivalent circuit diagram of film transistor device;

Fig. 3: TFT-LCD device cross of the present invention.

Identify among the figure: 1, glass substrate; 2, gate electrode; 3, grid electrode insulating layer; 3a, lower floor's insulation film; 3b, mesosphere insulation film; 3c, upper strata insulation film; 4, active layer; 5, doped layer; 6, source electrode; 7, drain electrode; 8, passivation layer; 9, transparent pixels electrode; 10, public electrode; 11, controlling grid scan line; 12, data scanning line; 13, thin-film transistor; 14, grid source parasitic capacitance; 15, storage capacitance; 16, liquid crystal layer electric capacity; 17, liquid crystal layer resistance.

Embodiment

Come the present invention is done more detailed description below in conjunction with drawings and Examples.

As shown in Figure 3, the upper and lower film of the grid electrode insulating layer structure under the film transistor device active layer is a silicon nitride, and intermediate layer film can be silica, silicon oxynitride (SiON), mix the silica (FSG) of fluorine, silica (the carbon-doped SiO of carbon dope ₂), silicon nitride (SiN _x), silicon nitride of other doping of low-k, the organic insulation medium of low-k etc.Because the silicon nitride (N-rich SiNx) of silica of oxygen enrichment (O-rich SiOx) and rich nitrogen, its dielectric constant has identical variation tendency.

Upper silicon nitride (etching barrier layer) the film 3c thickness of the grid electrode insulating layer under this thin film transistor active layer is 10 nanometer to 200 nanometers, lower floor's silicon nitride (boundary layer) film 3a thickness is 10 nanometer to 100 nanometers, and intermediate layer insulating oxide silicon thin film 3b thickness is 100 to 600 nanometers.

SiO more below ₂And Si ₃N ₄The comparison of dielectric constant: ${\mathrm{\&epsiv;}}_{\mathrm{<figure-callout\; id="2"\; label="Si\; O"\; filenames="C20051010329900071.png"\; state="\{\{state\}\}">Si</figure-callout>}{O}_{}{}_2}=4~5$ With ${\mathrm{\&epsiv;}}_{{\mathrm{Si}}_3{N}_4}=6~7$ 。Grid source parasitic capacitance is equivalent to three capacitances in series, because the low-k of foregoing silica adopts silica as dielectric in the electric capacity of same size, than the electric capacity reduction by 50% of silicon nitride like this.In the grid electrode insulating layer, use silica as middle one deck insulation film, can reduce the parasitic capacitance Cgs between gate electrode 2 and the source electrode 6, thereby reduce leaping voltage.

And use the boundary layer of SiNx as amorphous silicon, and lower because rate is brought out in its hole than SiOx, can keep better turn-off current characteristic.The SiNx of bottom cuts off grid metal and source and leaks metal as the corrosion barrier layer of intermediate insulation film, prevents the short circuit between the two.

It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims (5)

1, a kind of film transistor device that reduces leaping voltage comprises: a transparent glass substrate; Gate electrode; The grid electrode insulating layer that cuts off gate electrode scan line and source electrode scan line; Active layer; Doped layer; Source/drain electrode; The passivation layer of partition source electrode scan line and transparent pixels electrode is characterized in that, wherein the grid electrode insulating layer under the active layer comprises three-layer insulated film, and the dielectric constant of the insulation film in the middle of being positioned at is lower than the dielectric constant of the upper and lower insulation film.

2, a kind of film transistor device that reduces leaping voltage according to claim 1, the dielectric constant of the intermediate insulation film of its grid electrode insulating layer is lower than 6.

3, according to the described film transistor device of claim 2, the upper and lower insulation film of its grid electrode insulating layer structure is a silicon nitride, and mesosphere insulation film is silicon dioxide, silicon oxynitride, mix the organic insulation medium of the silicon nitride of other doping of the silica of the silica of fluorine, carbon dope, silicon nitride, low-k, low-k.

4, according to a kind of film transistor device that reduces leaping voltage described in the claim 3, the upper strata insulation film thickness of its grid electrode insulating layer is 10 nanometer to 200 nanometers, lower floor's insulation film thickness is 10 nanometer to 100 nanometers, and the thickness of mesosphere insulation film is 100 to 600 nanometers.

5, a kind of film transistor device that reduces leaping voltage according to claim 1, the intermediate insulation film of its grid electrode insulating layer is a multilayer structure.

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