JPH05312905A - Circuit simulating apparatus - Google Patents

Abstract

PURPOSE:To shorten the required time when a logic circuit is corrected for eliminating a trouble in the result of logic simulation and when logic simulation is performed for recognizing the logic of the logic circuit after the correction. CONSTITUTION:A connection information comparing means 7 compares the connection information of a logic circuit before correction from a simulation- result memory means 6 with the connection information of the logic circuit after the correction and extracts the element and node, which output the signal for indicating the fact that the change in signal for the time after the correction does not agree with the result of simulation of the logic circuit before the correction. A connection-information extracting means 2 extracts the connection information from the comparison information from the connection-information comparing means 7. A test-pattern forming means 3 forms a test pattern based on the comparison information. A simulation executing means 4 executes the simulation based on the information from the test-pattern forming means 3. A simulation-path displaying means 8 displays the simulation executing path. These means are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit simulation device capable of shortening a simulation time of a logic circuit.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing respective means constituting a conventional circuit simulation device and input / output information thereof, in which 1 is a circuit diagram input means for inputting a logic circuit diagram to be simulated. Is the connection information extraction means,
Reference numeral 3 is a test pattern creating means, and 4 is a simulation executing means. The circuit diagram input means 1 inputs a logic circuit diagram to be simulated, the connection information extracting means 2 extracts connection information, and the extracted connection information is input to the simulation executing means 4. A test pattern is separately input to the simulation executing means 4 from the test pattern creating means 3.

The simulation executing means 4 executes a simulation for the connection information according to the input test pattern, and displays the simulation result on the simulation result displaying means 5. If the simulation result is defective, the designer corrects the logic circuit diagram, inputs the corrected logic circuit diagram again from the circuit diagram inputting means 1, and repeats the above process to repeat the logic circuit diagram. The simulation is executed for all the nodes in the figure, the simulation result is displayed on the simulation result display means 5, and the corrected result is confirmed.

[0004]

By the way, in such a conventional circuit simulation apparatus, for example, even if the correction portion is a part, in the simulation after the correction, the simulation is executed for all the nodes on the logic circuit diagram. Therefore, there is a problem that the simulation takes a long time.

The present invention has been made in view of the above circumstances, and its object is to provide an area for outputting a signal in which the change of the signal with respect to time of each node of the logic circuit before and after the correction does not match. The purpose of the present invention is to provide a simulation device that can significantly reduce the simulation time by simulating only.

[0006]

A simulation apparatus according to the present invention comprises a logic circuit diagram inputting means, a connection information extracting means for extracting connection information from the input logic circuit diagram,
In a circuit simulation device including a test pattern creating means and a simulation executing means, means for storing a simulation result for a logic circuit before correction, connection information of the logic circuit before correction stored in the storage means, and correction The test pattern is provided for the correction area obtained by the connection information comparing means, which has connection information comparing means for comparing the connection information of the subsequent logic circuit and extracting the correction area of the logic circuit. It is characterized in that a test pattern is created by the creating means and a simulation is performed on the correction area by the simulation executing means.

[0007]

According to the present invention, by providing the connection information comparing means for comparing the connection information of the logic circuits before and after the correction, the signal at each node of the logic circuit before and after the simulation target area is corrected. It is possible to narrow down the portions where the changes do not match, that is, the correction area and its influence area.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 2 is a block diagram showing each means constituting the circuit simulation apparatus according to the present invention and the input / output information thereof. In the figure, 1 is a circuit diagram input means for inputting a logic circuit diagram to be simulated, and 2 is a circuit diagram input means. Connection information extracting means for extracting the connection information from the logic circuit diagram, 3 is a test pattern creating means, and 4 is a simulation executing means.

The connection information extracting means 2 extracts the connection information from the logic circuit diagram which is the simulation target input through the circuit diagram inputting means 1 and outputs it to the simulation executing means 4. The test pattern is input to the simulation executing means 4 from the test pattern creating means 3, and the simulation executing means 4 executes the simulation for the connection information according to the input test pattern and displays the result on the result displaying means 5. It is stored in the simulation result storage means 6.

If there is any inconvenience in the simulation result, the circuit designer corrects the logic circuit,
The corrected logic circuit diagram is input through the circuit diagram input means 1. The connection information is extracted from the input circuit diagram by the connection information extracting unit 2, and the extracted connection information is output to the connection information comparing unit 7. The connection information comparison unit 7 compares the connection information of the logic circuit before correction read from the simulation result storage unit 6 with the connection information after correction input from the connection information extraction unit 2, and deletes the connection information common to both. Then, the remaining connection information, that is, the comparison processing information is output to the connection information extracting means 2 and the test pattern creating means 3.
The connection information extraction means 2 extracts connection information from the comparison processing information and outputs it to the simulation execution means 4 and the simulation execution path display means 8.

Further, the test pattern creating means 3 creates a new test pattern based on the comparison processing information input from the connection information comparing means 7 and outputs it to the simulation executing means 4. The simulation executing means 4 executes a simulation based on the connection information regarding the corrected logic circuit input from the connection information extracting means 2 and the test pattern for the comparison processing information input from the test pattern creating means 3. The data is output to the simulation result display means 5 and stored in the simulation result storage means 6. The above process is repeated until the logic circuit is no longer inconvenient.

The simulation after the logic circuit modification performed by the simulation executing means 4 is the connection information comparing means 7
Since it is performed by the test pattern created based on the comparison processing information from, the simulation time is significantly shortened because it is limited to the correction area and its influence area. The simulation execution route performed by the simulation execution means 4 is displayed on the simulation execution route display means 8 each time.

Next, the operation of the present invention will be described in detail with reference to the flow chart shown in FIG. 3 and the logic circuit diagram shown in FIG. First, as shown in FIG. 3, a logic simulation is executed for a simulation target circuit, for example, a logic circuit as shown in FIG. 4 (a) (step S1). Figure 4
As shown in (a), the logic circuit diagram is input through the circuit diagram inputting means 1 shown in FIG. 2, and the connection information extracting means 2 obtains the connection information A as shown in FIG. 4 (b). In the logic circuit diagram shown in FIG. 4 (a), the output terminals of the NOT circuits 25 and 26 are connected to the respective input terminals of the NOR circuit 24, and the output terminal of the NOR circuit 24 is connected to one input terminal of the NAND circuit 23. At the same time, the output terminal of the NOT circuit 27 is connected to the other input terminal. In the connection information A shown in FIG. 4B, 15 to 22 are signal line node names and 23, respectively.
~ 27 indicates the instance name.

In the connection information shown in FIG. 4 (b), the instance name of each element and its input end a, b and output end Y are described. A simulation is executed for such connection information based on the test pattern, and the result is stored in the simulation result storage means 6. If there is any inconvenience in the simulation result, the logic circuit diagram is corrected (step S2).

FIG. 5 (a) is a modified logic circuit diagram, and FIG. 5 (b).
Shows the connection information B extracted similarly. Figure 5 (a)
In comparison with the logic circuit diagram shown in FIG. 4 (a), the circuit diagram shown in FIG. 4 has the NOR circuit 24 modified to a NAND circuit 29, as is apparent. The signal node names of the input terminals a and b and the output terminal Y remain unchanged. The corrected logic circuit diagram is input again through the circuit diagram inputting means 1 shown in FIG. 2, and the connection information extracting means 2 extracts the connection information as shown in FIG. 5B (step S3). In the connection information shown in Fig. 5 (b),
It has been rewritten to NAND = 29 instead of NOR = 24.

The connection information about the corrected logic circuit is output to the connection information comparison means 7 and compared therewith with the connection information of the logic circuit before correction read from the simulation result storage means 6 (step S4). Connection information is extracted by the connection information extraction means 2 from the information subjected to the comparison processing (step S5), is output to the simulation execution means 4, the simulation is executed (step S6), and the result is displayed (step S7).

FIG. 5 (c) shows a comparison processing result by the connection information comparing means 7, which is an element or node that outputs a signal whose signal change with time does not match the simulation result of the logic circuit before correction, that is, a NOT circuit. 25, 26, 27 are erased, and the NAND circuit 29 and its input terminals a, b (node names 18, 1
9), only the information regarding the output terminal Y, the NAND circuit 23 to which this output terminal is connected to the input terminal and its input terminals a and b (node names 20, 21), and the output terminal Y (node name 22) remain. Circuit
(Enclosed by a solid line). Therefore, the comparison processing information from the connection information comparison means 7 is information in a state where the area 32 surrounded by a broken line in FIG. 5B is erased.

FIG. 6 (a) is a logic circuit diagram showing another modification of the logic circuit diagram. The output terminal (node name) of the NOT circuit 27 is different from the logic circuit diagram before modification shown in FIG. 4 (a). 20) and NAND circuit
It has been modified to add the NOT circuit 30 to the input terminal (node name 31) of 23.

As a result, the comparison processing information from the connection information comparing means 7 is, as shown in FIG. 6 (b), from the connection information shown in FIG. 4 (b), NOT circuits 25, 26, 27 and NOR circuits common to both are obtained. twenty four
Is erased, the NOT circuit 30 and its input end a (node name 20), output end Y (node name 31) information, and the output end of this NOT circuit 30 are connected to the input end.
Only the information of the NAND circuit 23 and its input ends a and b (node names 21, 31) and the output end Y (node name 22) is left.

FIG. 7 (a) is a logic circuit diagram showing still another modification example. NOT to the circuit diagram before modification shown in FIG. 4 (a).
The circuit 15 and the NOT circuit 24 are modified to be deleted. As a result, the comparison processing information becomes as shown in FIG. 7 (b), and as is apparent by comparing this with FIG. 4 (b), the NOT circuit 25 is deleted, and the NAND circuit 23 (instance name 23) and its Input terminal (node name 19), output end Y (node name 22)
Only information about will be left. Of the information about the NAND circuit 23, the input end b (node name 20) is erased as a result common to both.

[0021]

As described above, in the device of the present invention, the connection information of the logic circuit before correction is compared with the connection information of the logic circuit after correction, and the signal change with time shows the simulation result of the logic circuit before correction. Since the logic simulation is executed only for the elements, nodes, etc. that output signals that do not match with the above, the number of nodes to be simulated is reduced, and the time required for the logic simulation can be greatly shortened. It plays.

[Brief description of drawings]

FIG. 1 is a block diagram showing each unit constituting a conventional device and its input / output information.

FIG. 2 is a block diagram showing each means constituting the device of the present invention and input / output information thereof.

FIG. 3 is a flow chart showing the processing steps of the device of the present invention.

FIG. 4 is an explanatory diagram showing a logic circuit diagram to be simulated and its connection information.

FIG. 5 is a logic circuit diagram before correction, an explanatory diagram showing connection information extracted from the logic circuit diagram, and a logic circuit diagram after a comparison process.

FIG. 6 is a logic circuit diagram showing another modification example and an explanatory diagram showing connection information thereof.

FIG. 7 is a logic circuit diagram showing still another modification example and an explanatory diagram showing connection information thereof.

[Explanation of symbols]

 1 Circuit Diagram Input Means 2 Connection Information Extraction Means 3 Test Pattern Creation Means 4 Simulation Execution Means 5 Simulation Result Display Means 6 Simulation Result Storage Means 7 Connection Information Comparison Means 8 Simulation Execution Route Display Means

Claims (1)

[Claims] 1. A logic circuit diagram inputting means, and connection information extracting means for extracting connection information from the input logic circuit diagram,
In a circuit simulation device including a test pattern creating means and a simulation executing means, means for storing a simulation result for a logic circuit before correction, connection information of the logic circuit before correction stored in the storage means, and correction The test pattern is provided for the correction area obtained by the connection information comparing means, which has connection information comparing means for comparing the connection information of the subsequent logic circuit and extracting the correction area of the logic circuit. A circuit simulation device characterized in that a test pattern is created by a creating means and a simulation is performed on a correction area by the simulation executing means.