JPH09325974A - Operation verification device for function block part - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an operation verification device with which the problem of timing or logic error can be canceled when simulating a plurality of functional block parts. SOLUTION: A simulation part 13 is provided with an inter-block terminal storage part 15 for storing the terminal names of functional block ports to be mutually connected inside a logic circuit and an inter-block data storage part 16 for storing the simulated result for each terminal store in the inter-block terminal storage part 15 when executing the simulation and the data stored in the respective storage parts 15 and 16 are utilized so that the simulation can be executed while using the result of operation verification due to one functional block part as input data to the following functional block part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for verifying the operation of each functional block unit in a large-scale logic circuit that is divided into a plurality of functional block units.

[0002]

2. Description of the Related Art Conventionally, most of the logic circuits are LSIs.
It has a plurality of functional block units and a CPU. In such a logic circuit, various methods are known for testing, that is, verifying the operation of each functional block section. Usually, simulation data is input to the functional block portion to be verified from outside the logic circuit, and the functional block portion is operated based on the simulation data. The operation result output from the functional block unit is evaluated by an evaluation device outside the logic circuit to confirm that the functional block unit is operating normally.

In the conventional method, when a plurality of functional block parts are present, the operational verification of the next functional block part is started after the operational verification by the simulation data is completed in one functional block part. As described above, since the above-described simulation is sequentially performed for each function block unit, the time required for operation verification of the entire logic circuit is at least equal to the sum of operation verification time of each function block unit. It takes time, and it takes a long time.

Therefore, in order to reduce the test time, the individual operation verifications are performed in parallel for each of the functional block sections as described above, and the operation result is immediately confirmed in each functional block section. Attempts have also been made to output the signals in parallel. According to this method, the operation verification time is the time required for the longest one of the test times of each functional block unit, so the test time is shorter than that of the system that requires the total simulation time as described above. Significantly shortened. But,
In the method of performing the operation verification in parallel as described above, it is necessary to input the simulation data and output the operation verification result by the simulation for each functional block unit to be tested. Therefore, it is necessary to input / output a control signal for each functional block unit to control each functional block unit, and the configuration required for these tests becomes very large.

In order to solve such a problem, Japanese Patent Laid-Open No. 4-55778 simulates a functional block part according to an instruction in accordance with a program executed by a processor included in the same system as the functional block part to be subjected to operation verification. As a result, there is disclosed a technique for shortening the test time without increasing the size of the structure for performing the test.

[0006]

In each of the above-mentioned prior arts, in the operation verification by the functional simulation of the dividedly designed logic circuit, an input pattern for the functional simulation is manually created for each functional block unit. The operation verification was performed with the data obtained by manually correcting the results output from other simulations as the input pattern. However, in the operation verification in the logic design for each functional block unit, if a simulation input pattern is created for each functional block unit, problems such as operational timing mistakes between functional block units and logic mistakes in connection may occur. There is.

Therefore, an object of the present invention is to solve problems such as timing and logic mistakes by using the operation verification result as an input pattern of another function block section without human intervention in the operation verification of each function block section. It is another object of the present invention to provide an operation verification technique that can solve the problem and further reduce the time required to create an input pattern.

[0008]

In order to solve the above-mentioned problems, in the operation verification of the functional block according to the present invention,
When verifying the operation of multiple functional block units designed separately in a large-scale logic circuit for each functional block unit, it has the function of storing the simulation output result executed for each functional block unit. Output result of
The simulation is performed as an input pattern of another connected functional block unit.

Specifically, a functional block operation verification apparatus according to the present invention is an apparatus for verifying the operation of each functional block section with respect to a logic circuit composed of a plurality of functional block sections. The present invention is characterized by comprising a simulation means for using the operation verification result by one functional block unit as input data to the subsequent functional block unit. In this device, the output from a function block can be used as it is as an input to another function block, the number of input patterns created by hand can be reduced, and the input pattern creation time can be reduced. Be reduced.

The simulation means operates by the first memory which holds the input / output connection information of at least one functional block section, and the functional block section according to the connection information held in the first memory. And a means for deciding the distribution destination of the verification result. With this configuration, the outputs connected to the other functional blocks are selectively distributed according to the connection information held in the first memory.

Further, the simulation means is further configured to have a second memory that holds the operation verification result of each function block unit by linking it with the input / output connection information of the function block unit. With this configuration, the operation verification result and the input / output connection information thereof are held in the second memory. Therefore, when performing operation verification on the output destination of the operation result held in the second memory,
By reading this second memory, it is possible to obtain the operation verification result that should be the input.

Further, the second memory holds an operation verification result of each function block unit for each of the function block units held in the first memory and holding the input / output connection information. To do so. By doing so, the input source and the output destination are held for each individual operation verification result, and the second memory is read in all the functional block units to which the operational verification results from other functional blocks are input. This makes it possible to obtain the operation verification result that should be the input.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block configuration diagram of an embodiment of the present invention, and shows an example of a case in which a function block portion 11 to be verified is simulated by an input pattern 12 composed of prescribed input data.

In this embodiment, the simulation unit 1
3, an inter-block terminal storage unit 15 (first memory) is provided. The inter-block terminal storage unit 15 stores the terminal names of the functional block units that are mutually connected in the logic circuit. Simulation part 1
3 further includes an inter-block data storage unit 16 (second memory). The inter-block data storage unit 16 stores the simulation result for each terminal stored in the inter-block terminal storage unit 15 when the simulation is executed.

FIG. 2 shows a plurality of functional block units 21 and 22.
3 shows an example of a logic circuit 23 composed of During the functional block simulation, each unit shown in FIGS. 1 and 2 is controlled by a control unit (not shown) such as data reading and input / output. Figure 3 shows the operation
Shown in

Details of the functional block simulation will be described below with reference to the flow chart of FIG. 3 using the stored data for storing the connection terminal names between the functional block portions shown in FIG. In FIG. 3, S represents a processing step.

When the functional block simulation is started, first, for each terminal of each functional block section, it is detected whether or not the terminal is connected to the output of another functional block section. In this embodiment, the circuit diagram data is read by an appropriate means to detect whether or not each terminal is connected to another functional block unit. The result is stored in the inter-block terminal storage unit 15 as connection data (S31).

Thereafter, it is detected for each input terminal of each function block unit whether or not the input is from another function block unit, and whether the data in the inter-block data storage unit is used or not is determined according to the result. It is determined (S32).

In this embodiment, as shown in FIG. 2, neither of the input terminals A1 and A2 of the function block unit 21 is connected to the function block unit, so that the input terminals of the function block unit 21 are connected to each other. On the other hand, the input pattern created in advance is read (S37) and the simulation is performed. On the other hand, the output terminal B of the functional block unit 21
Of B1, B2, B3, since the B1 and B2 terminals are connected to the input terminals of the functional block unit 22, the inter-block terminal storage unit 15 of FIG. As shown by 41, the terminal names, that is, B1 and B2 are stored (S31).

After storing these terminal names, a simulation result of the stored terminal names is stored in the inter-block data storage unit 16 by performing a simulation. The simulation result of the functional block unit 21 is output to the result output unit 14 as the simulation result.

Next, the functional block section 22 is simulated. The input terminal of the functional block unit 22 is an input terminal B connected to the functional block unit 21.
1, C1 and an input terminal C2 directly from the outside, and output terminals D1 and D2 to the outside. In this case, like the functional block unit 21, the circuit data of the functional block unit 22 is read and the stored data 41 of the functional block unit 21 stored in the inter-block terminal storage block 15 and the input terminal name of the functional block unit B22 are read. The connection information having different terminal names is stored in the interblock terminal storage unit 15 as the storage data 42 (S31).

When the functional block unit 22 has a connection in the logic circuit, the output terminal name is stored in the inter-block terminal storage block 15 as in the functional unit block 21. Input whether the data of the inter-block data storage block 16 is used or not when the simulation is executed (S3
2). When used, the stored data 42 of the inter-block terminal storage unit 15 is searched for whether or not the data to the input terminal of the functional block unit 22 exists in the inter-block data storage block 16 (S33).

If there is a retrieved terminal name, the data (B1, B2 terminal data) stored in the inter-block data storage section 16 is read as an input pattern (S35). If there is no searched terminal name, the data created as the input pattern 12 is used as the input pattern of the C2 terminal to perform simulation (S36), and the result is output to the inter-block data storage unit (S38). If there is data in the inter-block terminal storage unit 15 but no data in the data storage unit 16, a simulation is performed using the created input pattern 12 (S36).

If there is an output terminal stored in the inter-block terminal storage section 15 in the functional block section 22, the simulation result data is stored in the inter-block data storage section 16. The simulation result of the function block unit 22 is output to the result output unit 14.

As described above, in this embodiment, the output result obtained by performing the simulation for each functional block unit is stored in the inter-block data storage unit 16, so that another functional block unit connected in the logic circuit is connected. The data stored in the inter-block data storage unit 16 at the time of executing the simulation can be read as it is during the simulation of other functional block units, and the simulation can be performed by using this as an input pattern.

[0026]

As is apparent from the above description, according to the present invention, the operation verification result is used as an input pattern of another function block section without human intervention when verifying the operation of each function block section. Therefore, problems such as timing and logic mistakes can be solved, and further, the time required to create an input pattern can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a functional block simulation according to an embodiment of the present invention.

FIG. 2 is a logic circuit diagram according to the present embodiment.

FIG. 3 is a flowchart showing an operation example of the present embodiment.

FIG. 4 is an explanatory diagram showing an example of stored data in an inter-block terminal storage unit according to the present embodiment.

[Explanation of symbols]

 11 Verification Function Block Unit 12 Input Pattern 13 Simulation Unit 14 Result Output Unit 15 Inter-block Terminal Storage Unit 16 Inter-block Data Storage Unit 21, 22 Functional Block Unit 23 Logic Circuit

Claims (4)

[Claims] 1. A device for verifying the operation of each function block unit with respect to a logic circuit composed of a plurality of function block units, wherein the result of operation verification by at least one function block unit is the succeeding function block unit. An operation verification device for a functional block, comprising a simulation means for inputting data to the device. 2. The simulation means includes a first memory that holds input / output connection information of at least one function block unit, and an operation performed by the function block unit according to the connection information held in the first memory. The operation verification apparatus for a functional block according to claim 1, further comprising: means for determining a distribution destination of the verification result. 3. The simulation means further comprises:
3. The functional block operation verification device according to claim 2, further comprising a second memory that holds the operation verification result of each functional block section linked to input / output connection information of the functional block section. 4. The second memory holds an operation verification result of an individual function block unit for each of the function block units held in the first memory and holding input / output connection information. 4. The functional block operation verification device according to claim 3, wherein