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JPH05308207A - High frequency semiconductor package - Google Patents

High frequency semiconductor package

Info

Publication number
JPH05308207A
JPH05308207A JP4137984A JP13798492A JPH05308207A JP H05308207 A JPH05308207 A JP H05308207A JP 4137984 A JP4137984 A JP 4137984A JP 13798492 A JP13798492 A JP 13798492A JP H05308207 A JPH05308207 A JP H05308207A
Authority
JP
Japan
Prior art keywords
high frequency
conductor
package
semiconductor
frequency characteristic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4137984A
Other languages
Japanese (ja)
Inventor
Takanori Onoda
高典 小野田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FUKUSHIMA NIPPON DENKI KK
NEC Fukushima Ltd
Original Assignee
FUKUSHIMA NIPPON DENKI KK
NEC Fukushima Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FUKUSHIMA NIPPON DENKI KK, NEC Fukushima Ltd filed Critical FUKUSHIMA NIPPON DENKI KK
Priority to JP4137984A priority Critical patent/JPH05308207A/en
Publication of JPH05308207A publication Critical patent/JPH05308207A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a desired high frequency characteristic by making a slit-like cut to a conductor on a dielectric board for the package. CONSTITUTION:In order to connect a bonding wire 4A connecting to an electrode of a semiconductor chip 4 and a lead wire 6 of the semiconductor package, a metallized conductor 3 is formed on a dielectric board 5. A slit-like cut is made in advance to the conductor 3 at two positions or over longer than a half of the width of the conductor 3 and the cuts 1 are arranged in parallel alternately so as not to be overlapped. The cuts 1 are provided to the electrode required in the electric characteristic and the quantity of the cut 1 is increased by using a laser cutter while measuring the high frequency characteristic in this state and the cutting is stopped when the desired high frequency characteristic is obtained. Then the high frequency semiconductor element in the package whose high frequency characteristic is arranged is obtained flexibly.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体を収納するパッ
ケージに係り、とくに,高周波用半導体のパッケージに
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a high frequency semiconductor package.

【0002】[0002]

【従来の技術】従来の高周波用半導体のパッケージ構造
は図2に示されるように,誘電体基板55にメタライズ
された導体53に接続されたリード線56を有し、この
導体53に半導体チップ54の電極をボンディングワイ
ヤ54を介して接続することで,半導体電極とリード線
56との間を接続するようになっている。そして半導体
チップ54上にキャップ57を被せ,これによって半導
体を保護するものとなっている。
2. Description of the Related Art A conventional high frequency semiconductor package structure has a lead wire 56 connected to a conductor 53 metallized on a dielectric substrate 55, and a semiconductor chip 54 is attached to the conductor 53, as shown in FIG. The electrodes are connected via the bonding wires 54 to connect the semiconductor electrodes to the lead wires 56. Then, a cap 57 is put on the semiconductor chip 54 to protect the semiconductor.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
パッケージ構造では、半導体チップ54の高周波特性と
パッケージの高周波特性が合成されて特性が現われる。
そのため、半導体チップ54とパッケージのいづれかの
高周波特性が変動した場合、全体としての特性が変動し
たとこになり、パッケージ入り半導体としてこの素子を
使用した高周波回路の特性が個々に変動することにな
り、かかる変動が電子機器等の生産上、大きな支障とな
るという不都合があった。
However, in the conventional package structure, the high-frequency characteristics of the semiconductor chip 54 and the high-frequency characteristics of the package are combined to make the characteristics appear.
Therefore, if the high-frequency characteristics of either the semiconductor chip 54 or the package fluctuates, it means that the characteristics as a whole fluctuate, and the characteristics of the high-frequency circuit using this element as a packaged semiconductor individually change. There is an inconvenience that such a variation greatly hinders the production of electronic devices and the like.

【0004】[0004]

【発明の目的】本発明は、このような従来例における不
都合を改善し、とくに、所望の高周波特性に合わせるこ
とができる融通性を備えた高周波用半導体パッケージを
提供することを,その目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-frequency semiconductor package which has the above-mentioned disadvantages in the prior art and which has flexibility and can be adjusted to desired high-frequency characteristics. .

【0005】[0005]

【課題を解決するための手段】本発明は、誘電体基板上
に半導体チップを搭載し、この半導体チップをキャップ
で被覆するパッケージにおいて、誘電体基板上の導体に
スリット状の切れ込みが設けられるという構成を採って
いる。これによって、前述の目的を達成しようとするも
のである。
According to the present invention, in a package in which a semiconductor chip is mounted on a dielectric substrate and the semiconductor chip is covered with a cap, slits are formed in a conductor on the dielectric substrate. The composition is adopted. This is intended to achieve the above-mentioned object.

【0006】[0006]

【作用】パッケージを構成する誘電体基板上の導体にス
リット状の切れ込みを入れることによって、半導体パッ
ケージのリード線のもつインダクタンス量を調整するこ
とが可能となり、半導体チップをパッケージに実装した
状態で高周波特性を測りながらスリット量を調整するこ
とで高周波特性の均一なパッケージ入り半導体素子を提
供することができる。
[Function] By making slit-like cuts in the conductor on the dielectric substrate that constitutes the package, it is possible to adjust the amount of inductance of the lead wire of the semiconductor package, and the high frequency is achieved when the semiconductor chip is mounted on the package. By adjusting the slit amount while measuring the characteristics, it is possible to provide a packaged semiconductor element having uniform high frequency characteristics.

【0007】[0007]

【実施例】以下、本発明の一実施例を図面に基づいて説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0008】図1は本発明の一実施例のマイクロ波用半
導体パッケージの斜視図を示している。この図におい
て、キャップ7内部の構造は従来品と同様であり、半導
体チップの電極に接続されたボンディングワイヤと半導
体パッケージのリード線6とを接続するために,誘電体
基板5上にメタライズされた導体3が形成されている。
導体3にはあらかじめスリット状の切れ込み1が導体3
の幅の半分より少し長めに2ケ所以上設けられており、
かつ、それら切り込み1は重ならないように交互に並設
されている。切れ込み1は電気特性上必要とされる電極
に設けられるようになっており、この状態で高周波特性
を測りながらレーザーカッターなどで切れ込み1の量を
増やしていき、高周波特性が所望の特性になったところ
で停止させ。ればよい。これによって高周波特性の揃っ
たパッケージ入り高周波用半導体素子が融通性をもって
得ることができる。
FIG. 1 is a perspective view of a microwave semiconductor package according to an embodiment of the present invention. In this figure, the structure inside the cap 7 is the same as that of the conventional product, and is metallized on the dielectric substrate 5 in order to connect the bonding wire connected to the electrode of the semiconductor chip and the lead wire 6 of the semiconductor package. The conductor 3 is formed.
The conductor 3 has a slit-shaped cut 1 in advance.
There are two or more places that are slightly longer than half the width of
Moreover, the notches 1 are alternately arranged so as not to overlap each other. The notch 1 is provided on the electrode required for electrical characteristics, and while measuring the high frequency characteristic in this state, the amount of the notch 1 is increased with a laser cutter or the like, and the high frequency characteristic becomes the desired characteristic. By the way, stop it. Just do it. As a result, a packaged high-frequency semiconductor element with uniform high-frequency characteristics can be obtained flexibly.

【0009】[0009]

【発明の効果】以上説明したように、本発明の前記構成
によれば、高周波特性を段階的に合わせるように切れ込
みの形成量を調整可能としたので、均一な高周波特性を
もった高周波用半導体素子を提供できるという,従来に
ない優れた効果を奏するパッケージとすることが実現さ
れる。
As described above, according to the above-described structure of the present invention, since the amount of notch formation can be adjusted so that the high frequency characteristics are matched stepwise, the high frequency semiconductor having uniform high frequency characteristics. It is possible to provide a package that can provide an element, which has an unprecedented excellent effect.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示した高周波半導体パッケ
ージ全体の斜視図である。
FIG. 1 is a perspective view of an entire high frequency semiconductor package showing an embodiment of the present invention.

【図2】図2(A)は従来例を示す斜視図で内部構造を
示すためにキャップをする前の状態を示し,図2(B)
は図2(A)の状態からキャップをした後の状態を示す
図である。
FIG. 2 (A) is a perspective view showing a conventional example, showing a state before capping to show the internal structure, and FIG. 2 (B).
FIG. 3 is a diagram showing a state after the cap is capped from the state of FIG. 2 (A).

【符号の説明】[Explanation of symbols]

1 切れ込み 2 ボンディングワイヤ 3 導体 4 半導体チップ 5 誘電体基板 7 キャップ 1 notch 2 bonding wire 3 conductor 4 semiconductor chip 5 dielectric substrate 7 cap

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 誘電体基板上に半導体チップを搭載し、
この半導体チップをキャップで被覆するパッケージにお
いて、前記誘電体基板上の導体にスリット状の切れ込み
が設けられることを特徴とする高周波半導体パッケー
ジ。
1. A semiconductor chip is mounted on a dielectric substrate,
A high-frequency semiconductor package in which a slit-shaped notch is provided in a conductor on the dielectric substrate in a package which covers the semiconductor chip with a cap.
JP4137984A 1992-04-30 1992-04-30 High frequency semiconductor package Pending JPH05308207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4137984A JPH05308207A (en) 1992-04-30 1992-04-30 High frequency semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4137984A JPH05308207A (en) 1992-04-30 1992-04-30 High frequency semiconductor package

Publications (1)

Publication Number Publication Date
JPH05308207A true JPH05308207A (en) 1993-11-19

Family

ID=15211343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4137984A Pending JPH05308207A (en) 1992-04-30 1992-04-30 High frequency semiconductor package

Country Status (1)

Country Link
JP (1) JPH05308207A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557144A (en) * 1993-01-29 1996-09-17 Anadigics, Inc. Plastic packages for microwave frequency applications
KR100686003B1 (en) * 2000-02-23 2007-02-23 엘지전자 주식회사 High frequency device package and its manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03117901A (en) * 1989-09-29 1991-05-20 Fujitsu Ltd Adjustment pattern for high frequency amplifier
JPH03258004A (en) * 1990-03-07 1991-11-18 Tdk Corp Impedance adjustment method in lc composite circuit
JP3107805B2 (en) * 1990-03-29 2000-11-13 株式会社リコー Image recording device with banding machine

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03117901A (en) * 1989-09-29 1991-05-20 Fujitsu Ltd Adjustment pattern for high frequency amplifier
JPH03258004A (en) * 1990-03-07 1991-11-18 Tdk Corp Impedance adjustment method in lc composite circuit
JP3107805B2 (en) * 1990-03-29 2000-11-13 株式会社リコー Image recording device with banding machine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557144A (en) * 1993-01-29 1996-09-17 Anadigics, Inc. Plastic packages for microwave frequency applications
KR100686003B1 (en) * 2000-02-23 2007-02-23 엘지전자 주식회사 High frequency device package and its manufacturing method

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Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19970401