JP2611718B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency semiconductor device, and more particularly, to a semiconductor device having a container capable of supporting a high frequency band.

[0002]

2. Description of the Related Art With the spread of satellite broadcasting and the like, semiconductor devices using a frequency band exceeding 10 GHz have been commercialized.
The demand for miniaturization, surface mounting, and cost reduction of semiconductor devices in the high-frequency band has been increasing. A low-cost, surface-mounting type semiconductor chip mounting container for system automation is required.

Conventionally, as a structure of a small-sized, surface-mount type semiconductor container and a semiconductor device of this kind, Japanese Patent Publication No. 52-2023
There is a semiconductor device proposed in Japanese Unexamined Patent Publication No. 0-205. FIG. 8 shows a semiconductor device disclosed in the publication. That is, the dielectric substrate 1
At least one of a first conductor layer 2 formed on the front surface of the substrate, a second conductor layer 3 formed on the back surface of the dielectric substrate 1, and a third conductor layer 4 formed on the side surface of the dielectric substrate 1. A semiconductor chip 5 mounted on one first conductive layer 2, connecting means 7 for electrically connecting an electrode 6 of the semiconductor chip 5 to another first conductive layer 2 ′, and a soldering wire on the second conductive layer 3. A predetermined number of third conductor layers 4 that include the first conductor layer 2 and the second conductor layer 3, including the external lead conductor leads 8 brazed by the material 13.
When viewed from above the surface of the dielectric substrate 1, the first
Have a structure in which the areas occupied by the conductor layer 2 and the second conductor layer 3 on the front and back of the dielectric substrate 1 do not overlap with each other. However, in this conventional semiconductor device, there is always a brazing portion 9 for brazing the conductor lead 8 to the second conductor layer 3, and in order to ensure a practical lead strength,
This brazing part 9 had to be enlarged to some extent.
For example, an external lead conductor lead having a thickness of about 0.2 mm and a width of about 0.4 mm is applied to the conventional semiconductor device, and the tensile strength of the conductor lead in the 90 ° direction is 0.5 kg.
In order to ensure the above, a brazing portion length of at least about 0.8 mm is required.

When the semiconductor device is mounted on another semiconductor device, for example, when the semiconductor device is mounted on a mounting substrate such as Teflon whose back surface has a ground pattern, the lead brazing portion 9 and the mounting portion of the mounting substrate Since a capacitance is formed between the lead brazing portion and the back surface pattern, the lead brazing portion 9 functions as an open stub circuit. This open stub circuit is inserted between a high-frequency transmission line connecting the semiconductor chip and an external circuit, and as the operating frequency of this type of semiconductor device increases, the effect of the open stub circuit causes the semiconductor chip and the external Impedance mismatch will occur with the circuit.

FIG. 9 shows a structure of a conventional surface mount type semiconductor device which avoids an open stub circuit. Only the through-hole and the fourth conductor layer formed in the through-hole make the first
A method of connecting the second conductor layer to the second conductor layer is conceivable, but there is a disadvantage that the through characteristics of the container portion are not good.

[0006]

As described above, in the conventional semiconductor device disclosed in Japanese Patent Publication No. 52-20230, an open stub circuit is formed at a connection portion with an external circuit. There is a drawback that impedance mismatch occurs at frequencies.

Further, the structure in which the through hole is formed and the conductive layer is not formed on the side surface of the substrate has a disadvantage that the through characteristic of the container portion is not good.

[0008]

According to the present invention, a first conductor layer formed on one main surface of a dielectric substrate and a second conductor formed on another main surface of the dielectric substrate are provided. Layer, a third conductor layer formed on the side surface of the dielectric substrate, a through hole penetrating the dielectric substrate, and a fourth conductor formed in the through hole.
A semiconductor chip mounted on one main surface of the dielectric substrate, connecting means for connecting the first conductive layer and the electrode of the semiconductor chip, and an external lead soldered to the second conductive layer And a third conductor layer and a fourth conductor layer are connected to the first conductor layer on one main surface of the dielectric substrate, and the third conductor layer and the fourth conductor layer are connected on the other main surface of the dielectric substrate. A semiconductor device is obtained in which the first conductor layer and the third conductor layer are connected to the second conductor layer, and the second conductor layer is connected to the external lead conductor lead.

[0009]

According to the semiconductor device of the present invention, as a means for electrically connecting the first conductor layer on the front surface of a dielectric substrate used for high-frequency transmission and the second conductor layer on the back surface of the dielectric substrate, It is characterized in that the connection is made by both the third conductor layer formed on the side surface of the substrate and the fourth conductor layer formed in the through hole formed in the dielectric substrate.

The effect as an open stub is canceled by electrically connecting the through hole to a location near the tip of the open stub circuit existing in the conventional semiconductor device by a fourth conductor layer formed in the through hole. Can prevent impedance mismatching.

FIG. 10 is a model diagram showing the resistance and inductance of the conductor layer. (A) is a first example of a conventional structure.
(B) shows the second example of the conventional structure, and (c) shows the first example of the present invention. According to the present invention, a resistance component and an inductance component are connected in parallel,
Dramatic improvements in characteristics that are completely different from the conventional series type can be obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of a semiconductor device according to the present invention, in which a first conductive layer 2 formed on a surface of a dielectric substrate 1 made of alumina or the like having a thickness of about 0.4 mm and a dielectric material. A second conductor layer 3 formed on the back surface of the substrate 1; a third conductor layer 4 formed on the side surface of the dielectric substrate 1;
And a fourth conductor layer 11 formed in the through hole 10. The fourth conductor layer 11 may be formed in the through hole 10 or formed on the wall surface of the through hole. The first conductor layer 2
Both the third conductor layer 4 and the fourth conductor layer 11 form the second
A first conductive layer 2 'is formed on the surface of the dielectric substrate electrically connected to the conductive layer 3 of this embodiment, and a semiconductor chip 5 such as GaAsIC is formed thereon with a brazing material such as AuSn. It is brazed. Electrode 6 of semiconductor chip 5
And the first conductor layer 2 are electrically connected by connection means 7 such as a gold wire. The external lead 8 and the back metal 12 for grounding are brazed to the second conductor layer by a brazing material 13 such as silver brazing. A ceramic cap 14 is adhered to the dielectric substrate 1 with a resin 15.

FIG. 2 is a sectional view showing a second embodiment of the present invention, and FIG. 7 is a partial plan view thereof. The basic configuration is the same as in the first embodiment. In the present embodiment, there are two through holes connecting the first conductor layer 2 and the second conductor layer 3, and these through holes 10, 10 'are each provided with a fourth conductor layer 11
And 11 'are formed. This embodiment has an effect that the inductance component of the fourth conductor layer formed in the through hole can be further reduced.

As a manufacturing method, first, a through-hole portion and a side metal (third conductor layer) forming portion are punched out from an unsintered alumina tape (green tape) shown in FIG. 3 by a predetermined die. Is not shown in the figure). Here, in the present embodiment, a plurality of dielectric substrates are formed, and the side metal forming portion 16 is first punched out in a circular shape like the through hole. After that, conductor (such as tungsten) printing (No. 1,
A second conductor layer) and through-hole metal formation (third and fourth conductor layers) are performed, and thereafter, an insulating layer is printed.
In this embodiment, the insulating layer is printed on the solder dam and the cap sealing portion. Thereafter, a cutting groove 17 is formed by a mold and fired at a temperature of about 1600 ° C. Take a plurality of fired, cut the substrate in the above cutting groove, cut into individual pieces, Ni
By the plating cutting, the side meta part becomes a semicircle or 1/4
Formed as a circle. The individual substrate is joined to the lead frame by Au-Cu or the like. After that, finish plating such as Au is completed (see FIGS. 4, 5, and 6). FIG. 4 is a plan view of the position of the through hole as viewed from above, and FIG. 5 is a bottom view. 4 and 5, the length (unit: mm) is entered. The length is preferably as shown in the figure, but may be changed by about ± 10%.

[0016]

As described above, in the semiconductor device of the present invention, the through hole is formed at a portion near the tip of the brazing portion of the conductor lead for external drawing, and the fourth hole formed in the through hole is formed. The first conductor layer 2 is formed by both the conductor layer and the third conductor layer formed on the side surface of the dielectric substrate.
And the second conductor layer are electrically connected. Due to the connection by the fourth conductor layer, the portion with the conductor lead brazing does not act as an open stub, and it is possible to suppress the mismatch between the semiconductor chip and the external circuit in a high frequency band.

FIGS. 11 (a) and 11 (b) show the reflection loss (S ₁₁ ) of the through characteristic in the container portion of the first embodiment of the present invention.
And the insertion loss (S ₂₁ ), and the reflection loss (S ₁₁ ) is reduced by −15 to approximately 20 GHz.
It can be seen that it can be secured below about dB.

FIGS. 12 (a) and 12 (b) show the container of the conventional structure and the container of the present invention in which the shortcomings of the conventional structure and the effects of the present invention are confirmed by a simple model. Reflection loss (S
Are represented respectively by the insertion loss ₁₁₎ (S _21). Here, the solid line is the characteristic of the structural model of the present invention, and the broken line is the characteristic of the structural model of the first conventional example. As shown in FIG.
In the structural model of the first conventional example, the reflection loss (S ₁₁ ) starts to deteriorate at a frequency of 15 GHz or more, and has a resonance around 30 GHz. In contrast, in the structural model of the present invention,
There is no resonance up to a frequency of 40 GHz, and the reflection loss (S ₁₁ ) is improved at 12 GHz or more as compared with the conventional case.

Further, as a structure of a surface mount type semiconductor device as shown in FIG. 9 for avoiding an open stub circuit, a first hole is formed only by a through-hole and a fourth conductor layer formed in the through-hole.
A second example of the conventional structure in which the second conductor layer and the second conductor layer are connected is considered. In FIGS. 13A and 13B, reflection loss (S ₁₁ ) and insertion loss (S ₂₁ ) are divided. As shown in the actual measurement data comparing the through characteristics of the container portion, it can be seen that the structure according to the present invention is also excellent in the reflection loss (S ₁₁ ) characteristics.

As described above, according to the semiconductor device of the present invention, practically sufficient characteristics can be obtained even in a frequency band of 10 GHz or more. The main part of the container of the semiconductor device can be made by one dielectric substrate, printing technology, through-hole technology and one-time brazing of the lead portion,
Can be created very cheaply.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a sectional view of a second embodiment of the semiconductor device according to the present invention.

FIG. 3 is a plan view showing a substrate before cutting in the first embodiment of the semiconductor device according to the present invention;

FIG. 4 is a plan view of a first embodiment of the semiconductor device according to the present invention.

FIG. 5 is a plan view showing a first embodiment of the semiconductor device according to the present invention.

FIG. 6 is a bottom view of the first embodiment of the semiconductor device according to the present invention.

FIG. 7 is a partial plan view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 8 is a sectional view of a first example of a conventional semiconductor device.

FIG. 9 is a sectional view of a second example of a conventional semiconductor device.

FIG. 10 shows resistance and inductance of a conductive layer portion,
(A) is a first conventional example (b) is a second conventional example (c)
1 is a model diagram showing a first embodiment according to the present invention.

FIG. 11 is a through characteristic diagram of the container section of the first embodiment according to the present invention.

FIG. 12 is a comparative characteristic diagram of the container portion of the first embodiment according to the present invention and the container portion of the first conventional example.

FIG. 13 is a comparison characteristic diagram of the container part of the first embodiment according to the present invention and the container part of the second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dielectric substrate 2 1st conductor layer 3 2nd conductor layer 4 3rd conductor layer 5 Semiconductor chip 6 Electrode of a semiconductor chip 7 Connection means (Au wire etc.) 8 Conductor lead for external drawing 9 Brazing part 10 Through Hole 11 Fourth conductor layer 12 Back metal 13 Brazing material 14 Ceramic cap 15 Resin 16 Punched hole for side metal 17 Cutting groove

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takeshi Umemoto 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Tatsuya Miya 5-7-1 Shiba, Minato-ku, Tokyo Japan Inside Electric Co., Ltd.

Claims (1)

(57) [Claims] A first conductor layer formed on one main surface of the dielectric substrate; a second conductor layer formed on another main surface of the dielectric substrate; The third formed on the side
A conductive layer, a through-hole penetrating the dielectric substrate, a fourth conductive layer formed in the through-hole,
A semiconductor chip mounted on one main surface of the dielectric substrate, connecting means for connecting the first conductor layer and an electrode of the semiconductor chip, and an external lead soldered to the second conductor layer And the third conductor layer and the fourth conductor layer are connected to the first conductor layer on one principal surface of the dielectric substrate, and the other main conductor of the dielectric substrate wherein said fourth conductive layer on the second conductive layer on the surface a third conductive
A semiconductor device, wherein a body layer is connected, and the second conductor layer and the external lead conductor lead are connected.