JPH0530061B2 - - Google Patents
Info
- Publication number
- JPH0530061B2 JPH0530061B2 JP59233086A JP23308684A JPH0530061B2 JP H0530061 B2 JPH0530061 B2 JP H0530061B2 JP 59233086 A JP59233086 A JP 59233086A JP 23308684 A JP23308684 A JP 23308684A JP H0530061 B2 JPH0530061 B2 JP H0530061B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- metal
- bonding pad
- gaas
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 19
- 239000000758 substrate Substances 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、化合物半導体のFET又はダイオー
ドの単体、もしくはそれらの集積回路等の半導体
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor device such as a single compound semiconductor FET or diode, or an integrated circuit thereof.
（従来例の構成とその問題点）
GaAs FETは優れた高周波特性を有するFET
として注目を集めている。近年はその多機能、高
安定性、高利得性に注目して、GaAs MESFET
集積回路も開発されている。しかし、実用化にと
もない、その低価格化が重要な問題となつてい
る。特に、歩留は大きくこの低価格化に関係し、
重要な課題となる。(Conventional configuration and its problems) GaAs FET is a FET with excellent high frequency characteristics
is attracting attention as In recent years, GaAs MESFETs have attracted attention due to their multifunctionality, high stability, and high gain.
Integrated circuits have also been developed. However, as they become more practical, their cost reduction has become an important issue. In particular, yield is greatly related to this lower price.
This will be an important issue.
GaAs MESFET回路においては、エピタキシ
ヤル層を堆積し、あるいはイオン注入したGaAs
基板上に回路が形成される。即ち、第１図に示し
たように、GaAs基板１の表面をSiO2などの絶縁
膜６で覆い、これに窓あけして、ソース及びドレ
インとしてのオーミツク金属３、およびゲート金
属２をつけ、配線金属４で配線及びボンデイング
パツド５を形成する。 GaAs MESFET circuits use GaAs with epitaxial layers or ion implantation.
A circuit is formed on the substrate. That is, as shown in FIG. 1, the surface of a GaAs substrate 1 is covered with an insulating film 6 such as SiO 2 , windows are opened in this, ohmic metal 3 as a source and drain, and gate metal 2 are attached. Wiring and bonding pads 5 are formed using wiring metal 4.
ところで、このようなGaAs MESFET回路素
子を量産する場合、ワイヤボンデイング時に、パ
ツド直下の絶縁膜６がはがれることがしばしばお
こる。この剥離は、超音波を使用するワイヤボン
デイングでなくても生じ、多いときには、ワイヤ
ボンデイングした素子の半数が不良となることが
ある。これは、１つの素子中の幾つかのパツドの
うち、１つでもはがれれば不良となるからであ
る。つまり、歩留を著しく低下させ、素子の価格
も著しく上がつてしまうことになる。 By the way, when such GaAs MESFET circuit elements are mass-produced, the insulating film 6 directly under the pad often peels off during wire bonding. This peeling occurs even when wire bonding is not performed using ultrasonic waves, and in some cases, half of the wire-bonded devices may become defective. This is because if one of the several pads in one element comes off, it becomes defective. In other words, the yield will be significantly reduced and the cost of the device will also be significantly increased.
この原因としては、ソース及びドレインのオー
ミツク金属３のアロイ時に500℃程度の高温度に
上げるため、SiO2などの絶縁膜６とGaAs基板１
の間に熱歪が生じ、小さいクラツク等を生じるた
めと考えられる。一方、この絶縁膜６はGaAs基
板１と非常に接着力が強いため、ワイヤボンデイ
ング時のはがれでは、ボンデイングパツド直下の
GaAs基板にえぐれを生じることが多い。 The reason for this is that when the ohmic metal 3 of the source and drain is alloyed, the temperature is raised to a high temperature of about 500°C, so the insulating film 6 such as SiO 2 and the GaAs substrate 1
This is thought to be due to thermal strain occurring during this time, resulting in small cracks. On the other hand, this insulating film 6 has a very strong adhesion to the GaAs substrate 1, so if it peels off during wire bonding,
Often causes gouges in GaAs substrates.
この絶縁膜６とGaAs基板１との間のはがれ
は、ボンデイングパツド５の金属と絶縁膜６との
間のはがれより圧倒的に多く、ほぼ95％以上が前
者のはがれである。これは、金属と絶縁膜６間の
接着力がより強固なものであるためと考えられ
る。また、ボンデイングパツド５の金属は、オー
ミツク金属のアロイのための高温処理の後に形成
されるため高温にさらされることなく、従つて下
層との歪も生じにくいためと考えられる。 The peeling between the insulating film 6 and the GaAs substrate 1 is overwhelmingly greater than the peeling between the metal of the bonding pad 5 and the insulating film 6, and approximately 95% or more is the peeling of the former. This is considered to be because the adhesive force between the metal and the insulating film 6 is stronger. Furthermore, since the metal of the bonding pad 5 is formed after high-temperature treatment for ohmic metal alloys, it is not exposed to high temperatures and is therefore less likely to cause distortion with the underlying layer.
（発明の目的）
本発明は、このような従来の問題に鑑み、はが
れを防ぎ、組立歩留の高い化合物半導体装置を提
供することを目的とする。(Object of the Invention) In view of such conventional problems, an object of the present invention is to provide a compound semiconductor device that prevents peeling and has a high assembly yield.
（発明の構成）
本発明の半導体装置は、化合物半導体上に形成
された絶縁膜に開口部を設け、この開口部を通し
てボンデイングパツド金属が直接、化合物半導体
上に密接して形成される。この構成によりワイヤ
ボンデイング時にボンデイングパツドのはがれの
ない安定した組立を可能とするものである。(Structure of the Invention) In the semiconductor device of the present invention, an opening is provided in an insulating film formed on a compound semiconductor, and a bonding pad metal is formed directly and in close contact with the compound semiconductor through the opening. This structure enables stable assembly without peeling of the bonding pad during wire bonding.
（実施例の説明）
第２図は、本発明の一実施例におけるGaAs
MESFETの断面を示したものであり、第１図と
同様に、エピタキシヤル層を堆積し、あるいはイ
オン注入したGaAs基板１上に、MESFETが形
成される。つまり、GaAs基板１をSiO2などの絶
縁膜６で覆い、これに窓あけして、ソース及びド
レインのオーミツク金属３をつける。ゲート金属
２も同様につけ、配線金属４で配線を行なう。本
発明のボンデイングパツド７は、配線金属４で配
線する前に、このボンデイングパツド直下の絶縁
膜６を除去し、配線金属の一部を、直接GaAs基
板１上に密着させてボンデイングパツド７とす
る。(Explanation of Example) Figure 2 shows GaAs in an example of the present invention.
This figure shows a cross section of a MESFET, and similarly to FIG. 1, the MESFET is formed on a GaAs substrate 1 on which an epitaxial layer is deposited or ions are implanted. That is, a GaAs substrate 1 is covered with an insulating film 6 such as SiO 2 , a window is opened in this, and ohmic metals 3 for the source and drain are attached. Gate metal 2 is also attached in the same manner, and wiring is performed using wiring metal 4. In the bonding pad 7 of the present invention, before wiring with the wiring metal 4, the insulating film 6 directly under the bonding pad is removed, and a part of the wiring metal is directly adhered to the GaAs substrate 1 to form the bonding pad. Set it to 7.
このように形成されたボンデイングパツド７
は、GaAs基板１と非常に強く接着し、高温処理
にも強いため、このボンデイングパツドへワイヤ
を接合する際に力が加わつても、はがれることが
ない。このため、組立歩留を著しく向上させ、こ
のボンデイングパツドを有する単体素子や、集積
回路の半導体装置の製造コストを著しく低減する
ことになる。 Bonding pad 7 formed in this way
It adheres very strongly to the GaAs substrate 1 and is resistant to high-temperature treatment, so it will not come off even if force is applied when bonding the wire to this bonding pad. Therefore, the assembly yield is significantly improved, and the manufacturing cost of single elements and integrated circuit semiconductor devices having this bonding pad is significantly reduced.
なお、実施例では、MESFET単体で説明した
が、化合物半導体を用いる半導体装置のすべてに
応用できることはいうまでもない。 In addition, in the embodiment, the MESFET alone was explained, but it goes without saying that the present invention can be applied to all semiconductor devices using compound semiconductors.
又、配線はすべて絶縁膜上に形成するように説
明したが、これは浮遊容量を減らすためである。
この容量が無視できるときは、配線金属４も、
GaAs基板１上に直接つけることも可能である。 Furthermore, although it has been explained that all wiring is formed on an insulating film, this is to reduce stray capacitance.
When this capacitance can be ignored, the wiring metal 4 also
It is also possible to attach it directly onto the GaAs substrate 1.
（発明の効果）
以上のように本発明の半導体装置は、化合物半
導体上に形成した絶縁膜に開口部を設け、この開
口部を通してボンデイングパツド金属が直接、化
合物半導体上に密接して形成されることによつ
て、ワイヤ接合の際に、ボンデイングパツドのは
がれをなくし、歩留を向上し、半導体装置の低価
格化に寄与するものである。(Effects of the Invention) As described above, in the semiconductor device of the present invention, an opening is provided in an insulating film formed on a compound semiconductor, and a bonding pad metal is formed directly and closely on the compound semiconductor through this opening. This eliminates peeling of the bonding pad during wire bonding, improves yield, and contributes to lower prices of semiconductor devices.
第１図は、従来のGaAs MESFETの断面図、
第２図は、本発明の一実施例におけるGaAs
MESFETの断面図である。
１……GaAs基板、２……ゲート金属、３……
ソース及びドレインのオーミツク金属、４……配
線金属、６……絶縁膜、７……ボンデイングパツ
ド。
Figure 1 is a cross-sectional view of a conventional GaAs MESFET.
FIG. 2 shows GaAs in one embodiment of the present invention.
FIG. 3 is a cross-sectional view of MESFET. 1...GaAs substrate, 2...gate metal, 3...
Source and drain ohmic metal, 4...wiring metal, 6...insulating film, 7...bonding pad.
Claims (1)
成され、ボンデイングパツド金属が前記開孔部を
通して前記化合物半導体の表面に密接しているこ
とを特徴とする半導体装置。1. A semiconductor device characterized in that an insulating film having an opening is formed on a compound semiconductor, and a bonding pad metal is in close contact with the surface of the compound semiconductor through the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233086A JPS61112361A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233086A JPS61112361A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61112361A JPS61112361A (en) | 1986-05-30 |
| JPH0530061B2 true JPH0530061B2 (en) | 1993-05-07 |
Family
ID=16949570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59233086A Granted JPS61112361A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61112361A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2678662B2 (en) * | 1989-06-08 | 1997-11-17 | 日本電信電話株式会社 | Integrated circuit and manufacturing method thereof |
-
1984
- 1984-11-07 JP JP59233086A patent/JPS61112361A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61112361A (en) | 1986-05-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |