JPH067575B2 - Multi-layer wiring method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for forming a multilayer wiring of a semiconductor integrated circuit.

(B) Conventional technology In semiconductor integrated circuits, electrode wiring must be provided to connect the electrodes.

Electrode wiring is performed in the manufacturing process of semiconductor integrated circuits. Since it is necessary to reduce the electric resistance in the circuit, a metal such as Au or Al, or an Al-based alloy is currently widely used as an electrode wiring material.

In particular, Au is used as the lower electrode wiring material.

However, since the adhesion between Au and the base is weak, a method of forming a lower electrode wiring having a structure in which Ti or the like is used as a base metal and an Au layer is stacked on the base metal is generally used.

The Ti / Au lower layer electrode wiring can secure strong adhesion between the base and the lower layer electrode wiring. Also, it is possible to prevent the wiring metal surface from being oxidized in another process. Ti enables strong adhesion, and Au prevents oxidation of Ti.

The above is related to the lower layer electrode wiring.

Even when the upper-layer metal wiring is bonded onto the lower-layer electrode wiring, the lowermost portion of the upper-layer metal wiring is made of a metal layer such as Ti, Ni, or Mo. This is to improve the adhesive force between the upper and lower layer wirings.

A method of executing metal wiring using only Mo has been proposed. However, this is because it is difficult to deposit Mo,
It is not enough because it has the disadvantages of being easily oxidized.

FIG. 2 is a sectional view showing an example of a wiring structure formed by the conventional multilayer wiring method described above.

The insulating film 4 is coated on the semiconductor crystal substrate 5.
A window is opened in a part of the insulating film 4, and the Au layer 11 forming the uppermost part of the lower electrode wiring is vapor-deposited there. On top of this, a metal layer 12 of Ti, Ni, Mo, etc., which constitutes the upper metal wiring
And a metal layer 13 of Au, Al, Al-based alloy, or the like that constitutes the upper metal wiring.

This cross-sectional view shows only a part of the cross section of the semiconductor integrated circuit. Since it is an integrated circuit, the semiconductor crystal substrate 5 is formed by an epitaxial thin layer portion, diffusion, or ion implantation in addition to the original substrate.
A mold region, a p-type region, etc. are included.

The circuit configuration and function are arbitrary. Since the present invention relates to the multilayer wiring method, it can be applied to a semiconductor integrated circuit having any circuit configuration and function.

The lower layer electrode wiring is a wiring forming the electrode portion. Directly to the semiconductor n-type, p-type, or insulation region (S
I) is contacted and an electric current is applied or a voltage is applied. It indicates a source electrode, a drain electrode, a gate electrode, or the like of the FET.

The term “lower layer” here means that it is close to and under the semiconductor substrate, but it is not the only one.

A semiconductor integrated circuit is a set of many unit elements. The electrodes of the individual elements are separated by the insulating film 4. The insulating film is an insulating film made of SiO ₂ , SiN or the like.

In this way, the wiring is separated for each unit element,
It is called a lower layer electrode wiring because it constitutes an electrode.

The Au layer forming the uppermost part will be described.

In the case of a FET, the source electrode and the drain electrode must make ohmic contact with the n-type layer or the p-type layer. In this case, for example, the structure is Ni / AuGe / Au from the bottom. Also, since the gate electrode is a shutter electrode, Ti / Pt / Au
It is often configured as

In any case, the uppermost layer of the lower electrode wiring is Au. Au
The lower wiring is arbitrary, and is therefore expressed as the Au layer 11 which constitutes the uppermost portion of the lower electrode wiring.

The upper-layer metal wiring refers to wiring for connecting a plurality of unit elements across unit elements. Although it has various lengths, it extends beyond the frame of the unit element.
In FIG. 2, it should be considered that the upper metal wirings 12 and 13 do not extend laterally, but extend in the direction perpendicular to the plane of the drawing.

As described above, the wiring is formed so as to extend beyond the unit element, and is therefore referred to as “upper layer”. In addition, it connects the electrodes, not the electrodes themselves. Therefore, it is called an upper metal wiring.

Even in the upper metal wiring, Ti, in order to increase the adhesion with the base,
After depositing a metal such as Ni or Mo, an Au layer is vapor-deposited on it. Mo cannot be deposited by resistance heating (using a boat), but electron beam deposition can be used.

(C) Problems of the conventional technology The conventional multilayer wiring method has the following drawbacks.

When Ti is used in the lowermost part of the upper layer metal wiring, Au in the uppermost part of the lower layer wiring and Ti chemically react with each other by the heat treatment after the wiring forming step to form an alloy.

The alloying increases the Au-Ti contact resistance. Also, Au
Interdiffuse into the upper metal wiring through the Ti layer. There are such drawbacks.

When Ni is used instead of Ti, there are similar drawbacks.

When Mo is used in the lowermost part of the upper metal wiring, there is a drawback that the adhesive force between Mo and the insulating film is weak. Therefore, there is a problem that the upper metal wiring is easily peeled off. The lowermost part of the upper metal wiring must also be strongly adhered to the insulating film.

Moreover, since Au is used for the upper layer wiring, the cost of the wiring process becomes high.

The conventional multilayer wiring method has such drawbacks. In order to construct an inexpensive and highly reliable multilayer wiring, the above drawbacks must be overcome.

(D) Purpose The present invention provides a multilayer wiring method for a semiconductor integrated circuit, and its objects are (1) no increase in contact resistance between upper and lower wirings, and (2) upper metal wiring. Does not peel off, (3) it is cheap, (4) the hold is high, etc.

(E) Structure The multilayer wiring method of the present invention is (1) on the lower layer electrode wiring having a structure in which the Au layer covered with the Pt layer is the uppermost layer, It is characterized by including the step of adhering wiring.

An example of a wiring structure of a semiconductor integrated circuit manufactured by the multilayer wiring method of the present invention will be described with reference to FIG.

The insulating film 4 is formed on the semiconductor crystal substrate 5.
The semiconductor crystal substrate 5 is a compound semiconductor substrate such as GaAs or InP or a substrate such as Si.

As already mentioned, the substrate contains a semiconductor integrated circuit having many unit elements. This figure shows only a part of the vicinity of one electrode in one unit element.

The substrate is not just a substrate as a material. The wafer process is completed and the functional parts are already formed.

That is, by using an epitaxial thin film formed on the substrate, diffusion, ion implantation, etc.
It is a mold, a p-type, or a high resistance region is formed.

The insulating film 4 is SiN or SiO ₂ .

The insulating film 4 is SiN or SiO ₂ when the substrate is GaAs or InP, but is limited to SiO ₂ when Si is the substrate. Since SiN does not have uniform chemical bonds and it is not always correct to write Si ₃ N _4, it is written as SiN.

A part of the semiconductor substrate is not covered with the insulating film 4 and has a window. Electrode wiring is made here.

The structure of the lower part of the lower layer electrode wiring may be several cases as described above. However, the upper part of the lower electrode wiring is
It is on the Au layer 1.

In the present invention, the upper metal wiring is not directly formed on the Au layer 1.

The lower electrode wiring Au layer 1 is covered with the Pt layer 2. Pt layer 2
May be, for example, 1000Å (0.1 μm). Generally 40
It may be 0 Å (0.0412) or more.

The Pt layer prevents the lower electrode wiring from being oxidized. A coating of about 400Å can prevent the lower electrode wiring from being oxidized.

It is also possible to use Mo or Zr layers instead of pt.

An insulating film 4 made of an insulating material and an Al layer 3 forming an upper metal wiring are provided on the Pt layer 2. The Al layer is a layer made of Al or Al alloy.

Since Al and Al alloy have a strong adhesive force to the insulator, the upper metal wiring is not peeled off. Also, Al and Al alloys are suitable as wiring materials because of their low resistance.

All metal layers used in the present invention are formed by a vacuum deposition method or a sputtering method. Al and Pt can be vacuum deposited by a resistance boat. The Mo layer can be formed by electron beam evaporation, sputtering and CVD.

(F) Operation The lower layer electrode wiring Au layer 1 is covered with Pt layer 2. Therefore, the Au layer and the upper metal wiring are cut off by the Pt layer. Mutual diffusion between the Au layer and the upper metal wiring is prevented by Pt. Since the upper layer metal wiring does not have Ti, Ni, Mo, etc., they are not alloyed with Au of the lower layer electrode wiring. It is possible to prevent an increase in contact resistance due to alloying.

Further, Pt prevents the lower electrode wiring from being oxidized. Therefore, it is possible to avoid the problem that the contact resistance increases due to the presence of the oxide on the surface of the lower electrode wiring, which is found in the conventional wiring structure.

Even if Zr or Mo is used instead of Pt, three functions of mutual diffusion prevention, alloying prevention, and oxidation prevention can be mentioned.

Al or Al alloy has a stronger adhesive force to the insulating layer than Au. When Al or an Al alloy is used as an upper layer metal wiring material, peeling of the upper layer metal wiring can be prevented.

When the metal deposition is performed by using the vacuum deposition method or the sputtering method, it is possible to form a uniform metal film without the inclusion of impurities.

(G) Effect According to the multilayer wiring method of the present invention, (1) the contact resistance between the upper and lower wirings can be reduced.

(2) The upper metal wiring does not peel off. This is because Al and Al alloy are strongly adhered to the insulating layer.

(3) Inexpensive multilayer wiring can be performed. A instead of Au
This is because the Al and Al alloys are used as the upper layer metal wiring material.

(4) High-yield multilayer wiring can be performed.

[Brief description of drawings]

FIG. 1 is a longitudinal sectional view showing a part of a wiring structure formed by the multilayer wiring method of the present invention. FIG. 2 is a longitudinal sectional view showing a part of a wiring structure formed by a conventional multilayer wiring method. 1 ………… Au layer constituting lower electrode wiring 2 ………… Pt layer constituting lower electrode wiring 3 ………… Al layer constituting upper layer metal wiring 4 ………… Insulating film 5 ………… Semiconductor crystal substrate 11 ………… Au layer on top of the lower electrode wiring 12 ………… Metal layers such as Ti, Ni, Mo that compose the upper metal wiring

Claims (3)

[Claims] 1. After a functional portion such as an n-type region and a p-type region is provided on the semiconductor substrate 5, the surface of the semiconductor substrate 5 is covered with an insulating film 4.
The insulating film 4 has a window at the portion where the electrode is taken out and a lower layer electrode wiring that contacts the surface of the semiconductor substrate 5 is provided. In the multi-layer wiring method in which the upper-layer metal wiring is provided so as to be in contact with the A multi-layer wiring method characterized in that a lower layer electrode wiring is formed by coating the upper layer metal wiring with Al or an Al-based alloy. 2. The multilayer wiring method according to claim 1, wherein the Pt, Mo or Zr layer 2 has a film thickness of 400 Å or more. 3. The multilayer wiring method according to claim 1, wherein the lower layer electrode wiring and the upper layer metal wiring are formed by a vacuum deposition method or a sputtering method.