JPH05299582A - Capacitor element - Google Patents
Capacitor elementInfo
- Publication number
- JPH05299582A JPH05299582A JP12550892A JP12550892A JPH05299582A JP H05299582 A JPH05299582 A JP H05299582A JP 12550892 A JP12550892 A JP 12550892A JP 12550892 A JP12550892 A JP 12550892A JP H05299582 A JPH05299582 A JP H05299582A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- metal wiring
- layer
- cvd method
- capacitive element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 13
- 239000003870 refractory metal Substances 0.000 claims description 22
- 150000002736 metal compounds Chemical class 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 7
- 230000005012 migration Effects 0.000 abstract description 6
- 238000013508 migration Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 57
- 239000010410 layer Substances 0.000 description 50
- 238000000034 method Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 description 1
- 238000009774 resonance method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置にお
ける容量素子に関し、特に高速性と高密度性を備えた容
量素子の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive element in a semiconductor integrated circuit device, and more particularly to the structure of a capacitive element having high speed and high density.
【０００２】[0002]
【従来の技術】半導体集積回路装置には、アクティブ素
子としてのＭＯＳＦＥＴやバイポーラトランジスタと共
にパッシブ素子としての抵抗や容量素子が必要である。
この中で、半導体集積回路装置の用途が広がるにつれて
高性能な容量素子への要求が高まりつつある。具体的に
は、(I) 高集積化に対しては、小面積で大容量が実現で
きることと、(II)高速化に対しては容量の周波数依存性
が小さいことが要求される。2. Description of the Related Art A semiconductor integrated circuit device requires a MOSFET or a bipolar transistor as an active element and a resistor or a capacitive element as a passive element.
Among these, as the applications of semiconductor integrated circuit devices are expanded, the demand for high-performance capacitive elements is increasing. Specifically, (I) high integration is required to realize a large capacity in a small area, and (II) high speed is required to have a small frequency dependency of capacity.
【０００３】ところで、容量素子は絶縁物層を電極で挟
む構造が一般的であり、上記(I) に対しては絶縁物層を
薄層化し、同(II)に対しては電極の抵抗を低減すること
が必要であった。しかし、上記(I)，(II) の条件を共に
満足する構造は実現されていないのが実状である。例え
ば、(I) 項を実現するために図６及び図７に示す構造が
提案されていた。By the way, a capacitor element generally has a structure in which an insulating layer is sandwiched between electrodes. For the above (I), the insulating layer is made thin, and for (II), the resistance of the electrode is reduced. It was necessary to reduce. However, the reality is that a structure that satisfies both the above conditions (I) and (II) has not been realized. For example, the structures shown in FIGS. 6 and 7 have been proposed in order to realize the item (I).
【０００４】図６は絶縁膜層として単結晶シリコンの熱
酸化膜２を使用した場合であり、膜厚としては１０ｎｍ
程度まで薄層化できるために単位面積あたりの容量は大
きくできるが、電極としては一方が単結晶シリコン３、
他方が多結晶シリコン１であるため抵抗を小さくするこ
とは困難であった。FIG. 6 shows a case where a thermal oxide film 2 of single crystal silicon is used as an insulating film layer, and the film thickness is 10 nm.
The capacity per unit area can be increased because the layer can be thinned to a certain degree, but one of the electrodes is single crystal silicon 3,
Since the other is polycrystalline silicon 1, it is difficult to reduce the resistance.
【０００５】図７は絶縁膜層として多結晶シリコンの酸
化膜５を使用した場合であり、電極の一方を金属層４と
することにより低抵抗化を図ったものであるが、他方の
電極が多結晶シリコン７であるために、十分な高速度化
ができなかった。なお、図７中符号６は層間絶縁膜、８
は酸化膜、９はシリコン基板である。FIG. 7 shows a case in which a polycrystalline silicon oxide film 5 is used as an insulating film layer, and one of the electrodes is a metal layer 4 to reduce the resistance, but the other electrode is Due to the polycrystalline silicon 7, it was not possible to achieve a sufficiently high speed. Reference numeral 6 in FIG. 7 is an interlayer insulating film, and 8
Is an oxide film, and 9 is a silicon substrate.
【０００６】一方、(II)項の高速化を実現するために両
電極を低抵抗の金属配線とした場合の従来構造を図８に
示す。図８は２層以上の多層金属配線技術を用いて電極
として低抵抗の金属層４1 ，４2 を使用した場合であ
る。この場合の絶縁膜層としては、多層配線技術におい
て用いられる通常のプラズマＣＶＤあるいは熱ＣＶＤ法
による絶縁膜５1 が使用され、その絶縁膜の電流−電圧
特性の一例を図９に示す。この図９は、絶縁膜の形成法
として、ＣＶＤ法，オゾンＴＥＯＳ（テトラエトキシシ
ラン）法，プラズマＴＥＯＳＣＶＤ法で500Å形成した
時の特性２２〜２４をそれぞれ示している。On the other hand, FIG. 8 shows a conventional structure in which both electrodes are made of metal wiring having low resistance in order to realize the high speed operation in the item (II). FIG. 8 shows a case where low resistance metal layers 4 1 and 4 2 are used as electrodes by using a multi-layer metal wiring technique of two or more layers. As the insulating film layer in the case is used the insulating film 5 1 by ordinary plasma CVD or thermal CVD method used in the multilayer wiring technology, current of the insulating film - shows an example of the voltage characteristics in FIG. FIG. 9 shows characteristics 22 to 24 when 500 Å is formed by the CVD method, the ozone TEOS (tetraethoxysilane) method, and the plasma TEOSCVD method as the insulating film forming method.
【０００７】[0007]
【発明が解決しようとする課題】このように、前述した
図６及び図７の構造では、絶縁膜層を薄層化できるため
大容量が実現できるが、電極の両方が低抵抗化されず、
十分な高速度化が達成できないという欠点がある。As described above, in the structure of FIGS. 6 and 7 described above, a large capacity can be realized because the insulating film layer can be made thin, but both electrodes do not have a low resistance,
There is a drawback that a sufficiently high speed cannot be achieved.
【０００８】また、図８の構造では、絶縁膜層として通
常のプラズマＣＶＤあるいは熱ＣＶＤ法による絶縁膜５
1 が使用されているが、これらの膜は単結晶シリコンの
熱酸化膜に比して脆弱であり、図９に示すように、電界
に対して電流が流れやすく絶縁性を考慮すると薄膜化す
ることが困難であり、厚膜の状態で使用することにな
る。このため、単位面積当たりの容量が小さくなり、高
集積化に適さないという欠点を有している。また、上記
のＣＶＤ法は形成温度がいずれも400 ℃程度であるた
め、アルミ合金系の金属配線上に形成した場合熱による
アルミの変形（マイグレーション）が生じ、結果として
容量素子の耐圧不良等が生じ歩留まり、信頼性の劣化を
引き起こす。これらの理由により、より高性能な容量素
子が求められていた。Further, in the structure shown in FIG. 8, the insulating film 5 is formed by the usual plasma CVD or thermal CVD method as the insulating film layer.
Although 1 is used, these films are more fragile than the thermal oxide film of single crystal silicon, and as shown in FIG. It is difficult to use, and it will be used in the state of a thick film. For this reason, the capacity per unit area becomes small, which is not suitable for high integration. In addition, since the above-mentioned CVD methods are all formed at a temperature of about 400 ° C., when they are formed on aluminum alloy-based metal wiring, aluminum is deformed (migrated) due to heat, and as a result, the breakdown voltage of the capacitive element or the like is deteriorated. Yield, which causes deterioration of reliability. For these reasons, a higher performance capacitive element has been demanded.
【０００９】本発明はこのような事情に鑑みてなされた
ものであり、その目的は、高速性と高密度性を兼ね備え
た容量素子を提供することにある。The present invention has been made in view of the above circumstances, and an object thereof is to provide a capacitive element having both high speed and high density.
【００１０】[0010]
【課題を解決するための手段】すなわち本発明の容量素
子は、高速性を実現するため電極を金属により構成する
と共に、高密度性を実現するために電極金属間の絶縁物
層をバイアスＥＣＲプラズマＣＶＤ法により低温で形成
される良質の絶縁膜とすることにより、薄層化を達成し
ようとするものである。また、本発明の別の発明は、上
記のものにおいて電極金属と絶縁膜の界面に高融点金属
あるいは高融点金属化合物層を設けることにより、さら
に信頼性を高めるようにしたものである。That is, in the capacitive element of the present invention, the electrodes are made of metal in order to achieve high speed, and the insulating layer between the electrode metals is biased by ECR plasma in order to achieve high density. By using a high-quality insulating film formed at a low temperature by the CVD method, it is intended to achieve a thin layer. Another invention of the present invention is to further improve reliability by providing a refractory metal or refractory metal compound layer at the interface between the electrode metal and the insulating film in the above-mentioned invention.
【００１１】[0011]
【作用】本発明においては、容量素子の絶縁物層にバイ
アスＥＣＲプラズマＣＶＤ法による絶縁膜を用いること
により、通常のＣＶＤ法による絶縁膜より良質の膜が得
られるため薄膜化が可能となる。また、このバイアスＥ
ＣＲプラズマＣＶＤ法は200 ℃以下の低温で形成できる
ため、金属配線のマイグレーションを減少でき、容量素
子としての歩留や信頼性を向上させることができる。さ
らに、本発明の別の発明においては、金属配線の絶縁膜
に接する部分を高融点金属あるいは高融点金属化合物と
することによって、金属配線のマイグレーションを更に
減少させることができる。In the present invention, by using the insulating film formed by the bias ECR plasma CVD method as the insulating layer of the capacitive element, a film having a better quality than the insulating film formed by the normal CVD method can be obtained, so that the film can be thinned. Also, this bias E
Since the CR plasma CVD method can be formed at a low temperature of 200 ° C. or lower, migration of metal wiring can be reduced and the yield and reliability as a capacitive element can be improved. Furthermore, in another invention of the present invention, the migration of the metal wiring can be further reduced by forming the portion of the metal wiring in contact with the insulating film with a refractory metal or a refractory metal compound.
【００１２】[0012]
【実施例】図１は本発明による容量素子の第１の実施例
を示す構造断面図である。同図において、１０はシリコ
ン基板１６上に形成された絶縁層、１１はこの絶縁層１
０上に選択的に形成された第１の金属配線層であり、１
２は第２の金属配線層である。これら金属配線層１１，
１２は通常のＬＳＩ製造工程において用いられるアルミ
合金系（例えば微量のＣｕ，Ｓｉとアルミの合金等）で
ある。1 is a structural sectional view showing a first embodiment of a capacitor according to the present invention. In the figure, 10 is an insulating layer formed on the silicon substrate 16, and 11 is this insulating layer 1.
0 is a first metal wiring layer selectively formed on
2 is a second metal wiring layer. These metal wiring layers 11,
Reference numeral 12 is an aluminum alloy system used in a normal LSI manufacturing process (for example, a trace amount of Cu, an alloy of Si and aluminum, etc.).
【００１３】また、１３は第１と第２の金属配線層１
１，１２間に設けられた絶縁膜であり、この絶縁膜１３
は第１の金属配線層１１上の所望位置に容量素子を形成
するために層間絶縁膜１４をエッチング除去して開口部
１５を形成した後，その上にバイアスＥＣＲプラズマＣ
ＶＤ法により形成されたシリコン酸化膜あるいはシリコ
ン窒化膜である。このバイアスＥＣＲプラズマＣＶＤ法
は200 ℃以下の低温、１０-5 〜１０-3 Ｔｏｒｒの低圧
下において絶縁膜を形成できるためにシリコン単結晶の
熱酸化膜に近い良質の酸化膜や窒化膜を得ることができ
る。その酸化膜の電流−電圧特性の一例を図２に示す。Further, 13 is the first and second metal wiring layers 1
And an insulating film provided between the first and the second insulating films.
Removes the interlayer insulating film 14 by etching to form a capacitive element at a desired position on the first metal wiring layer 11, forms an opening 15, and then forms a bias ECR plasma C on the opening 15.
It is a silicon oxide film or a silicon nitride film formed by the VD method. In this bias ECR plasma CVD method, an insulating film can be formed at a low temperature of 200 ° C. or lower and a low pressure of 10 −5 to 10 −3 Torr, so that a high quality oxide film or nitride film close to a thermal oxide film of silicon single crystal is obtained. be able to. An example of the current-voltage characteristics of the oxide film is shown in FIG.
【００１４】図２はバイアスＥＣＲプラズマＣＶＤ法に
より形成した酸化膜の特性２１を他の絶縁膜と比較して
示したものであり、図２より、図９に示した従来のＣＶ
Ｄ法による酸化膜より高電界でも低い電流を示してお
り、絶縁特性に優れていることが明らかである。また形
成温度が200 ℃以下であるため、絶縁膜形成時のアルミ
系金属配線のマイグレーションが生じにくいことから、
容量素子としての耐圧劣化が生じにくい利点を有する。FIG. 2 shows characteristics 21 of the oxide film formed by the bias ECR plasma CVD method in comparison with other insulating films. From FIG. 2, the conventional CV shown in FIG. 9 is shown.
It shows a lower current even in a higher electric field than the oxide film by the D method, and it is clear that the insulating property is excellent. In addition, since the formation temperature is 200 ° C or less, migration of aluminum-based metal wiring during the formation of the insulating film is less likely to occur,
It has an advantage that the breakdown voltage of the capacitor is not easily deteriorated.
【００１５】図３は本発明の第２の実施例を示す構造断
面図である。この実施例において図１のものと異なるの
は、容量素子の電極を構成する第１及び第２の金属配線
層１１，１２とその絶縁膜１３との接する界面部分にそ
れぞれ高融点金属層１７，１８あるいは高融点金属化合
物層を設けたことである。なお、図中同一符号は同一ま
たは相当部分を示している。FIG. 3 is a structural sectional view showing a second embodiment of the present invention. This embodiment is different from that shown in FIG. 1 in that the refractory metal layers 17 and 12 are respectively formed at the interfaces between the first and second metal wiring layers 11 and 12 forming the electrodes of the capacitive element and the insulating film 13. 18 or a refractory metal compound layer is provided. The same reference numerals in the drawings indicate the same or corresponding parts.
【００１６】この実施例の構造によると、チタンやタン
グステン等の高融点金属あるいは窒化チタン等の高融点
金属化合物はアルミ合金に比して熱による変形が生じに
くいことから、バイアスＥＣＲプラズマＣＶＤ法の低温
で絶縁膜１３が形成できる特徴と相俟って、より高性能
の容量素子の形成が可能となる特徴を有する。According to the structure of this embodiment, the refractory metal such as titanium or tungsten or the refractory metal compound such as titanium nitride is less likely to be deformed by heat than the aluminum alloy. Combined with the feature that the insulating film 13 can be formed at a low temperature, it has a feature that a higher performance capacitor element can be formed.
【００１７】なお、本発明は図３の実施例のものに限ら
ず、第１の金属配線層１１あるいは第２の金属配線層１
２の少なくともどちらか一方の絶縁層１３に接する部分
に高融点金属あるいは高融点金属化合物層を設けても同
様の効果が得られる。また、金属配線層全体が高融点金
属でも良いことは明らかである。The present invention is not limited to the embodiment shown in FIG. 3, but is not limited to the first metal wiring layer 11 or the second metal wiring layer 1.
The same effect can be obtained by providing a refractory metal or refractory metal compound layer in a portion in contact with at least one of the two insulating layers 13. Further, it is clear that the entire metal wiring layer may be made of a refractory metal.
【００１８】図４は本発明の第１の実施例の構造を実現
する製法の一例を示す主要工程の断面図である。本実施
例では、まず図４(a) に示すように、絶縁層１０上に第
１の金属配線層１１を選択的に形成した後、層間絶縁膜
１４をＣＶＤ法等により形成する。次いで図４(b) に示
すように、容量素子を形成する領域２０の層間絶縁膜１
４を選択的に除去して開口部１５を形成した後、その上
にバイアスＥＣＲプラズマＣＶＤ法により容量素子に使
用するシリコン酸化膜等の絶縁膜１３を形成する。FIG. 4 is a cross-sectional view of main steps showing an example of a manufacturing method for realizing the structure of the first embodiment of the present invention. In this embodiment, first, as shown in FIG. 4A, the first metal wiring layer 11 is selectively formed on the insulating layer 10, and then the interlayer insulating film 14 is formed by the CVD method or the like. Next, as shown in FIG. 4B, the interlayer insulating film 1 in the region 20 where the capacitive element is to be formed.
After selectively removing 4 to form an opening 15, an insulating film 13 such as a silicon oxide film used for a capacitive element is formed thereon by a bias ECR plasma CVD method.
【００１９】この時、バイアスＥＣＲプラズマＣＶＤ法
は、電子サイクロトロン共鳴法によりプラズマを生成
し、薄膜を形成するとともに基板ホルダーにｒｆバイア
スを印加しスパッタエッチングにより平坦化及び膜質改
善を行う方法であり、ガス圧１０-5〜１０-3Ｔｏｒｒの
低圧で、200 ℃以下の低温で良質の薄膜を形成すること
が可能である。At this time, the bias ECR plasma CVD method is a method of generating plasma by an electron cyclotron resonance method to form a thin film, applying an rf bias to a substrate holder, and performing flattening and film quality improvement by sputter etching. It is possible to form a good quality thin film at a low temperature of 200 ° C. or lower at a low gas pressure of 10 −5 to 10 −3 Torr.
【００２０】本実施例では、マイクロ波パワー700Ｗ，
ｒｆパワー200Ｗ，ＳｉＨ4とＯ2を用いてガス圧1.0 ｍ
Ｔｏｒｒの条件のもとにシリコン酸化膜を形成した。ｒ
ｆパワーは主として平坦化のために行うため印加する必
要は特にない場合もある。次に図４(c) に示すように、
第１層配線と第２層配線を接続するためのスルーホール
１９を所定の位置に開孔し、しかる後、第２の金属配線
層１２を形成する。これにより、本発明の第１の実施例
に示す容量素子構造が実現できる。In this embodiment, the microwave power is 700 W,
rf power 200W, gas pressure 1.0m using SiH 4 and O 2
A silicon oxide film was formed under the conditions of Torr. r
Since the f-power is mainly used for flattening, it may not be necessary to apply it. Next, as shown in Fig. 4 (c),
A through hole 19 for connecting the first layer wiring and the second layer wiring is opened at a predetermined position, and then the second metal wiring layer 12 is formed. As a result, the capacitive element structure shown in the first embodiment of the present invention can be realized.
【００２１】図５は本発明の第２の実施例の構造を実現
するための製法の一例を示す主要工程の断面図である。
図４に示した実施例と異なるのは、第１の金属配線層１
１の少なくとも上部が高融点金属層１７あるいは高融点
金属化合物層となっている点にあり、高融点金属として
はチタン，タングステンあるいはモリブデン等が使用で
き、化合物としては前記高融点金属の窒化物，酸化物等
が使用できる。また、第２の金属配線層１２についても
その下部の容量素子用の絶縁膜１３と接する部分が前記
高融点金属層１８あるいは高融点金属化合物層となって
いる点に特徴がある。なお、図５において図４と同一部
分は同一符号を記してある。FIG. 5 is a cross-sectional view of main steps showing an example of a manufacturing method for realizing the structure of the second embodiment of the present invention.
The difference from the embodiment shown in FIG. 4 is that the first metal wiring layer 1
At least the upper part of 1 is a refractory metal layer 17 or a refractory metal compound layer, titanium, tungsten, molybdenum or the like can be used as the refractory metal, and the compound is a nitride of the refractory metal, Oxides and the like can be used. In addition, the second metal wiring layer 12 is also characterized in that the portion below the second metal wiring layer 12 which is in contact with the insulating film 13 for the capacitive element is the refractory metal layer 18 or the refractory metal compound layer. In FIG. 5, the same parts as those in FIG. 4 are designated by the same reference numerals.
【００２２】[0022]
【発明の効果】以上説明したように本発明は、容量素子
の構造として絶縁層にバイアスＥＣＲプラズマＣＶＤ法
による絶縁膜を用いることにより、従来のＣＶＤ法によ
る絶縁膜に比して良質の膜が得られるため薄膜化が可能
となる。このため単位面積当たりの容量が大きく得ら
れ、容量素子の微細化すなわち高密度化が可能となる利
点を有する。また、バイアスＥＣＲプラズマＣＶＤ法は
200 ℃以下の低温で形成できるため、金属配線のマイグ
レーションを減少できることから、容量素子としての歩
留，信頼性を向上させることが可能となる。As described above, according to the present invention, by using the insulating film by the bias ECR plasma CVD method for the insulating layer as the structure of the capacitive element, a film of higher quality can be obtained as compared with the insulating film by the conventional CVD method. Since it is obtained, thinning is possible. Therefore, a large capacitance per unit area can be obtained, and there is an advantage that the capacitance element can be miniaturized, that is, high density can be achieved. In addition, the bias ECR plasma CVD method
Since it can be formed at a low temperature of 200 ° C. or less, migration of metal wiring can be reduced, so that the yield and reliability as a capacitive element can be improved.
【００２３】本発明の別の発明は、容量素子の電極を構
成する金属配線層の絶縁膜に接する部分に高融点金属あ
るいは高融点金属化合物層を設けることにより、金属配
線のマイグレーションをさらに減少させ得るため、より
高信頼性を有する容量素子を実現することが可能とな
る。しかも、本発明では容量素子の電極はいずれも金属
配線を用いているために低抵抗であり、高信頼性にも優
れた容量素子を実現できる。これらの特徴により本発明
により実現される容量素子は高速性，高密度性ともに高
信頼性に優れた構造を提供することが可能となる。Another aspect of the present invention is to further reduce migration of metal wiring by providing a refractory metal or a refractory metal compound layer in a portion of the metal wiring layer constituting the electrode of the capacitive element in contact with the insulating film. Therefore, it is possible to realize a capacitive element having higher reliability. Moreover, in the present invention, since the electrodes of the capacitive element are all made of metal wiring, the capacitive element has low resistance and is highly reliable. Due to these characteristics, the capacitive element realized by the present invention can provide a structure which is excellent in both high speed and high density.
【図１】本発明の第１の実施例を示す構造断面図であ
る。FIG. 1 is a structural sectional view showing a first embodiment of the present invention.
【図２】本実施例におけるバイアスＥＣＲプラズマＣＶ
Ｄ法で形成した酸化膜と通常の絶縁膜との電流−電圧特
性を対比して示した図である。FIG. 2 is a bias ECR plasma CV in this embodiment.
It is the figure which compared and showed the current-voltage characteristic of the oxide film formed by D method, and the normal insulating film.
【図３】本発明の第２の実施例を示す構造断面図であ
る。FIG. 3 is a structural cross-sectional view showing a second embodiment of the present invention.
【図４】図１の実施例を実現する製法の一例を示す主要
工程の断面図である。FIG. 4 is a sectional view of a main process showing an example of a manufacturing method for realizing the embodiment of FIG.
【図５】図３の実施例を実現する製法の一例を示す主要
工程の断面図である。FIG. 5 is a cross-sectional view of main steps showing an example of a manufacturing method for realizing the embodiment of FIG.
【図６】従来技術の一例を示す構造断面図である。FIG. 6 is a structural cross-sectional view showing an example of a conventional technique.
【図７】従来技術の別の例を示す構造断面図である。FIG. 7 is a structural cross-sectional view showing another example of the prior art.
【図８】従来技術のさらに別の例を示す構造断面図であ
る。FIG. 8 is a structural sectional view showing still another example of the prior art.
【図９】通常の各種絶縁膜の電流−電圧特性を対比して
示した図である。FIG. 9 is a diagram showing current-voltage characteristics of various ordinary insulating films for comparison.
１０ 絶縁層 １１ 第１の金属配線層 １２ 第２の金属配線層 １３ 容量素子の絶縁膜（シリコン酸化膜） １４ 層間絶縁膜 １５ 開口部 １６ シリコン基板 １７，１８ 高融点金属層 DESCRIPTION OF SYMBOLS 10 Insulating layer 11 1st metal wiring layer 12 2nd metal wiring layer 13 Insulating film (silicon oxide film) of a capacitive element 14 Interlayer insulating film 15 Opening 16 Silicon substrate 17,18 Refractory metal layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 尾崎 義治 東京都千代田区内幸町１丁目１番６号 日 本電信電話株式会社内 (72)発明者 三浦 賢次 東京都千代田区内幸町１丁目１番６号 日 本電信電話株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshiharu Ozaki, 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (72) Kenji Miura 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation
Claims (2)
と、その上部に形成された絶縁膜と、さらにその上部に
形成された第２の金属配線層からなり、前記絶縁膜はバ
イアスＥＣＲプラズマＣＶＤ法により形成された絶縁膜
であることを特徴とする容量素子。1. A first metal wiring layer formed on a substrate, an insulating film formed on the first metal wiring layer, and a second metal wiring layer further formed on the first metal wiring layer, wherein the insulating film is a bias. A capacitive element, which is an insulating film formed by an ECR plasma CVD method.
上部の前記絶縁膜と接する部分，あるいは第２の金属配
線層の下部の前記絶縁膜と接する部分の少なくとも一方
に、高融点金属あるいは高融点金属化合物層を設けたこ
とを特徴とする容量素子。2. The refractory metal according to claim 1, wherein at least one of a portion of the first metal wiring layer that is in contact with the insulating film and a portion of the second metal wiring layer that is in contact with the insulating film is a refractory metal. Alternatively, a capacitor having a high melting point metal compound layer is provided.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4125508A JP2707017B2 (en) | 1992-04-20 | 1992-04-20 | Capacitive element |
| US08/034,906 US5674771A (en) | 1992-04-20 | 1993-03-22 | Capacitor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4125508A JP2707017B2 (en) | 1992-04-20 | 1992-04-20 | Capacitive element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05299582A true JPH05299582A (en) | 1993-11-12 |
| JP2707017B2 JP2707017B2 (en) | 1998-01-28 |
Family
ID=14911869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4125508A Expired - Lifetime JP2707017B2 (en) | 1992-04-20 | 1992-04-20 | Capacitive element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2707017B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5913126A (en) * | 1996-11-06 | 1999-06-15 | Samsung Electronics Co., Ltd. | Methods of forming capacitors including expanded contact holes |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03203261A (en) * | 1989-12-28 | 1991-09-04 | Sony Corp | Semiconductor device |
| JPH0425128A (en) * | 1990-05-21 | 1992-01-28 | Fuji Electric Co Ltd | Formation of insulating film |
-
1992
- 1992-04-20 JP JP4125508A patent/JP2707017B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03203261A (en) * | 1989-12-28 | 1991-09-04 | Sony Corp | Semiconductor device |
| JPH0425128A (en) * | 1990-05-21 | 1992-01-28 | Fuji Electric Co Ltd | Formation of insulating film |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5913126A (en) * | 1996-11-06 | 1999-06-15 | Samsung Electronics Co., Ltd. | Methods of forming capacitors including expanded contact holes |
| US5949100A (en) * | 1996-11-06 | 1999-09-07 | Samsung Electronics Co., Ltd. | Integrate circuit device including expanded contact holes and related structures |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2707017B2 (en) | 1998-01-28 |
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